Abstract: A semiconductor device includes: a package; two semiconductor chip fixing parts located adjacently to each other in the package; and first and the second semiconductor chips, each of which is fixed on the semiconductor chip fixing part and has a field effect transistor formed therein. A gate lead G1, a source lead S1, and a drain lead D2 are arranged from left to right on the first surface of the package and a drain lead D1, a source lead S2, and a gate lead G2 are arranged from left to right on the second surface. A gap between the source lead S1 and the drain lead D2 is two times a gap between the gate lead G1 and the source lead S1, and a gap between the drain lead D1 and the source lead S2 is two times a gap between the source lead S2 and the gate lead G2.

Abstract: A lateral conduction Schottky diode includes multiple mesa regions upon which Schottky contacts are formed and which are at least separated by ohmic contacts to reduce the current path length and reduce current crowding in the Schottky contact, thereby reducing the forward resistance of a device. The multiple mesas may be isolated from one another and have sizes and shapes optimized for reducing the forward resistance. Alternatively, some of the mesas may be finger-shaped and intersect with a central mesa or a bridge mesa, and some or all of the ohmic contacts are interdigitated with the finger-shaped mesas. The dimensions of the finger-shaped mesas and the perimeter of the intersecting structure may be optimized to reduce the forward resistance. The Schottky diodes may be mounted to a submount in a flip chip arrangement that further reduces the forward voltage as well as improves power dissertation and reduces heat generation.

Abstract: A small semiconductor package having two electrodes, which can be produced at reduced cost and which features high reliability. The package has a structure in which an anode and a cathode are arranged on one surface of a semiconductor chip, each electrode having a bump electrode for connecting the electrode to an external substrate. An insulating resin is provided on the surface of the semiconductor chip and on the surfaces of the bump electrodes, except at least for the connection portions to the external substrate.

Abstract: An InGaAs/GaAs High Electron Mobility Transistor (HEMT) comprises a buffer layer, a main conducting channel, an InGaAs/GaAs thickness-graded superlattice structure, a mono atom ?-doped carrier supply layer, a Schottky cap layer of gate electrode and an Ohmic cap layer of drain electrode and source electrode which are formed successively on a substrate. The superlattice structure comprises spacer and sub-channel. By using thickness-graded superlattice spacer structure is able to ameliorate lattice-mismatch-induced scattering within heterostucture interfacial, increase range of gate voltage swing in gate electrode, and through real-space transfer generated by bias voltage in high electric field, drain-to-source saturation current proceed step-up phenomenon to forming a HEMT having scalable voltage multi-extrinsic transconductance enhanced portions.

Abstract: In a method of forming a semiconductor device with a first channel layer formed over a portion of a second channel layer, a portion of the second channel underlying the first channel is etched so as to form an overhanging ledge in the first channel, and then a metallic contact disposed on top of the ledge portion is diffused into the first channel by ohmic alloying to form an electrode in the first channel.

Abstract: A Schottky diode includes a semiconductor substrate made of 4H—SiC, an epitaxially grown 4H—SiC layer, an ion implantation layer, a Schottky electrode, an ohmic electrode, and an insulative layer made of a thermal oxide film. The Schottky electrode and the insulative layer are not in contact with each other, with a gap being provided therebetween, whereby an altered layer does not occur. Therefore, it is possible to suppress the occurrence of a leak current.

Abstract: A semiconductor device having grooves uniformly filled with semiconductor fillers is provided. Both ends of each of narrow active grooves are connected to an inner circumferential groove surrounding the active grooves. The growth speed of semiconductor fillers on both ends of the active grooves becomes equal to that at their central portions. As a result, a semiconductor device having the active grooves filled with the semiconductor fillers at a uniform height is obtained.

Abstract: A semiconductor switching device includes a plurality of metal layers. At least one of the metal layers forming a Schottky junction with a semi-insulating substrate or an insulating layer on a substrate. The device also includes an impurity diffusion region, and a high-concentration impurity region formed between two of the metal layers or between one of the metal layers and the impurity diffusion region so as to suppress expansion of a depletion layer from the corresponding metal layer.

Abstract: A good interface characteristic can be maintained, and a leakage current of a dielectric film can be decreased. A semiconductor device according to one aspect of the present invention includes: a semiconductor substrate; a gate dielectric film containing at least nitrogen and a metal, the gate dielectric film being formed on the semiconductor substrate, and including a first layer region contacting the semiconductor substrate, a second layer region located at a side opposite to that of the first layer region in the gate dielectric film, and a third layer region located between the first and second layer regions, a maximum value of a nitrogen concentration in the third layer region being higher than maximum values thereof in the first and second layer regions; a gate electrode contacting the second layer region; and a pair of source and drain regions formed at both sides of the gate dielectric film in the semiconductor substrate.

Abstract: SiC MESFETs are disclosed which utilize a semi-insulating SiC substrate which substantially free of deep-level dopants. Utilization of the semi-insulating substrate may reduce back-gating effects in the MESFETs. Also provided are SiC MESFETs with a two recess gate structure. MESFETS with a selectively doped p-type buffer layer are also provided. Utilization of such a buffer layer may reduce output conductance by a factor of 3 and produce a 3 db increase in power gain over SiC MESFETs with conventional p-type buffer layers. A ground contact may also be provided to the p-type buffer layer and the p-type buffer layer may be made of two p-type layers with the layer formed on the substrate having a higher dopant concentration. SiC MESFETs according to embodiments of the present invention may also utilize chromium as a Schottky gate material. Furthermore, an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs.

Abstract: An extracting transistor (10)—an FET—includes a conducting channel extending via a p-type InSb quantum well (22) between p-type InAlSb layers (20, 24) of wider band-gap. One of the InAlSb layers (24) incorporates an ultra-thin n-type &dgr;-doping layer (28) of Si, which provides a dominant source of charge carriers for the quantum well (22). It bears n+ source and drain electrodes (30a, 30b) and an insulated gate (30c). The other InAlSb layer (20) adjoins a barrier layer (19) of still wider band-gap upon a substrate layer (14) and substrate (16) with electrode (18). Biasing one or both of the source and drain electrodes (30a, 30b) positive relative to the substrate electrode (18) produces minority carrier extraction in the quantum well (22) reducing its intrinsic contribution to conductivity, taking it into an extrinsic saturated regime and reducing leakage current.

Abstract: A GaN-based Schottky diode includes a sapphire substrate on which are formed a GaN buffer layer, an n+-type GaN layer, and an n-type GaN layer that has a surface portion thereof shaped to form a protrusion having an upper face with which a Ti electrode forms a Schottky junction and a side face with which a Pt electrode forms a Schottky junction through an Al0.2Ga0.8N layer. A cathode electrode constituted by a TaSi layer forms an ohmic junction with the n+-type GaN layer. The Ti and Pt electrodes constitute a combined anode electrode contributing to increasing a withstand voltage of and decreasing an on-voltage of the Schottky diode.

Abstract: A vertical JFET architecture. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is disposed over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET.

Abstract: A device includes an element (e.g. in the shape of a sleeve) and a core located in an interior volume defined by the element and at least partially surrounded by the element. The element has two portions: one portion overlaps at least a region of the core thereby to form a capacitor, while another portion surrounds the core thereby to form an inductor. The device may further include an additional capacitor formed by another element that is separated from the core but overlaps at least a region of the core when viewed in a direction perpendicular to the core. The two elements substantially surround the core. The core may be used to hold charge in a non-volatile manner, even when no power is supplied to the device.

Abstract: A compound semiconductor device includes a gate electrode, a drain electrode, and a source electrode, and a p-type semiconductor layer provided between the gate electrode and the drain electrode. The p-type semiconductor layer has a lower acceptor concentration on a drain side thereof than that on a gate side thereof.

Abstract: The present invention provides a mask for use in forming a thin-layer pattern of an organic electroluminescence element having high-precision pixels. The mask is manufactured by wet-etching a (100) silicon wafer (single crystal silicon substrate) in a crystal orientation-dependent anisotropic fashion so as to form through-holes having (111)-oriented walls serving as apertures corresponding to a thin-layer pattern to be formed.

Abstract: The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 &mgr;m for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 &mgr;m or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 &mgr;m or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer.

Abstract: A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 &mgr;m and a signal receiving FET has a gate width of 400 &mgr;m. A resistor connecting a gate electrode and a control terminal of the signal transmitting FET is tightly configured to provide expanding space for the FET. Despite the reduced size, the switching device can allow a maximum power of 22.5 dBm to pass through because of the asymmetrical device design. The switching device operates at frequencies of 2.4 GHz or higher without use of shunt FET.

Abstract: Multiple sample introduction means have been configured in Atmospheric Pressure Ion sources which are interfaced to mass analyzers. Different samples can be introduced through multiple Electrospray (ES) or Atmospheric Pressure Chemical Ionization (APCI) probes individually or simultaneously and ionized. The gas phase ion mixture resulting from individual solutions sprayed from multiple ES or APCI probe inputs is mass analyzed. In this manner a calibration solution can be introduced through one ES or APCI probe while one or more sample solutions are spray from additional probes. Simultaneous spraying of calibration and sample solutions, results in an acquired mass spectrum containing peaks of ions with known molecular weights as well as sample related peaks. The calibration peaks can be used as an internal calibration standard during data analysis.

Abstract: A ferroelectric transistor is disclosed which has two source/drain regions and a channel region disposed in between in a semiconductor substrate. A metallic intermediate layer is disposed on the surface of the channel region and forms a Schottky diode with the semiconductor substrate, and a ferroelectric layer and a gate electrode are disposed on its surface. The ferroelectric transistor is fabricated using steps appertaining to silicon process technology.

Abstract: A Schottky barrier diode and process of making is disclosed. The process forms a metal contact pattern in masked areas on a silicon carbide wafer. A preferred embodiment includes on insulating layer that is etched in the windows of the mask. An inert edge termination is implanted into the wafer beneath the oxide layer and adjacent the metal contacts to improve reliability. A further oxide layer may be added to improve surface resistance to physical damage.

Abstract: In some embodiments, a circuit structure comprises a semiconductor substrate, an opening passing through the substrate between a first side of the substrate and a second side of the substrate, and a plurality of conductive layers in the opening. In some embodiments, one conductive layer provides an electromagnetic shield that shields the substrate from AC signals carried by a contact pad made from another conductive layer on a backside of the substrate. The conductive layers can also be used to form capacitor/rectifier networks. Manufacturing methods are also provided.

Abstract: A semiconductor switching device of mirror logic includes two FETs having a gate width of 600 &mgr;m, a common input terminal, two control terminal and two output terminals. The resistors connecting the control terminals and the gate electrodes of FETs are placed underneath a pad metal layer extending from the common input terminal. Both FETs extend into the space between the control terminals and the output terminals. The device can be housed in the same package as the device of non-mirror logic.

Abstract: A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.

Abstract: An enhancement mode FET device (10) that employs a strained N-doped InAlAs charge shield layer (22) disposed on an intrinsic InAlAs barrier layer (20). A gate metal electrode (38) of the FET device (10) is controllably diffused through a recess (36) into the shield layer (22) to the barrier layer (20). The resulting enhancement mode device (10) provides an excellent Schottky barrier with a high barrier height that inhibits undesirable surface depletion effects through charge shielding by the shield layer (22) in the regions between the recess edge and the gate metal. Minimizing surface depletion effects makes the device more robust by making the surface less sensitive to processing conditions and long-term operation effects.

Abstract: An insulating-gate semiconductor device has a first nitride semiconductor layer formed over a substrate and an insulating oxidation layer obtained by oxidizing a second nitride semiconductor layer formed on the first nitride semiconductor layer. A gate electrode is formed on the insulating oxidation layer.

Abstract: A switching circuit device has a first FET and a second FET, and operates with single control terminal. The device also has a common input terminal connected to the drain or source electrode of the two FETs, a first output terminal and a second output terminal connected to the source or the drain electrode of the respective FET, a bias element applying an bias to the first output terminal, a first connection connecting the control terminal to the second FET, a second connection connecting the gate of the second FET to the ground, and a direct current isolation element placed between the two FETs. The device is housed in a MCP6 package with six pins.

Abstract: A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface. Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices.

Abstract: A field effect transistor includes (a) a semi-insulating GaAs substrate, (b) a step-doped structured active layer including an n type GaAs layer deposited on the substrate, and an n− type GaAs layer or a non-doped GaAs layer deposited on the n type GaAs layer, the n− type GaAs layer or non-doped GaAs layer being formed with at least one recess, and (c) a gate electrode formed in the recess so that the gate electrode is oriented in such a direction that drain current runs in the active layer along crystal orientation [01(−1)]. The field effect transistor enhances linearity of transfer conductance, and further improves strain characteristic.

Abstract: There is disclosed a semiconductor device in which a device isolating insulating film is formed in a periphery of a device region of a semiconductor silicon substrate device region. A side wall insulating film formed of a silicon nitride film is formed to cover the periphery of a channel region on the silicon substrate. A Ta2O5 film, and a metal gate electrode are formed inside a trench whose side wall is formed of the side wall insulating film. An interlayer insulating film is formed on the device isolating insulating film. A Schottky source/drain formed of silicide is formed on the silicon substrate in a bottom portion of the trench whose side wall is formed of the side wall insulating film and interlayer insulating film. A source/drain electrode is formed on the Schottky source/drain.

Abstract: A silicon carbide vertical field-effect transistor is provided wherein a first conductivity type drift layer formed of silicon carbide is laminated on a first conductivity type silicon carbide drain layer, and a second conductivity type gate region and a first conductivity type source region are formed in selected portions of a surface layer of the first conductivity type drift layer, such that the gate and source regions are spaced from each other, while a second conductivity type embedded region is formed in a selected portion of the drift layer below the gate region and source region, such that the embedded region is not connected to the source region. A second conductivity type contact region that is in contact with the embedded region is short-circuited to a gate electrode that is formed on the gate region, so that the potential of the embedded region is made equal to that of the gate region. A method for manufacturing such a silicon carbide vertical FET is also disclosed.

Abstract: A method for forming an interconnect wiring structure, such as a fuse structure, comprises forming an opening in an insulating layer using a phase shift mask (the opening having vertical sidewalls sloped sidewalls and horizontal surfaces), depositing a conductive material in the opening and removing the conductive material from the sloped sidewalls and horizontal surfaces, wherein the conductive material remains on the vertical sidewalls as fuse links.

Abstract: A method of making an inductor and the inductor. The inductor comprises a plurality of serially connected transistors at least partially formed in a substrate, preferably a silicon on insulator substrate, and comprises a gate common to the plurality of transistors. The plurality of transistors, transistor contacts, and electrical interconnects form the coil of the inductor and the gate common to the plurality of transistors forms the core of the inductor. Two inductors of the invention are magnetically coupled to form a transformer of the invention. A control transistor is serially connected to the primary inductor of the transformer. The control transistor is gated by a periodic output signal of a ring oscillator. An actuation and a deactuation of the control transistor allows the current in the primary coil to vary creating a changing magnetic flux in the primary and secondary cores and inducing a fluctuating current in the secondary coil.

Abstract: The present invention provides a method of forming a gate recess in an insulating film on a substrate for depositing a gate electrode film being in contact with a part of the substrate and also extending at least within the gate recess.

Abstract: Devices with Schottky junctions are manufactured in that a semiconductor body with a substrate is provided with a first, for example n-type semiconductor region in the form of an epitaxial layer. A Schottky metal is locally provided thereon. A second semiconductor region is advantageously formed directly below the Schottky metal, with the purpose of adjusting the level of the Schottky barrier. Around this, a third semiconductor region is formed in the first region at at least two sides, which third region is then of the p-conductivity type and, when it entirely surrounds the second region, forms a so-called guard ring. A disadvantage of the above known method is that the devices obtained thereby have a (forward) current-voltage characteristic which is not very well controllable and reproducible. This hampers mass manufacture.

Abstract: A first electrode layer composed of Pt is formed on an operating layer, and a second electrode layer composed of a material which is different from Pt is formed on the operating layer so as to cover the first electrode layer. A buried electrode layer composed of Pt is formed in the operating layer under the first electrode layer. The first electrode layer, the second electrode layer and the buried electrode layer constitute a gate electrode.

Abstract: A MESFET has a metallic laminate including WSi.sub.x, Ti, Pt and Au films and implementing gate, source and drain electrodes of the MESFET and interconnects therefor. The substrate of the MESFET is formed of a substrate body, a first semiconductor layer made of n.sup.+ -GaAs doped with Si at a concentration of 2.times.10.sup.18 atoms/cm.sup.3 and a second semiconductor layer made of n.sup.+ -InGaAs doped with Si at a concentration of 1.times.10.sup.19 atoms/cm.sup.3. The source and drain electrodes contact the second semiconductor layer in an ohmic contact while the gate electrode contacts the first semiconductor layer in a Schottky contact through a hole formed in the second semiconductor layer. A reduced number of steps in manufacture of the MESFET can be obtained, thereby reducing fabrication costs of the MESFET.

Abstract: A composite-layer semiconductor device includes a gate above a host substrate, an n++ contact layer above the gate, and source and drain ohmic contacts applied to the n++ contact layer. The source and drain ohmic contacts define a central gate location which is recessed through the n++ contact layer toward the gate. The source and drain ohmic contacts create a barrier to chemical etching so that a current path below the central gate location can be incrementally recessed in repeated steps to precisely tailor the operating mode of the device for depletion or enhancement applications. The composite-layer semiconductor device is fabricated by depositing a gate on an n++ contact layer above a semi-insulating substrate. The semi-insulating substrate and gate are flipped onto an epoxy layer on the host substrate so that the gate is secured to the epoxy layer and the semi-insulating substrate presents an exposed backside. A portion of the exposed backside is removed.

Abstract: A compound semiconductor transistor has a structure in which a first insulating film is formed only under a overhang of a gate electrode an upper part of which is formed widely, and a second insulating film for threshold voltage adjustment is formed on the side of a gate electrode and the first insulating film.

Abstract: A method of making an inductor and the inductor. The inductor comprises a plurality of serially connected transistors at least partially formed in a substrate, preferably a silicon on insulator substrate, and comprises a gate common to the plurality of transistors. The plurality of transistors, transistor contacts, and electrical interconnects form the coil of the inductor and the gate common to the plurality of transistors forms the core of the inductor. Two inductors of the invention are magnetically coupled to form a transformer of the invention. A control transistor is serially connected to the primary inductor of the transformer. The control transistor is gated by a periodic output signal of a ring oscillator. An actuation and a deactuation of the control transistor allows the current in the primary coil to vary creating a changing magnetic flux in the primary and secondary cores and inducing a fluctuating current in the secondary coil.

Abstract: In a body driven SOIMOSFET, a semiconductor layer extends over the insulator and comprises a first conductivity type high impurity concentration diffusion layer, a low impurity concentration region and another first conductivity type high impurity concentration diffusion layer which are in this order connected with each other. A second conductivity type high impurity concentration semiconductor layer is formed in contact with a top of the low impurity concentration region. A bottom electrode is formed within the insulation layer so that the bottom electrode is surrounded by the insulation layer. The bottom electrode is positioned under the low impurity concentration region and being separated by the insulation layer from the low impurity concentration region. It is important that the bottom electrode does not extend under the first conductivity high impurity concentration regions.

Abstract: A semiconductor device includes an ohmic electrode and a Schottky electrode respectively carrying interconnection patterns with intervening adhesion layer and a diffusion barrier layer, wherein the Schottky electrode further includes a metal layer that prevents a reaction between the Schottky electrode and the diffusion barrier layer such that the metal layer is interposed between the top surface of the Schottky electrode and adhesion layer for increasing the distance between the diffusion barrier layer and the Schottky electrode.

Abstract: A multi-layered wiring structure includes a lower wiring having an upper surface, a first inter-level insulating layer having a first flat upper surface substantially coplanar with the upper surface of the lower conductive wiring and a recess contiguous to the first flat upper surface, a spin-on-glass layer filling the recess and having a second flat upper surface substantially coplanar with the first flat upper surface, a second inter-level insulating layer covering the first and second flat surfaces and the upper surface of the lower conductive wiring and an upper conductive wiring extending on the second inter-level insulating layer and passing through a contact hole of the second inter-level insulating layer so as to be held in contact with the lower conductive wiring, and the first and second flat upper surfaces are created through an etch-back using gaseous etchant equally etching the first inter-level insulating layer and the spin-on-glass layer, thereby creating smooth surface under the second inter-l

Abstract: The object of the invention is a field-effect transistor comprising a drain (D) and a source (S) and a gate (G) with a determined width (W) and length (L), equipped with means (G1-G2) for generating a voltage distribution on the gate in direction of its width. The gate comprises a first end in direction of its width and a second end essentially opposite to the first end, and that a first gate contact (G1) is arranged at the first end for providing a first voltage (V.sub.G1) to the first end, and a second gate contact (G2) is arranged at the second end for providing a second voltage (V.sub.G2) to the second end, for generating a voltage distribution on the gate in direction of its width with the help of a difference voltage (V.sub.G1 -V.sub.G2) between the first (G1) and the second (G2) gate contact. On the basis of the first (V.sub.G1) and second (V.sub.

Abstract: A field effect transistor structure having a first type conductivity semiconductor body disposed on an insulator and having formed in different regions of the semiconductor, a source region and a drain region of the opposite type conductivity to the first type, a gate electrode adapted to control a flow of carriers in a channel through the semiconductor body between the source and drain regions, and a Schottky diode contact region between the semiconductor body and one of the source or the drain regions. With such an arrangement, the Schottky diode, when forward biased provides a fixed voltage, about 0.3 volts, between the semiconductor body and one of the source or the drain regions.

Abstract: A method of fabricating a compound semiconductor device includes a step of removing a semiconductor layer by an etching process to expose an upper major surface of an underlying semiconductor layer, followed by a growth of another semiconductor layer of the p-type on the surface thus exposed, wherein the exposed surface is cleaned by a flushing of a gaseous metal organic compound containing a group V element for removing impurities therefrom and further doping the exposed surface to the p-type.

Abstract: An electron emitting semiconductor device is provided with a P-type semiconductor layer arranged on a semiconductor substrate having an impurity concentration. A Schottky barrier electrode is arranged on a surface of the P-type semiconductor layer. Plural P.sup.+ -type area units are positioned under and facing the Schottky barrier electrode. An N.sup.+ -type area is disposed in the vicinity of the P.sup.+ -type units. The impurity concentration is such as to cause an avalanche breakdown in at least a portion of the surfaces.

Abstract: A method of making an inductor and the inductor. The inductor comprises a plurality of serially connected transistors at least partially formed in a substrate, preferably a silicon on insulator substrate, and comprises a gate common to the plurality of transistors. The plurality of transistors, transistor contacts, and electrical interconnects form the coil of the inductor and the gate common to the plurality of transistors forms the core of the inductor. Two inductors of the invention are magnetically coupled to form a transformer of the invention. A control transistor is serially connected to the primary inductor of the transformer. The control transistor is gated by a periodic output signal of a ring oscillator. An actuation and a deactuation of the control transistor allows the current in the primary coil to vary creating a changing magnetic flux in the primary and secondary cores and inducing a fluctuating current in the secondary coil.

Abstract: A stable FET including a substrate structure with a doped layer formed as a portion of the substrate structure and defining an electrically conductive shielding region adjacent a surface of the substrate structure. A channel region is positioned on the shielding region and includes a plurality of epitaxial layers grown on the surface of the substrate structure in overlying relationship to the doped layer. A drain and a source are positioned on the channel region in spaced relationship from each other with a gate positioned in overlying relationship on the channel region between the drain and source. An externally accessible electrical contact is connected to the shielding region and to the source region to provide a path for the removal of internally generated charges, such as holes.

Abstract: A horizontal MOSFET prevents itself from breakdown caused by an avalanche current which flows to a base of a parasitic bipolar transistor when avalanche breakdown of a diode formed between a drain and a substrate occurs. A current path, comprised of a back electrode or a layer with high impurity concentration, is disposed on the side of a back surface of a semiconductor substrate. This current path reduces the base current of the parasitic transistor. Due to this, heat generation caused by an operation of the parasitic transistor is suppressed, and the avalanche withstand capability of the MOSFET is improved corresponding to reduction of the internal resistance component of the MOSFET.