With Schottky Gate Patents (Class 257/280)
  • Patent number: 11127863
    Abstract: This invention concerns a gate structure and a process for its manufacturing. In particular, the present invention concerns the gate structuring of a field effect transistor with reduced thermo-mechanical stress and increased reliability (lower electromigration or diffusion of the gate metal). The gate structure according to the invention comprises a substrate; an active layer disposed on the substrate; an intermediate layer disposed on the active layer, the intermediate layer-having a recess extending through the entire intermediate layer towards the active layer; and a contact element which is arranged within the recess, the contact element completely filling the recess and extending to above the intermediate layer, the contact element resting at least in sections directly on the intermediate layer; the contact element being made of a Schottky metal and the contact element having an interior cavity completely enclosed by the Schottky metal.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: September 21, 2021
    Assignee: FORSCHUNGSVERBUND BERLIN E.V.
    Inventors: Konstantin Osipov, Richard Lossy, Hans-Joachim Würfl
  • Patent number: 11043583
    Abstract: A semiconductor structure includes a substrate, a gate electrode, a first dielectric layer, a gate metal layer, a source structure, and a drain structure. The first dielectric layer has a first opening exposing the gate electrode and a second opening, and the depth of the second opening is greater than the depth of the first opening. The gate metal layer conformally covers the top surface of the first dielectric layer, the first opening, and the second opening to serve as a gate field plate. A first portion of the gate metal layer at the bottom of the first opening is higher than a second portion of the gate metal layer at the bottom of the second opening. The source structure and the drain structure are disposed at opposite sides of the gate structure, wherein the second opening is disposed between the gate electrode and the drain structure.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 22, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yu-Chieh Chou, Hsin-Chih Lin, Chang-Xiang Hung
  • Patent number: 10894267
    Abstract: A method for producing a vapor deposition mask capable of satisfying both enhancement in definition and reduction in weight even when a size increased, a method for producing a vapor deposition mask device capable of aligning the vapor deposition mask to a frame with high precision, and a method for producing an organic semiconductor element capable of producing an organic semiconductor element with high definition are provided. A metal mask provided with a slit, and a resin mask that is positioned on a front surface of the metal mask and has openings corresponding to a pattern to be produced by vapor deposition arranged by lengthwise and crosswise in a plurality of rows, are stacked.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: January 19, 2021
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Yoshinori Hirobe, Yutaka Matsumoto, Masato Ushikusa, Toshihiko Takeda, Hiroyuki Nishimura, Katsunari Obata, Takashi Takekoshi
  • Patent number: 10868168
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the first conductivity type, a gate insulating film, and a gate electrode. A threshold voltage of the semiconductor device is higher than forward voltage of a built-in PN diode constituted by the second semiconductor layer, the semiconductor substrate, and the first semiconductor layer. Thus, when high electric potential is applied to a source electrode and the built-in PN diode is driven, the generation of crystal effects may be suppressed.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 15, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Hashizume, Keishirou Kumada, Yasuyuki Hoshi
  • Patent number: 10847456
    Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non-volatile and volatile memories. The memory circuitry employs an antifuse scheme that includes an array of 1T bitcells, wherein each bitcell effectively contains one gate or transistor-like device that provides both an antifuse element and a selector device for that bitcell. In particular, the bitcell device has asymmetric trench-based source/drain contacts such that one contact forms a capacitor in conjunction with the spacer and gate metal, and the other contact forms a diode in conjunction with a doped diffusion area and the gate metal. The capacitor serves as the antifuse element of the bitcell, and can be programmed by breaking down the spacer. The diode effectively provides a Schottky junction that serves as a selector device which can eliminate program and read disturbs from bitcells sharing the same bitline/wordline.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Ting Chang, Chia-Hong Jan, Walid M. Hafez
  • Patent number: 10804366
    Abstract: A method is presented for forming a semiconductor device. The method may include forming a first gate structure on a first portion of a semiconductor material located on a surface of an insulating substrate, the first gate structure including a first sacrificial layer and a second sacrificial layer and forming a second gate structure on a second portion of the semiconductor material located on the surface of the insulating substrate, the second gate structure including a third sacrificial layer. The method further includes etching the first and second dielectric sacrificial layers to create a first contact region within the first gate structure and etching the third dielectric sacrificial layer to create a second contact region within the second gate structure. The method further includes forming silicide in at least the first and second contact regions of the first and second gate structures, respectively.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: October 13, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10790397
    Abstract: A gate electrode (6) is provided on the semiconductor layer (2) and a least includes a lowermost layer (6a) in contact with the semiconductor layer (2), and an upper layer (6b) provided on the lowermost layer (6a). The upper layer (6b) applies stress to the lowermost layer (6a) to cause both edges of the lowermost layer (6a) to curl up from the semiconductor layer (2).
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: September 29, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tasuku Sumino, Takayuki Hisaka
  • Patent number: 10777671
    Abstract: Embodiments of the invention include a semiconductor device and methods of forming such devices. In an embodiment, the semiconductor device includes a source region, a drain region, and a channel region formed between the source region and drain region. In an embodiment, a first interlayer dielectric (ILD) may be formed over the channel region, and a first opening is formed through the first ILD. In an embodiment, a second ILD may be formed over the first ILD, and a second opening is formed through the second ILD. Embodiments of the invention include the second opening being offset from the first opening. Embodiments may also include a gate electrode formed through the first opening and the second opening. In an embodiment, the offset between the first opening and the second opening results in the formation of a field plate and a spacer that reduces a gate length of the semiconductor device.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic
  • Patent number: 10741655
    Abstract: The present technology relates to a semiconductor device, a manufacturing method of a semiconductor device, a solid-state imaging device, and an electronic device capable of reducing a parasitic capacitance between a gate electrode and source/drain electrodes and reducing a leakage current. The semiconductor device includes a first impurity region formed between element isolation regions on both sides, a gate electrode formed on an upper surface of a semiconductor substrate where the element isolation regions and the first impurity region are formed so that both ends are respectively overlapped with the element isolation regions on both sides and the gate electrode is separated from the first impurity region by a predetermined distance along a planar direction, and a second impurity region formed on the semiconductor substrate between the gate electrode and the first impurity region in plan view as having the same conductivity type as the first impurity region.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: August 11, 2020
    Assignee: Sony Corporation
    Inventor: Akiko Honjo
  • Patent number: 10741644
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an active layer disposed on the substrate; a via through the active layer; and a plurality of electrodes disposed on the active layer and into the via. Additionally, a package structure that includes the semiconductor device is also provided. The electrode is electrically connected to the substrate through the via.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: August 11, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Shiau-Shi Lin, Tzu-Hsuan Cheng, Hsin-Chang Tsai
  • Patent number: 10741700
    Abstract: Gate fingers (2-1 to 2-6) are arranged in one direction and each of the gate fingers is disposed so as to be adjacent to a corresponding one of drain electrodes (3-1 to 3-3) and a corresponding one of source electrodes (4-1 to 4-4) alternately, and have non-uniform gate head lengths.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: August 11, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yutaro Yamaguchi, Masatake Hangai, Koji Yamanaka
  • Patent number: 10686053
    Abstract: A high electron mobility transistor (HEMT) includes a semiconductor layer on a substrate; an insulating film on the semiconductor layer; a gate electrode in contact with a surface of the semiconductor layer through an opening in the insulating film; and a conductive film provided between the insulating film and a portion of the gate electrode at peripheries of the opening. The insulating film and the conductive film are made of respective materials containing silicon (Si). The gate electrode includes a Schottky metal in contact with the semiconductor layer and a cover metal provided on the Schottky metal. The Schottky metal covers the conductive film thereunder.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 16, 2020
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Tadashi Watanabe, Hajime Matsuda
  • Patent number: 10686487
    Abstract: A universal transmit-receive (UTR) module for phased array systems comprises an antenna element shared for both transmitting and receiving; a transmit path that includes a transmit-path phase shifter, a driver, a switch-mode power amplifier (SMPA) that is configured to be driven by the driver, and a dynamic power supply (DPS) that generates and supplies a DPS voltage to the power supply port of the SMPA; and a receive path that includes a TX/RX switch that determines whether the receive path is electrically connected to or electrically isolated from the antenna element, a bandpass filter (BPF) that aligns with the intended receive frequency and serves to suppress reflected transmit signals and reverse signals, an adjustable-gain low-noise amplifier (LNA), and a receive-path phase shifter. The UTR module is specially designed for operation in phased array systems.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: June 16, 2020
    Assignee: Eridan Communications, Inc.
    Inventors: Douglas A. Kirkpatrick, Earl W. McCune, Jr.
  • Patent number: 10607989
    Abstract: Provided herein are integrated circuits for use in performing analyte measurements and methods of fabricating the same. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in chemical and/or biological processes, including DNA hybridization and/or sequencing reactions. The methods for fabricating the integrated circuits include steps of depositing an insulating layer on a semiconducting substrate, and forming trenches in the insulating dielectric layer. Conductive material may be deposited in the trenches to form electrodes, and the insulating layer may be conditioned so that the electrodes protrude above the insulating layer. A 2D material, such as graphene, may be deposited on to electrodes to form a channel between the electrodes.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: March 31, 2020
    Assignee: NANOMEDICAL DIAGNOSTICS, INC.
    Inventor: Paul Hoffman
  • Patent number: 10580894
    Abstract: At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 10396194
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the second conductivity type, a third semiconductor region of the first conductivity type, a trench, a first electrode, and a Schottky electrode. Between trenches where the Schottky electrode is provided, a sidewall of each of the trenches is in contact with first semiconductor layer; and between trenches where the first electrode is provided, a sidewall of each of the trenches is in contact with the second semiconductor region and the third semiconductor region. A region of a part of the Schottky electrode faces toward the first semiconductor region in a depth direction and the trench faces the first semiconductor region in the depth direction.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: August 27, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yusuke Kobayashi
  • Patent number: 10391511
    Abstract: A method for producing a vapor deposition mask capable of satisfying both enhancement in definition and reduction in weight even when a size increased, a method for producing a vapor deposition mask device capable of aligning the vapor deposition mask to a frame with high precision, and a method for producing an organic semiconductor element capable of producing an organic semiconductor element with high definition are provided. A metal mask provided with a slit, and a resin mask that is positioned on a front surface of the metal mask and has openings corresponding to a pattern to be produced by vapor deposition arranged by lengthwise and crosswise in a plurality of rows, are stacked.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: August 27, 2019
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Yoshinori Hirobe, Yutaka Matsumoto, Masato Ushikusa, Toshihiko Takeda, Hiroyuki Nishimura, Katsunari Obata, Takashi Takekoshi
  • Patent number: 10109713
    Abstract: A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 23, 2018
    Assignees: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, CREE INC.
    Inventors: Alessandro Chini, Umesh Kumar Mishra, Primit Parikh, Yifeng Wu
  • Patent number: 10084095
    Abstract: The embodiments of present disclosure provide a thin film transistor, a method for manufacturing the same, and an array substrate. The thin film transistor comprises an active layer provided on a substrate, the active layer including a middle channel region, a first high resistance region and a second high resistance region provided respectively on external sides of the middle channel region, a source region provided on an external side of the first high resistance region and a drain region provided on an external side of the second high resistance region, wherein a base material of the active layer is diamond single crystal.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: September 25, 2018
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Xiaolong Li, Zheng Liu, Xiaoyong Lu, Chunping Long, Huijuan Zhang
  • Patent number: 10084109
    Abstract: A semiconductor structure for improving the gate metal adhesion and the Schottky stability, comprising: a III-nitride semiconductor having a top surface on which a conductive area and a non-conductive area are defined; a source contact metal and a first drain contact metal forming ohmic contact with the III-nitride semiconductor on the conductive area, and the first drain contact metal provided at one side of the source contact metal; and a gate metal layer comprising a gate connection line and a first gate finger extending from the gate connection line, the first gate finger interposing between the source contact metal and the first drain contact metal and forming a Schottky contact with the III-nitride semiconductor on the conductive area, wherein the first gate finger has a first terminal anchor at an end thereof surrounding the source contact metal, and the first terminal anchor has an increased width.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: September 25, 2018
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Jhih-Han Du, Yi Wei Lien, Che-Kai Lin, Wei-Chou Wang
  • Patent number: 10056487
    Abstract: At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 10037886
    Abstract: A method of manufacturing a silicon carbide semiconductor device having a contact formed between a p-type silicon carbide semiconductor body and a metal electrode, includes forming on a surface of the p-type silicon carbide semiconductor body, a graphene layer so as to reduce a potential difference generated in a conjunction interface between the p-type silicon carbide semiconductor body and the metal electrode; forming an insulator layer comprising a hexagonal boron nitride on a surface of the graphene layer; and forming the metal electrode on a surface of the insulation layer.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 31, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Fujii, Mariko Sato, Takuro Inamoto
  • Patent number: 9984886
    Abstract: A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate adjacent the gate structure in a first direction crossing the second direction, a first conductive contact plug on the gate structure, and a second contact plug structure disposed on the source/drain layer. The second contact plug structure includes a second conductive contact plug and an insulation pattern, and the second conductive contact plug and the insulation pattern are disposed in the second direction and contact each other. The first conductive contact plug and the insulation pattern are adjacent to each other in the first direction. The first and second conductive contact plugs are spaced apart from each other.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: May 29, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoon-Hae Kim, Hwa-Sung Rhee, Keun-Hwi Cho
  • Patent number: 9978858
    Abstract: Gallium nitride material devices and methods associated with the same. In some embodiments, the devices may be transistors which include a conductive structure connected to a source electrode. The conductive structure may form a source field plate which can be formed over a dielectric material and can extend in the direction of the gate electrode of the transistor. The source field plate may reduce the electrical field (e.g., peak electrical field and/or integrated electrical field) in the region of the device between the gate electrode and the drain electrode which can lead to a number of advantages including reduced gate-drain feedback capacitance, reduced surface electron concentration, increased breakdown voltage, and improved device reliability. These advantages enable the gallium nitride material transistors to operate at high drain efficiencies and/or high output powers. The devices can be used in RF power applications, amongst others.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: May 22, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Jerry Wayne Johnson, Sameer Singhal, Allen W. Hanson, Robert Joseph Therrien
  • Patent number: 9966264
    Abstract: A substrate for semiconductor device includes a substrate, a reaction layer provided on a back surface of the substrate, a transmission preventing metal having a transmittance with respect to red light or infrared light lower than that of the substrate and a material of the substrate being mixed in the reaction layer, and a metal thin film layer formed on a back surface of the reaction layer and formed of the same material as the transmission preventing metal.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: May 8, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kohei Nishiguchi
  • Patent number: 9941401
    Abstract: A semiconductor device includes a semiconductor stacked structure in which a semiconductor layer including an electron supply layer and an electron transit layer is stacked, and a gate electrode contacting with the semiconductor layer included in the semiconductor stacked structure or an insulating layer. The portion of the gate electrode contacting with the semiconductor layer or the insulating layer is an oxide of a metal configuring the portion of the gate electrode contacting with the semiconductor layer or the insulating layer.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: April 10, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Kozo Makiyama, Naoya Okamoto
  • Patent number: 9917027
    Abstract: A method for fabricating an integrated circuit includes forming a first opening in an upper dielectric layer, the first opening having a first width, forming a second opening in a lower dielectric layer, the lower dielectric layer being below the upper dielectric layer, the second opening having a second width that is narrower than the first width, the second opening being substantially centered underneath the first opening so as to form a stepped via structure, conformally depositing an aluminum material layer in the stepped via structure and over the upper dielectric layer, and forming a passivation layer over the aluminum material layer.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: March 13, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Mahesh Bhatkar, Chin Chuan Neo, Juan Boon Tan
  • Patent number: 9899500
    Abstract: A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: February 20, 2018
    Assignee: NXP USA, INC.
    Inventors: Weize Chen, Xin Lin, Patrice M. Parris
  • Patent number: 9887718
    Abstract: A radio-frequency module includes a multilayer substrate, an input switch, an output switch, and filters. A switch IC is disposed on a main surface of the multilayer substrate. The input switch is disposed in the switch IC and includes a first input terminal and first output terminals. The output switch is disposed in the switch IC and includes second input terminals and a second output terminal. The filters are disposed outside the switch IC and are connected to the first output terminals and the second input terminals. In a plan view of the multilayer substrate, the first input terminal and the first output terminals are disposed close to a first side of an exterior of the switch IC, and the second input terminals and the second output terminal are disposed close to a second side different from the first side of the exterior of the switch IC.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: February 6, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takashi Watanabe
  • Patent number: 9882041
    Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: January 30, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jungwoo Joh, Naveen Tipirneni, Chang Soo Suh, Sameer Pendharkar
  • Patent number: 9847781
    Abstract: A radio frequency switch may include a common port transmitting and receiving a radio frequency signal, a first switching unit including a plurality of first switch elements connected in series and opening or closing a signal transfer path between a first port inputting and outputting the radio frequency signal and the common port, and a second switching unit having a plurality of second switch elements connected in series and opening or closing a signal transfer path between a second port inputting and outputting the radio frequency signal and the common port. The second switching unit further includes a first filter circuit unit connected to a control terminal of at least one second switch element among the plurality of second switch elements to remove at least one preset frequency band signal.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: December 19, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yoo Sam Na, Jong Myeong Kim, Hyun Jin Yoo, Hyun Hwan Yoo, Yoo Hwan Kim
  • Patent number: 9722059
    Abstract: There are disclosed herein various implementations of a latch-up free power transistor. Such a device includes an insulated gate situated adjacent to a conduction channel in the power transistor, an emitter electrode in direct physical contact with the conduction channel, and a collector electrode in electrical contact with the conduction channel. The power transistor also includes an emitter layer in contact with a surface of a semiconductor substrate adjacent the conduction channel.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: August 1, 2017
    Assignee: Infineon Technologies AG
    Inventor: Alim Karmous
  • Patent number: 9722037
    Abstract: An embodiment of a compound semiconductor device includes: a substrate; a nitride compound semiconductor stacked structure formed on or above the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. A recess positioning between the gate electrode and the drain electrode in a plan view is formed at a surface of the compound semiconductor stacked structure.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: August 1, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Kozo Makiyama
  • Patent number: 9647076
    Abstract: A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: May 9, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Michael Shur, Remigijus Gaska
  • Patent number: 9634004
    Abstract: Semiconductor devices include a passivating layer over a pair of fins. A barrier extends through the passivating layer and between the pair of fins and that electrically isolates the fins. Electrical contacts are formed through the passivating layer to the fins. The electrical contacts directly contact sidewalls of the barrier.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: April 25, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie, Tenko Yamashita
  • Patent number: 9576806
    Abstract: A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith E. Fogel, Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek
  • Patent number: 9564358
    Abstract: A method of forming a semiconductor device includes forming a trench in a passivating layer between neighboring fins. A barrier is formed in the trench. Conductive contacts are formed in the passivating layer to provide electrical connectivity to the fins. The conductive contacts are in direct contact with sidewalls of the barrier. A semiconductor device includes a passivating layer over a pair of fins. A barrier extends through the passivating layer and between the pair of fins and that electrically isolates the fins. Electrical contacts are formed through the passivating layer to the fins. The electrical contacts directly contact sidewalls of the barrier.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: February 7, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC
    Inventors: Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie, Tenko Yamashita
  • Patent number: 9543290
    Abstract: A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: January 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 9536971
    Abstract: A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer. A conductive transistor gate layer is then formed within the trench and over the vertical spacing layer. The transistor gate layer is etched, which exposes the vertical spacing layer. A spacer layer is formed over the etched conductive gate layer and over the vertical spacing layer, then the spacer layer and the vertical spacing layer are anisotropically etched. Subsequent to anisotropically etching the vertical spacing layer, a portion of the vertical spacing layer is interposed between the semiconductor wafer and the etched conductive transistor gate layer in a direction perpendicular to the plane of a major surface of the semiconductor wafer.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: January 3, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 9530876
    Abstract: At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: December 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 9530727
    Abstract: A method comprises: forming a plurality of reference voltage patterns in a first layer of a semiconductor substrate using a first mask, the reference voltage patterns including alternating first reference voltage patterns and second reference voltage patterns; and forming a plurality of signal patterns in the first layer of the semiconductor substrate using a second mask, ones of the plurality of signal patterns located between successive pairs of reference voltage patterns.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: You-Cheng Xiao, Wei Min Chan, Ken-Hsien Hsieh
  • Patent number: 9525063
    Abstract: In an embodiment, a switching circuit includes input drain, source and gate nodes, a high voltage depletion mode transistor including a current path coupled in series with a current path of a low voltage enhancement mode transistor, and an overheating detection circuit for detecting overheating of the switching circuit.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: December 20, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess, Rainald Sander
  • Patent number: 9472626
    Abstract: A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: October 18, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Robert Beach, Zhi He, Jianjun Cao
  • Patent number: 9466724
    Abstract: According to an exemplary embodiment of the present embodiment, a semiconductor device is provided as follows. An active fin protrudes from a substrate, extending in a direction. A gate structure crosses a first region of the active fin. A source/drain is disposed on a second region of the active fin. The source/drain includes upper surfaces and vertical side surfaces. The vertical side surfaces are in substantially parallel with side surfaces of the active fin.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: October 11, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changjae Yang, Shigenobu Maeda, Changhwa Kim, Youngmoon Choi
  • Patent number: 9449979
    Abstract: A new form of a solid-state non-volatile memory cell is presented. The solid-state memory cell comprises a series of different layers of ferroelectric materials, semiconductors, ferroelectric semiconductors, metals, and ceramics, and oxides. The memory device stores information in the direction and magnitude of polarization of the ferroelectric layers. Additionally, a method is presented for storing multiple bits of information in a single memory cell by allowing partial polarization of a single ferroelectric layer and stacking of multiple ferroelectric functional units on top of each other. Additionally, a technique for reading and writing said memory cell is presented. Additionally, the memory cell design allows for the formation of Schottky barriers which act to improve functionality and increase resistance. Additionally, a method is presented for depositing textured lithium niobate thin films.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: September 20, 2016
    Inventors: Thomas J McKinnon, Erol Girt
  • Patent number: 9437689
    Abstract: A Ga2O3 semiconductor element includes: an n-type ?-Ga2O3 single crystal film, which is formed on a high-resistance ?-Ga2O3 substrate directly or with other layer therebetween; a source electrode and a drain electrode, which are formed on the n-type ?-Ga2O3 single crystal film; and a gate electrode, which is formed on the n-type ?-Ga2O3 single crystal film between the source electrode and the drain electrode.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: September 6, 2016
    Assignees: TAMURA CORPORATION, NATIONAI INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY
    Inventors: Kohei Sasaki, Masataka Higashiwaki
  • Patent number: 9418990
    Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: August 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Raheel Azmat, Sharma Deepak, Chulhong Park
  • Patent number: 9397170
    Abstract: A Ga2O3 semiconductor element includes: an n-type ?-Ga2O3 single crystal film, which is formed on a high-resistance ?-Ga2O3 substrate directly or with other layer therebetween; a source electrode and a drain electrode, which are formed on the n-type ?-Ga2O3 single crystal film; and a gate electrode, which is formed on the n-type ?-Ga2O3 single crystal film between the source electrode and the drain electrode.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: July 19, 2016
    Assignees: TAMURA CORPORATION, NATIONAI INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY
    Inventors: Kohei Sasaki, Masataka Higashiwaki
  • Patent number: 9391173
    Abstract: A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: July 12, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith E. Fogel, Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek
  • Patent number: 9373639
    Abstract: A method of forming a field effect transistor (FET) device includes forming a recess in a PFET region of a starting semiconductor substrate comprising a bulk semiconductor layer an epitaxial n+ layer formed on the bulk semiconductor layer, a buried insulator (BOX) layer formed on the epitaxial n+ layer, and an active semiconductor or silicon-on-insulator (SOI) layer formed on the BOX layer, the recess being formed completely through the SOI layer, the BOX layer, and partially into the epitaxial n+ layer; epitaxially growing a silicon germanium (SiGe) transition layer on the epitaxial n+ layer, the SiGe transition layer having a lower dopant concentration than the epitaxial n+ layer; and epitaxially growing embedded source/drain (S/D) regions on the SiGe transition layer and adjacent the SOI layer in the PFET region, the embedded S/D regions comprising p-type doped SiGe.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: June 21, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek