With Schottky Gate Patents (Class 257/280)
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Patent number: 11929408Abstract: Various embodiments are disclosed for improved and structurally optimized transistors, such as RF power amplifier transistors. A transistor may include a drain metal portion raised from a surface of a substrate, a drain metal having a notched region, a gate manifold body with angled gate tabs extending from the gate manifold, and/or a source-connected shielding. The transistor may include a high-electron-mobility transistor (HEMT), a gallium nitride (GaN)-on-silicon transistor, a GaN-on-silicon-carbide transistor, or other type of transistor.Type: GrantFiled: May 14, 2020Date of Patent: March 12, 2024Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.Inventors: Shamit Som, Wayne Mack Struble, Jason Matthew Barrett, Nishant R Yamujala, John Stephen Atherton
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Patent number: 11871644Abstract: A mask including: a deposition pattern portion including a plurality of deposition holes that are configured to have deposition material pass therethrough; and a dummy pattern portion outside the deposition pattern portion, wherein the dummy pattern portion includes an auxetic structure having a negative Poisson's ratio.Type: GrantFiled: April 27, 2022Date of Patent: January 9, 2024Assignee: Samsung Display Co., Ltd.Inventors: Daewon Baek, Minji Jang, Jongbum Kim
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Patent number: 11830776Abstract: An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.Type: GrantFiled: April 27, 2022Date of Patent: November 28, 2023Assignee: STMicroelectronics (Crolles 2) SASInventor: Jean Jimenez Martinez
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Patent number: 11810971Abstract: A semiconductor device comprises a III-N device and a Field Effect Transistor (FET). The III-N device comprises a substrate on a first side of a III-N material structure, a first gate, a first source, and a first drain on a side of the III-N material structure opposite the substrate. The FET comprises a second semiconductor material structure, a second gate, a second source, and a second drain, and the second source being on an opposite side of the second semiconductor material structure from the second drain. The second drain of the FET is directly contacting and electrically connected to the first source of the III-N devices, and a via-hole is formed through a portion of the III-N material structure exposing a portion of the top surface of the substrate and the first gate is electrically connected to the substrate through the via-hole.Type: GrantFiled: March 20, 2020Date of Patent: November 7, 2023Assignee: Transphorm Technology, Inc.Inventors: Yifeng Wu, John Kirk Gritters
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Patent number: 11735519Abstract: A package device comprises a first transceiver comprising a first integrated circuit (IC) die and transmitter circuitry, and a second transceiver comprising a second IC die and receiver circuitry. The receiver circuitry is coupled to the transmitter circuitry via a channel. The package device further comprises an interconnection device connected to the first IC die and the second IC die. The interconnection device comprises a channel connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element disposed external to the first IC die and the second IC die and along the channel.Type: GrantFiled: June 24, 2021Date of Patent: August 22, 2023Assignee: XILINX, INC.Inventors: Zhaoyin Daniel Wu, Parag Upadhyaya, Hong Shi
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Patent number: 11670586Abstract: A semiconductor device includes transistors and a resistor. The transistors are connected in series between a power terminal and a ground terminal, and gate terminals of the transistors being connected together. The resistor is overlaid above the transistors. The resistor is connected between a source terminal of the transistors and the ground terminal.Type: GrantFiled: January 3, 2022Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Zeng Kang, Wen-Shen Chou, Yung-Chow Peng
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Patent number: 11659774Abstract: Methods and devices are provided that include a magnetic tunneling junction (MTJ) element. A first spacer layer abuts sidewalls of the MTJ element. The first spacer layer has a low-dielectric constant (low-k) oxide composition. A second spacer layer is disposed on the first spacer layer and has a low-k nitride composition.Type: GrantFiled: November 25, 2020Date of Patent: May 23, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiang-Ku Shen, Dian-Hau Chen
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Patent number: 11658093Abstract: A semiconductor element includes a main body and an obverse face electrode. The main body includes an obverse face that faces in a thickness direction. The obverse face electrode is electrically connected to the main body. The obverse face electrode includes a first section and a plurality of second sections. The first section is provided on the obverse face. The plurality of second sections are in contact with the first section, and spaced apart from each other in a direction perpendicular to the thickness direction. A total area of the plurality of second sections is smaller than an area of the first section including portions overlapping with the plurality of second sections, in a view along the thickness direction.Type: GrantFiled: June 26, 2019Date of Patent: May 23, 2023Assignee: ROHM CO., LTD.Inventors: Hirofumi Tanaka, Yuto Nishiyama
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Patent number: 11532632Abstract: A semiconductor device includes a base substrate including an NMOS region and a PMOS region. The PMOS region includes a first P-type region and a second P-type region. The semiconductor device also includes an interlayer dielectric layer, a gate structure formed through the interlayer dielectric layer and including an N-type region gate structure formed in the NMOS region, a first gate structure formed in the first P-type region and connected to the N-type region gate structure, and a second gate structure formed in the second P-type region and connected to the first gate structure. The direction from the N-type region gate structure to the second gate structure is an extending direction of the N-type region opening, and along a direction perpendicular to the extending direction of the N-type region opening, the width of the first gate structure is larger than the width of the second gate structure.Type: GrantFiled: January 29, 2021Date of Patent: December 20, 2022Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Yong Li
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Patent number: 11511301Abstract: A method for producing a vapor deposition mask capable of satisfying both enhancement in definition and reduction in weight even when a size increased, a method for producing a vapor deposition mask device capable of aligning the vapor deposition mask to a frame with high precision, and a method for producing an organic semiconductor element capable of producing an organic semiconductor element with high definition are provided. A metal mask provided with a slit, and a resin mask that is positioned on a front surface of the metal mask and has openings corresponding to a pattern to be produced by vapor deposition arranged by lengthwise and crosswise in a plurality of rows, are stacked.Type: GrantFiled: November 18, 2020Date of Patent: November 29, 2022Assignee: Dai Nippon Printing Co., Ltd.Inventors: Yoshinori Hirobe, Yutaka Matsumoto, Masato Ushikusa, Toshihiko Takeda, Hiroyuki Nishimura, Katsunari Obata, Takashi Takekoshi
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Patent number: 11417759Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.Type: GrantFiled: June 6, 2019Date of Patent: August 16, 2022Assignee: General Electric CompanyInventors: Stephen Daley Arthur, Joseph Darryl Michael, Tammy Lynn Johnson, David Alan Lilienfeld, Kevin Sean Matocha, Jody Alan Fronheiser, William Gregg Hawkins
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Patent number: 11387339Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same, and it relates to a field of semiconductor technology. The semiconductor device includes a substrate, a semiconductor layer, a dielectric layer, a source, a drain, and a gate, wherein a first face of the gate close to a side of the drain and close to the semiconductor layer has a first curved face. A gate trench corresponding to the gate is provided on the dielectric layer, a material of the gate being filled in the gate trench, and at least a part of a second face of the gate trench in contact with the gate is a second curved face which extends from a surface of the dielectric layer away from the semiconductor layer toward the semiconductor layer.Type: GrantFiled: December 17, 2018Date of Patent: July 12, 2022Assignee: DYNAX SEMICONDUCTOR, INC.Inventors: Naiqian Zhang, Xi Song, Qingzhao Gu, Xingxing Wu
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Patent number: 11309412Abstract: A high electron mobility transistor (HEMT) device comprising a substrate, a plurality of semiconductor layers provided on the substrate, and a source terminal, a drain terminal and at least one gate terminal provided on the plurality of semiconductor layers. The HEMT also includes a metal ring formed on the plurality of semiconductor layers around the source terminal, the drain terminal and the at least one gate terminal, where the metal ring operates to shift the pinch-off voltage of the device. In one embodiment, the metal ring includes an ohmic portion and an electrode portion, where both the ohmic portion and the electrode portion include a lower titanium layer, a middle platinum layer and an upper gold layer.Type: GrantFiled: May 17, 2017Date of Patent: April 19, 2022Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: Xiaobing Mei, Wayne Yoshida
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Patent number: 11296239Abstract: A MESFET transistor on a horizontal substrate surface with at least one wiring layer on the substrate surface. The transistor comprises source, drain and gate electrodes which are at least partly covered by a semiconducting channel layer. The source, drain and gate electrodes optionally comprise interface contact materials for changing the junction type between each electrode and the channel. The interface between the source electrode and the channel is an ohmic junction, the interface between the drain electrode and the channel is an ohmic junction, and the interface between the gate electrode and the channel is a Schottky junction. The substrate is a CMOS substrate.Type: GrantFiled: March 14, 2019Date of Patent: April 5, 2022Assignee: EMBERION OYInventors: Sami Kallioinen, Helena Pohjonen
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Patent number: 11233147Abstract: A semiconductor device includes an inversion type semiconductor element including: a semiconductor substrate; a first conductive type layer formed on the semiconductor substrate; an electric field blocking layer formed on the first conductive type layer and including a linear shaped portion; a JFET portion formed on the first conductive type layer and having a linear shaped portion; a current dispersion layer formed on the electric field blocking layer and the JFET portion; a deep layer formed on the electric field blocking layer and the JFET portion; a base region formed on the current dispersion layer and the deep layer; a source region formed on the base region; trench gate structures including a gate trench, a gate insulation film, and a gate electrode, and arranged in a stripe shape; an interlayer insulation; a source electrode; and a drain electrode formed on a back surface side of the semiconductor substrate.Type: GrantFiled: January 17, 2020Date of Patent: January 25, 2022Assignee: DENSO CORPORATIONInventors: Masato Noborio, Jun Saito, Yukihiko Watanabe
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Patent number: 11127863Abstract: This invention concerns a gate structure and a process for its manufacturing. In particular, the present invention concerns the gate structuring of a field effect transistor with reduced thermo-mechanical stress and increased reliability (lower electromigration or diffusion of the gate metal). The gate structure according to the invention comprises a substrate; an active layer disposed on the substrate; an intermediate layer disposed on the active layer, the intermediate layer-having a recess extending through the entire intermediate layer towards the active layer; and a contact element which is arranged within the recess, the contact element completely filling the recess and extending to above the intermediate layer, the contact element resting at least in sections directly on the intermediate layer; the contact element being made of a Schottky metal and the contact element having an interior cavity completely enclosed by the Schottky metal.Type: GrantFiled: November 20, 2017Date of Patent: September 21, 2021Assignee: FORSCHUNGSVERBUND BERLIN E.V.Inventors: Konstantin Osipov, Richard Lossy, Hans-Joachim Würfl
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Patent number: 11043583Abstract: A semiconductor structure includes a substrate, a gate electrode, a first dielectric layer, a gate metal layer, a source structure, and a drain structure. The first dielectric layer has a first opening exposing the gate electrode and a second opening, and the depth of the second opening is greater than the depth of the first opening. The gate metal layer conformally covers the top surface of the first dielectric layer, the first opening, and the second opening to serve as a gate field plate. A first portion of the gate metal layer at the bottom of the first opening is higher than a second portion of the gate metal layer at the bottom of the second opening. The source structure and the drain structure are disposed at opposite sides of the gate structure, wherein the second opening is disposed between the gate electrode and the drain structure.Type: GrantFiled: May 20, 2019Date of Patent: June 22, 2021Assignee: Vanguard International Semiconductor CorporationInventors: Yu-Chieh Chou, Hsin-Chih Lin, Chang-Xiang Hung
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Patent number: 10894267Abstract: A method for producing a vapor deposition mask capable of satisfying both enhancement in definition and reduction in weight even when a size increased, a method for producing a vapor deposition mask device capable of aligning the vapor deposition mask to a frame with high precision, and a method for producing an organic semiconductor element capable of producing an organic semiconductor element with high definition are provided. A metal mask provided with a slit, and a resin mask that is positioned on a front surface of the metal mask and has openings corresponding to a pattern to be produced by vapor deposition arranged by lengthwise and crosswise in a plurality of rows, are stacked.Type: GrantFiled: July 9, 2019Date of Patent: January 19, 2021Assignee: Dai Nippon Printing Co., Ltd.Inventors: Yoshinori Hirobe, Yutaka Matsumoto, Masato Ushikusa, Toshihiko Takeda, Hiroyuki Nishimura, Katsunari Obata, Takashi Takekoshi
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Patent number: 10868168Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the first conductivity type, a gate insulating film, and a gate electrode. A threshold voltage of the semiconductor device is higher than forward voltage of a built-in PN diode constituted by the second semiconductor layer, the semiconductor substrate, and the first semiconductor layer. Thus, when high electric potential is applied to a source electrode and the built-in PN diode is driven, the generation of crystal effects may be suppressed.Type: GrantFiled: December 27, 2018Date of Patent: December 15, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yuichi Hashizume, Keishirou Kumada, Yasuyuki Hoshi
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Patent number: 10847456Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non-volatile and volatile memories. The memory circuitry employs an antifuse scheme that includes an array of 1T bitcells, wherein each bitcell effectively contains one gate or transistor-like device that provides both an antifuse element and a selector device for that bitcell. In particular, the bitcell device has asymmetric trench-based source/drain contacts such that one contact forms a capacitor in conjunction with the spacer and gate metal, and the other contact forms a diode in conjunction with a doped diffusion area and the gate metal. The capacitor serves as the antifuse element of the bitcell, and can be programmed by breaking down the spacer. The diode effectively provides a Schottky junction that serves as a selector device which can eliminate program and read disturbs from bitcells sharing the same bitline/wordline.Type: GrantFiled: March 26, 2018Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Ting Chang, Chia-Hong Jan, Walid M. Hafez
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Patent number: 10804366Abstract: A method is presented for forming a semiconductor device. The method may include forming a first gate structure on a first portion of a semiconductor material located on a surface of an insulating substrate, the first gate structure including a first sacrificial layer and a second sacrificial layer and forming a second gate structure on a second portion of the semiconductor material located on the surface of the insulating substrate, the second gate structure including a third sacrificial layer. The method further includes etching the first and second dielectric sacrificial layers to create a first contact region within the first gate structure and etching the third dielectric sacrificial layer to create a second contact region within the second gate structure. The method further includes forming silicide in at least the first and second contact regions of the first and second gate structures, respectively.Type: GrantFiled: June 18, 2019Date of Patent: October 13, 2020Assignee: ELPIS TECHNOLOGIES INC.Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
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Patent number: 10790397Abstract: A gate electrode (6) is provided on the semiconductor layer (2) and a least includes a lowermost layer (6a) in contact with the semiconductor layer (2), and an upper layer (6b) provided on the lowermost layer (6a). The upper layer (6b) applies stress to the lowermost layer (6a) to cause both edges of the lowermost layer (6a) to curl up from the semiconductor layer (2).Type: GrantFiled: February 27, 2017Date of Patent: September 29, 2020Assignee: Mitsubishi Electric CorporationInventors: Tasuku Sumino, Takayuki Hisaka
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Patent number: 10777671Abstract: Embodiments of the invention include a semiconductor device and methods of forming such devices. In an embodiment, the semiconductor device includes a source region, a drain region, and a channel region formed between the source region and drain region. In an embodiment, a first interlayer dielectric (ILD) may be formed over the channel region, and a first opening is formed through the first ILD. In an embodiment, a second ILD may be formed over the first ILD, and a second opening is formed through the second ILD. Embodiments of the invention include the second opening being offset from the first opening. Embodiments may also include a gate electrode formed through the first opening and the second opening. In an embodiment, the offset between the first opening and the second opening results in the formation of a field plate and a spacer that reduces a gate length of the semiconductor device.Type: GrantFiled: September 30, 2016Date of Patent: September 15, 2020Assignee: Intel CorporationInventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic
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Patent number: 10741644Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an active layer disposed on the substrate; a via through the active layer; and a plurality of electrodes disposed on the active layer and into the via. Additionally, a package structure that includes the semiconductor device is also provided. The electrode is electrically connected to the substrate through the via.Type: GrantFiled: November 22, 2016Date of Patent: August 11, 2020Assignee: DELTA ELECTRONICS, INC.Inventors: Shiau-Shi Lin, Tzu-Hsuan Cheng, Hsin-Chang Tsai
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Patent number: 10741655Abstract: The present technology relates to a semiconductor device, a manufacturing method of a semiconductor device, a solid-state imaging device, and an electronic device capable of reducing a parasitic capacitance between a gate electrode and source/drain electrodes and reducing a leakage current. The semiconductor device includes a first impurity region formed between element isolation regions on both sides, a gate electrode formed on an upper surface of a semiconductor substrate where the element isolation regions and the first impurity region are formed so that both ends are respectively overlapped with the element isolation regions on both sides and the gate electrode is separated from the first impurity region by a predetermined distance along a planar direction, and a second impurity region formed on the semiconductor substrate between the gate electrode and the first impurity region in plan view as having the same conductivity type as the first impurity region.Type: GrantFiled: January 6, 2017Date of Patent: August 11, 2020Assignee: Sony CorporationInventor: Akiko Honjo
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Patent number: 10741700Abstract: Gate fingers (2-1 to 2-6) are arranged in one direction and each of the gate fingers is disposed so as to be adjacent to a corresponding one of drain electrodes (3-1 to 3-3) and a corresponding one of source electrodes (4-1 to 4-4) alternately, and have non-uniform gate head lengths.Type: GrantFiled: May 18, 2017Date of Patent: August 11, 2020Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yutaro Yamaguchi, Masatake Hangai, Koji Yamanaka
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Patent number: 10686053Abstract: A high electron mobility transistor (HEMT) includes a semiconductor layer on a substrate; an insulating film on the semiconductor layer; a gate electrode in contact with a surface of the semiconductor layer through an opening in the insulating film; and a conductive film provided between the insulating film and a portion of the gate electrode at peripheries of the opening. The insulating film and the conductive film are made of respective materials containing silicon (Si). The gate electrode includes a Schottky metal in contact with the semiconductor layer and a cover metal provided on the Schottky metal. The Schottky metal covers the conductive film thereunder.Type: GrantFiled: September 11, 2018Date of Patent: June 16, 2020Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Tadashi Watanabe, Hajime Matsuda
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Patent number: 10686487Abstract: A universal transmit-receive (UTR) module for phased array systems comprises an antenna element shared for both transmitting and receiving; a transmit path that includes a transmit-path phase shifter, a driver, a switch-mode power amplifier (SMPA) that is configured to be driven by the driver, and a dynamic power supply (DPS) that generates and supplies a DPS voltage to the power supply port of the SMPA; and a receive path that includes a TX/RX switch that determines whether the receive path is electrically connected to or electrically isolated from the antenna element, a bandpass filter (BPF) that aligns with the intended receive frequency and serves to suppress reflected transmit signals and reverse signals, an adjustable-gain low-noise amplifier (LNA), and a receive-path phase shifter. The UTR module is specially designed for operation in phased array systems.Type: GrantFiled: June 23, 2015Date of Patent: June 16, 2020Assignee: Eridan Communications, Inc.Inventors: Douglas A. Kirkpatrick, Earl W. McCune, Jr.
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Patent number: 10607989Abstract: Provided herein are integrated circuits for use in performing analyte measurements and methods of fabricating the same. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in chemical and/or biological processes, including DNA hybridization and/or sequencing reactions. The methods for fabricating the integrated circuits include steps of depositing an insulating layer on a semiconducting substrate, and forming trenches in the insulating dielectric layer. Conductive material may be deposited in the trenches to form electrodes, and the insulating layer may be conditioned so that the electrodes protrude above the insulating layer. A 2D material, such as graphene, may be deposited on to electrodes to form a channel between the electrodes.Type: GrantFiled: July 2, 2018Date of Patent: March 31, 2020Assignee: NANOMEDICAL DIAGNOSTICS, INC.Inventor: Paul Hoffman
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Patent number: 10580894Abstract: At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.Type: GrantFiled: May 2, 2018Date of Patent: March 3, 2020Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
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Patent number: 10391511Abstract: A method for producing a vapor deposition mask capable of satisfying both enhancement in definition and reduction in weight even when a size increased, a method for producing a vapor deposition mask device capable of aligning the vapor deposition mask to a frame with high precision, and a method for producing an organic semiconductor element capable of producing an organic semiconductor element with high definition are provided. A metal mask provided with a slit, and a resin mask that is positioned on a front surface of the metal mask and has openings corresponding to a pattern to be produced by vapor deposition arranged by lengthwise and crosswise in a plurality of rows, are stacked.Type: GrantFiled: November 8, 2018Date of Patent: August 27, 2019Assignee: Dai Nippon Printing Co., Ltd.Inventors: Yoshinori Hirobe, Yutaka Matsumoto, Masato Ushikusa, Toshihiko Takeda, Hiroyuki Nishimura, Katsunari Obata, Takashi Takekoshi
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Patent number: 10396194Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the second conductivity type, a third semiconductor region of the first conductivity type, a trench, a first electrode, and a Schottky electrode. Between trenches where the Schottky electrode is provided, a sidewall of each of the trenches is in contact with first semiconductor layer; and between trenches where the first electrode is provided, a sidewall of each of the trenches is in contact with the second semiconductor region and the third semiconductor region. A region of a part of the Schottky electrode faces toward the first semiconductor region in a depth direction and the trench faces the first semiconductor region in the depth direction.Type: GrantFiled: December 18, 2017Date of Patent: August 27, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventor: Yusuke Kobayashi
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Patent number: 10109713Abstract: A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.Type: GrantFiled: September 30, 2016Date of Patent: October 23, 2018Assignees: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, CREE INC.Inventors: Alessandro Chini, Umesh Kumar Mishra, Primit Parikh, Yifeng Wu
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Patent number: 10084109Abstract: A semiconductor structure for improving the gate metal adhesion and the Schottky stability, comprising: a III-nitride semiconductor having a top surface on which a conductive area and a non-conductive area are defined; a source contact metal and a first drain contact metal forming ohmic contact with the III-nitride semiconductor on the conductive area, and the first drain contact metal provided at one side of the source contact metal; and a gate metal layer comprising a gate connection line and a first gate finger extending from the gate connection line, the first gate finger interposing between the source contact metal and the first drain contact metal and forming a Schottky contact with the III-nitride semiconductor on the conductive area, wherein the first gate finger has a first terminal anchor at an end thereof surrounding the source contact metal, and the first terminal anchor has an increased width.Type: GrantFiled: December 11, 2017Date of Patent: September 25, 2018Assignee: WIN SEMICONDUCTORS CORP.Inventors: Jhih-Han Du, Yi Wei Lien, Che-Kai Lin, Wei-Chou Wang
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Patent number: 10084095Abstract: The embodiments of present disclosure provide a thin film transistor, a method for manufacturing the same, and an array substrate. The thin film transistor comprises an active layer provided on a substrate, the active layer including a middle channel region, a first high resistance region and a second high resistance region provided respectively on external sides of the middle channel region, a source region provided on an external side of the first high resistance region and a drain region provided on an external side of the second high resistance region, wherein a base material of the active layer is diamond single crystal.Type: GrantFiled: March 1, 2016Date of Patent: September 25, 2018Assignee: BOE Technology Group Co., Ltd.Inventors: Xiaolong Li, Zheng Liu, Xiaoyong Lu, Chunping Long, Huijuan Zhang
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Patent number: 10056487Abstract: At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.Type: GrantFiled: November 30, 2016Date of Patent: August 21, 2018Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
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Patent number: 10037886Abstract: A method of manufacturing a silicon carbide semiconductor device having a contact formed between a p-type silicon carbide semiconductor body and a metal electrode, includes forming on a surface of the p-type silicon carbide semiconductor body, a graphene layer so as to reduce a potential difference generated in a conjunction interface between the p-type silicon carbide semiconductor body and the metal electrode; forming an insulator layer comprising a hexagonal boron nitride on a surface of the graphene layer; and forming the metal electrode on a surface of the insulation layer.Type: GrantFiled: June 30, 2016Date of Patent: July 31, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takeshi Fujii, Mariko Sato, Takuro Inamoto
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Patent number: 9984886Abstract: A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate adjacent the gate structure in a first direction crossing the second direction, a first conductive contact plug on the gate structure, and a second contact plug structure disposed on the source/drain layer. The second contact plug structure includes a second conductive contact plug and an insulation pattern, and the second conductive contact plug and the insulation pattern are disposed in the second direction and contact each other. The first conductive contact plug and the insulation pattern are adjacent to each other in the first direction. The first and second conductive contact plugs are spaced apart from each other.Type: GrantFiled: January 20, 2016Date of Patent: May 29, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoon-Hae Kim, Hwa-Sung Rhee, Keun-Hwi Cho
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Patent number: 9978858Abstract: Gallium nitride material devices and methods associated with the same. In some embodiments, the devices may be transistors which include a conductive structure connected to a source electrode. The conductive structure may form a source field plate which can be formed over a dielectric material and can extend in the direction of the gate electrode of the transistor. The source field plate may reduce the electrical field (e.g., peak electrical field and/or integrated electrical field) in the region of the device between the gate electrode and the drain electrode which can lead to a number of advantages including reduced gate-drain feedback capacitance, reduced surface electron concentration, increased breakdown voltage, and improved device reliability. These advantages enable the gallium nitride material transistors to operate at high drain efficiencies and/or high output powers. The devices can be used in RF power applications, amongst others.Type: GrantFiled: February 15, 2017Date of Patent: May 22, 2018Assignee: Infineon Technologies Americas Corp.Inventors: Jerry Wayne Johnson, Sameer Singhal, Allen W. Hanson, Robert Joseph Therrien
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Patent number: 9966264Abstract: A substrate for semiconductor device includes a substrate, a reaction layer provided on a back surface of the substrate, a transmission preventing metal having a transmittance with respect to red light or infrared light lower than that of the substrate and a material of the substrate being mixed in the reaction layer, and a metal thin film layer formed on a back surface of the reaction layer and formed of the same material as the transmission preventing metal.Type: GrantFiled: October 26, 2015Date of Patent: May 8, 2018Assignee: Mitsubishi Electric CorporationInventor: Kohei Nishiguchi
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Patent number: 9941401Abstract: A semiconductor device includes a semiconductor stacked structure in which a semiconductor layer including an electron supply layer and an electron transit layer is stacked, and a gate electrode contacting with the semiconductor layer included in the semiconductor stacked structure or an insulating layer. The portion of the gate electrode contacting with the semiconductor layer or the insulating layer is an oxide of a metal configuring the portion of the gate electrode contacting with the semiconductor layer or the insulating layer.Type: GrantFiled: October 20, 2016Date of Patent: April 10, 2018Assignee: FUJITSU LIMITEDInventors: Shirou Ozaki, Kozo Makiyama, Naoya Okamoto
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Patent number: 9917027Abstract: A method for fabricating an integrated circuit includes forming a first opening in an upper dielectric layer, the first opening having a first width, forming a second opening in a lower dielectric layer, the lower dielectric layer being below the upper dielectric layer, the second opening having a second width that is narrower than the first width, the second opening being substantially centered underneath the first opening so as to form a stepped via structure, conformally depositing an aluminum material layer in the stepped via structure and over the upper dielectric layer, and forming a passivation layer over the aluminum material layer.Type: GrantFiled: December 30, 2015Date of Patent: March 13, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wanbing Yi, Mahesh Bhatkar, Chin Chuan Neo, Juan Boon Tan
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Patent number: 9899500Abstract: A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed.Type: GrantFiled: May 5, 2014Date of Patent: February 20, 2018Assignee: NXP USA, INC.Inventors: Weize Chen, Xin Lin, Patrice M. Parris
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Patent number: 9887718Abstract: A radio-frequency module includes a multilayer substrate, an input switch, an output switch, and filters. A switch IC is disposed on a main surface of the multilayer substrate. The input switch is disposed in the switch IC and includes a first input terminal and first output terminals. The output switch is disposed in the switch IC and includes second input terminals and a second output terminal. The filters are disposed outside the switch IC and are connected to the first output terminals and the second input terminals. In a plan view of the multilayer substrate, the first input terminal and the first output terminals are disposed close to a first side of an exterior of the switch IC, and the second input terminals and the second output terminal are disposed close to a second side different from the first side of the exterior of the switch IC.Type: GrantFiled: October 18, 2016Date of Patent: February 6, 2018Assignee: Murata Manufacturing Co., Ltd.Inventor: Takashi Watanabe
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Patent number: 9882041Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.Type: GrantFiled: November 17, 2016Date of Patent: January 30, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jungwoo Joh, Naveen Tipirneni, Chang Soo Suh, Sameer Pendharkar
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Patent number: 9847781Abstract: A radio frequency switch may include a common port transmitting and receiving a radio frequency signal, a first switching unit including a plurality of first switch elements connected in series and opening or closing a signal transfer path between a first port inputting and outputting the radio frequency signal and the common port, and a second switching unit having a plurality of second switch elements connected in series and opening or closing a signal transfer path between a second port inputting and outputting the radio frequency signal and the common port. The second switching unit further includes a first filter circuit unit connected to a control terminal of at least one second switch element among the plurality of second switch elements to remove at least one preset frequency band signal.Type: GrantFiled: January 29, 2015Date of Patent: December 19, 2017Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Yoo Sam Na, Jong Myeong Kim, Hyun Jin Yoo, Hyun Hwan Yoo, Yoo Hwan Kim
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Patent number: 9722059Abstract: There are disclosed herein various implementations of a latch-up free power transistor. Such a device includes an insulated gate situated adjacent to a conduction channel in the power transistor, an emitter electrode in direct physical contact with the conduction channel, and a collector electrode in electrical contact with the conduction channel. The power transistor also includes an emitter layer in contact with a surface of a semiconductor substrate adjacent the conduction channel.Type: GrantFiled: August 21, 2015Date of Patent: August 1, 2017Assignee: Infineon Technologies AGInventor: Alim Karmous
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Patent number: 9722037Abstract: An embodiment of a compound semiconductor device includes: a substrate; a nitride compound semiconductor stacked structure formed on or above the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. A recess positioning between the gate electrode and the drain electrode in a plan view is formed at a surface of the compound semiconductor stacked structure.Type: GrantFiled: March 21, 2016Date of Patent: August 1, 2017Assignee: FUJITSU LIMITEDInventor: Kozo Makiyama
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Patent number: 9647076Abstract: A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal.Type: GrantFiled: April 12, 2016Date of Patent: May 9, 2017Assignee: Sensor Electronic Technology, Inc.Inventors: Grigory Simin, Michael Shur, Remigijus Gaska
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Patent number: 9634004Abstract: Semiconductor devices include a passivating layer over a pair of fins. A barrier extends through the passivating layer and between the pair of fins and that electrically isolates the fins. Electrical contacts are formed through the passivating layer to the fins. The electrical contacts directly contact sidewalls of the barrier.Type: GrantFiled: June 14, 2016Date of Patent: April 25, 2017Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.Inventors: Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie, Tenko Yamashita