Abstract: Complementary Modulation-Doped Field-Effect Transistors (CMODFETs) using a heterostructure based Silicon and Germanium alloys are described. The design of the Si/Si.sub.1-x Ge.sub.x -based CMODFET is also presented and shown to enable both n-channel or p-channel transport between source and drain implantation regions of the carriers with mobilities enhanced by 1) low ionized dopant scattering phenomena and 2) discretization of the free carrier energy due to quantum confinement.

Abstract: A field-effect transistor has its gate length made to be minute, and a short channel effect is prevented. The field-effect transistor which attains the above objects has first and second semiconductor regions having different impurity concentrations disposed so as to be adjacent to each other. A source electrode is disposed on the second semiconductor region with a high impurity concentration, a drain electrode on the first semiconductor region with a low impurity concentration, and a gate electrode on the first semiconductor region side of the second semiconductor region.

Abstract: A semiconductor device includes a semiconductor substrate having a surface; an active layer of a compound semiconductor disposed at the surface of the semiconductor substrate; and a Schottky barrier gate electrode including a multi-layer film alternately laminating a conductive refractory metal compound layer including a first refractory metal (M.sub.1) and a second refractory metal (M.sub.2) layer to three or more layers respectively, disposed on the active layer, thereby forming a Schottky junction with the active layer. The gate resistance of the Schottky barrier gate electrode can be held low and the internal stress can be reduced, whereby peeling off of the can be suppressed.

Abstract: A FET has comb-shaped electrode assemblies for source, drain and gate of the FET. Each of the source and drain electrode assemblies has a plurality of electrodes contacting the active region of the FET and formed as a first layer metal laminate, and a bus bar connecting the electrodes together to a corresponding pad and formed as a second layer metal laminate. The gate electrode layer has a plurality of gate electrodes contacting the active layer in Schottky contact, a gate bus bar connecting the gate electrodes together, a gate pad connected to the gate bus bar. The gate bus bar is formed as a first layer metal laminate intersecting the stem portion of the comb-shaped source bus bar. The two-layer metal structure of the FET reduces the number of photolithographic steps and thereby fabrication costs of the FET.

Abstract: A MOSFET device is constructed with an integrated Schottky diode clamp connected between the source or drain terminal and the bulk terminal. In an illustrative implementation, one or more MOSFETs are formed in an n-well located in a p-type silicon substrate. Each drain is formed by a p+ region underlying a portion of a metal-silicide layer. In one embodiment, the p+ region underlies an edge of the metal-silicide; in another embodiment, the p+ region underlies opposing edges of the metal-silicide, such that a portion of the metal-silicide contacts the n-well. Each source is formed by a p+ region underlying a layer of metal-silicide. Each gate includes a layer of p+ or n+ polycrystalline silicon clad with a layer of metal-silicide, the gates being separated from the n-well by a layer of oxide. In comparison to p-n junction diodes, the integrated Schottky diodes more effectively limit excess voltages applied to MOSFETs.

Abstract: In a recessed structure MESFET, an active layer (n-type layer) 2 is provided on a high resistance GaAs substrate 1, a pair of contact layers (n.sup.+ -type layers) 31, 32 is provided on the active layer 2, a source electrode 6 is provided on one contact layer 31, a drain electrode 7 is provided on the other contact layer 32 and a gate electrode 5 is provided on the active layer 2 to achieve a recessed structure. A semiconductor layer 4 having a lower impurity density than that of the contact layer 31, 32 is formed at the recess edge portion at at least drain side to alleviate the concentration of the electric field and current there to suppress the generation of electron-holes pairs by collision ionization to reduce the damage to the crystal lattice by non-luminescence recombination of the electron-holes thus preventing the degradation of the FET characteristics.

Abstract: A dual gate field effect transistor including first and second gates comprises a conductive region, wherein a potential difference between a second gate electrode section and the conductive region is larger than that between the second gate electrode section and a channel operation region.

Abstract: The present invention is to provide a static induction semiconductor device with a distributed main electrode structure and a static induction semiconductor device with a static induction main electrode shorted structure where the main electrode region is composed of regions of higher and lower impurity densities relative to each other and formed partly in contact with the lower impurity density region as well, and alternatively a static induction short-circuit region opposite in conductivity type to the main electrode region is formed in the lower impurity density region surrounded by the higher impurity density region.

Abstract: It is an object of the present invention to provide a dual-gate type MESFET having a high drain breakdown voltage and excellent high-frequency characteristics. A semiconductor substrate used in the present invention is obtained by sequentially forming a non-doped buffer layer 2, a thin first pulse-doped layer 3 having a high impurity concentration, and a cap layer 7 on an underlying semiconductor substrate 1 by epitaxial growth. The cap layer 7 has a thin second pulse-doped layer 5 having a high impurity concentration sandwiched between non-doped layers 4 and 6. The thickness and impurity concentration of the second pulse-doped layer 5 are set such that the second pulse-doped layer 5 is depleted by a surface depletion layer caused by the interface state of the cap layer surface, and the surface depletion layer does not extend to the first pulse-doped layer 3. A source electrode 13, a drain electrode 16, and first and second gate electrodes 14 and 15 are formed on the semiconductor substrate surface.

Abstract: Germanium is used to significantly enhance the drift mobilities of minority carriers in the channels of N-channel and P-channel metal-oxide-semiconductor (MOS) transistors with silicon substrates. Germanium processing is also used to enhance the source/drain contact conductance for MOS devices. Methods are disclosed for forming the germanium-rich interfacial layer utilizing a germanium implant and wet oxidation or growing a silicon-germanium alloy by molecular beam epitaxy.

Abstract: A compound semiconductor device includes an undoped semiconductor layer; a doped semiconductor layer formed on the undoped semiconductor layer and having smaller electron affinity than the undoped semiconductor layer; a gate electrode formed on the doped semiconductor layer; a cap layer formed on the doped semiconductor layer; and a source electrode and a drain electrode respectively formed on the cap layer. In the device, an undoped-material layer having greater electron affinity than the doped semiconductor layer and the cap layer, is formed between the doped semiconductor layer and the cap layer. A layer which has the same composition and impurities as those of the doped semiconductor layer and whose impurity concentration is sufficiently higher than an impurity concentration of the doped semiconductor layer may, be provided between the doped semiconductor layer and the cap layer.

Abstract: An advanced MESFET switching structure which includes an interdigitated source region and an interdigitated drain region, also includes a gate electrode region disposed between adjacent portions of the interdigitated source and drain regions having a series gate electrode in Schottky barrier contact therewith. The use of the series connect gate electrode rather than conventional parallel coupled gate fingers eliminates the need for an airbridge overlays to interconnect the source regions as in a conventional MESFET transducer. Moreover, the topography permits smaller MESFET structures and thus higher integration of circuits employing the advanced MESFET switch structure. The smaller transistors will also have lower parasitic reactances. In a preferred embodiment, all interconnections for drain, gate, and source electrodes are disposed on the active layer portion of the transistor providing an even smaller transistor structure.

Abstract: A field-effect transistor in which a metal gate (14) is defined on top of an insulating substrate (12). A free-standing semiconductor thin film (16), obtained by the epitaxial lift-off process, is bonded to both the top of the metal gate and the insulating substrate. Electrodes (20, 22) attached to the top of ends of the semiconductor film complete the transistor.

Abstract: Germanium is used to significantly enhance the drift mobilities of minority carriers in the channels of N-channel and P-channel metal-oxide-semiconductor (MOS) transistors with silicon substrates. Germanium processing is also used to enhance the source/drain contact conductance for MOS devices. Methods are disclosed for forming a germanium-rich interfacial layer utilizing a germanium implant and wet oxidation or growing a silicon-germanium alloy by molecular beam epitaxy.

Abstract: A Schottky diode is presented which has reduced minority carrier injection and reduced diffusion of the metallization into the semiconductor. These improvements are obtained by interposing a layer comprising a mixture of silicon and chromium between the anode metallization layer and the semiconductor in a Schottky diode. The layer including chromium acts an effective barrier against the diffusion of the metallization layer into the semiconductor, and at the same time reduces the amount of minority carrier injection into the substrate. The layer including chromium requires no addition photolithograpic masks because it can be plasma etched using the metallization layer as a mask after that layer has been patterned.

Abstract: Germanium is used to significantly enhance the drift mobilities of minority carriers in the channels of N-channel and P-channel metal-oxide-semiconductor (MOS) transistors with silicon substrates. Germanium processing is also used to enhance the source/drain contact conductance for MOS devices. Methods are disclosed for forming the germanium-rich interfacial layer utilizing a germanium implant and wet oxidation or growing a silicon-germanium alloy by molecular beam epitaxy.

Abstract: Electrical ohmic contacts are made to a matrix of silicon having conductive rods embedded therein without making contact to any of the rods. Those rods which extend to the surface in the selected area of the matrix to be contacted are etched to form holes. The holes are filled with insulating polycrystalline silicon. The region of the selected area is heavily doped, and an ohmic contact member is made thereto. The underlying rods are spaced from the ohmic contact member and the heavily-doped region by intervening polycrystalline silicon.

Abstract: A structure for modulating electrostatic potential in the vicinity of a surface of a structure comprises: a substrate; a first electrically conductive layer having an exposed surface and made of a first electrically conducive material formed on the subrate, the first electrically conductive material disposed to being transformed into an electrically insulting material; an electrically insulating layer formed on the surface of the first layer from the first electrically conducive material; and a second layer of a second electrically conductive material formed on the substrate and contiguous with the insulating layer so that a voltage potential between said first and second layers provides an electrostatic interaction with the substrate.

Abstract: A semiconductor device wherein a bipolar transistor and a junction type field effect transistor which has a high voltage resisting property and a high mutual conductance are formed into a single chip to reduce the cost. A bipolar transistor formation region is separated from a junction type field effect transistor formation region by a transistor separating region. In the former region, a collector diffused layer is formed on the semiconductor substrate on which an epitaxial layer is formed, and a base diffused layer and a collector lead diffused layer are formed in the epitaxial layer with an element separating region interposed therebetween and connect to the collector diffused layer. Further, an emitter diffused layer is formed on the base diffused layer. In the latter region, a bottom gate diffused layer is formed on the semiconductor substrate, and a channel formation region is formed in the epitaxial layer and connects to the bottom gate diffused layer.

Abstract: In a semiconductor device, an interconnection of differentially doped diffusion regions formed on a substrate includes an interconnecting layer disposed between the two diffusion regions so that the two regions are coupled to one another. The interconnect region is defined by the existing mask boundaries of N+ dopant and P+ dopant regions such that N+ and P+ dopant is not allowed to enter the interconnect region. Thus, the interconnect region is defined without requiring additional masking and etching steps. Once the interconnect region is defined, then the interconnecting layer is formed by a deposition and sintering process. The interconnecting layer provides a schottky barrier and ohmic contact.

Abstract: An SB FET comprising source and drain regions formed in the surface of a gallium arsenide (GaAs) substrate, and a channel region formed between the source and drain regions. The gate electrode of the SB FET is formed on the channel region in Schottky contact therewith. The SB FET further comprises source and drain electrodes which are mounted on the source and drain regions in ohmic contact therewith, while being separated from each other at a greater distance than the length of the channel region.