With Means For Preventing Charge Leakage Due To Minority Carrier Generation (e.g., Alpha Generated Soft Error Protection Or "dark Current" Leakage Protection) Patents (Class 257/297)
  • Patent number: 10290647
    Abstract: A source select level silicon nitride layer and an alternating stack of insulating layers and sacrificial silicon nitride layers are formed over a substrate. A memory opening is formed through the alternating stack and the source select level silicon nitride layer. The source select level silicon nitride layer is laterally recessed farther than the sacrificial silicon nitride layers employing an isotropic etch process. A pedestal channel portion including a laterally protruding annular portion is formed at a bottom region of the memory opening. A memory stack structure is formed on the pedestal channel portion in the memory opening. The source select level silicon nitride layer and the sacrificial silicon nitride layers are replaced with a source select level electrically conductive layer and word line electrically conductive layers, respectively.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: May 14, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masato Noguchi, Junichi Sato
  • Patent number: 10217647
    Abstract: A method of manufacturing a semiconductor device may include forming active patterns, forming a polygonal mask pattern having a first width and a second width on the active patterns, forming an active region by executing a first etching process using the mask pattern, forming a first cutting mask for removing a first corner rounding in which a width of the active region is the first width, removing the first corner rounding by executing a second etching process using the first cutting mask, forming a second cutting mask for removing a second corner rounding in which the width of the active region is changed from the first width to the second width, and executing a third etching process using the second cutting mask.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: February 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ho Do, Jonghoon Jung, Sanghoon Baek, Seungyoung Lee, Taejoong Song, Jinyoung Lim
  • Patent number: 10204687
    Abstract: A semiconductor integrated circuit includes a first circuit, a second circuit, a memory circuit having a plurality of flip-flops, a storage unit, a signal generating unit to produce an operation mode setting signal, a control circuit configured to cause the memory circuit to operate such that the plurality of flip-flops holds a value for setting characteristics of the first circuit when the operation mode setting signal indicates a first operation mode, and configured to cause the memory circuit to operate as a counter to measure a time length used in the second circuit when the operation mode setting signal indicates a second operation mode, and a setting circuit configured to cause trimming data stored in the storage unit to set the characteristic of the first circuit when the operation mode setting signal indicates the second operation mode, the trimming data corresponding to the value held by the memory circuit.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: February 12, 2019
    Assignee: MISUMI ELECTRIC CO., LTD.
    Inventor: Takeshi Yamaguchi
  • Patent number: 10181469
    Abstract: Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: January 15, 2019
    Assignee: SOCIONEXT INC.
    Inventor: Hiroyuki Shimbo
  • Patent number: 10163628
    Abstract: A structure includes a substrate including a first semiconductor material; a dielectric feature embedded in the substrate; and a second semiconductor material embedded in the substrate, the second semiconductor material having lattice mismatch to the first semiconductor material, the second semiconductor material having two upper sidewalls and two lower sidewalls, the two upper sidewalls in contact with the dielectric feature, the two lower sidewalls in contact with the substrate, the two lower sidewalls being non-perpendicular to a top surface of the substrate, a bottommost portion of the dielectric feature being lower than a topmost portion of the two lower sidewalls.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hsien Wu, I-Sheng Chen
  • Patent number: 10158043
    Abstract: A method for manufacturing a light-emitting diode (LED) includes plural steps as follows. A first type semiconductor layer is formed. A second type semiconductor layer is formed on the first type semiconductor layer. An impurity is implanted into a first portion of the second type semiconductor layer. The concentration of the impurity present in the first portion of the second type semiconductor layer is greater than the concentration of the impurity present in a second portion of the second type semiconductor layer after the implanting, such that the resistivity of the first portion of the second type semiconductor layer is greater than the resistivity of the second portion of the second type semiconductor layer.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: December 18, 2018
    Assignee: MIKRO MESA TECHNOLGY CO., LTD.
    Inventors: Li-Yi Chen, Pei-Yu Chang, Hsin-Wei Lee, Chun-Yi Chang, Shih-Chyn Lin
  • Patent number: 9842841
    Abstract: A method of fabricating a semiconductor device, the method including etching a portion of a substrate including a first region and a second region to form a device isolation trench; forming a device isolation layer defining active regions by sequentially stacking a first insulating layer, a second insulating layer, and a third insulating layer on an inner surface of the device isolation trench; forming word lines buried in the substrate of the first region, the word lines extending in a first direction to intersect the active region of the first region, the word lines being spaced apart from each other; forming a first mask layer covering the word lines on the substrate of the first region, the first mask layer exposing the substrate of the second region; forming a channel layer on the substrate of the second region; and forming a gate electrode on the channel layer.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: December 12, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Hun Kim, Ilgweon Kim, Junhwa Song, Jeonghoon Oh, WonSeok Yoo, Eun-Sun Lee
  • Patent number: 9761688
    Abstract: A method for fabricating a semiconductor device may include: preparing a semiconductor substrate including a doping region; performing tilt implantation using a first additional dopant to form an amorphous region in the doping region; doping a second additional dopant in the amorphous region; forming a metal layer on the doped amorphous region; and reacting the doped amorphous region with the metal layer to form metal silicide.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: September 12, 2017
    Assignee: SK Hynix Inc.
    Inventors: Jae-Chun Cha, An-Bae Lee, Ah-Young Oh
  • Patent number: 9564431
    Abstract: A semiconductor structure is provided comprising a vertical channel structure extending from a substrate and formed as a channel between a source region and a drain region. The semiconductor structure further comprises a metal gate that surrounds a portion of the vertical channel structure. The metal gate has a gate length. The metal gate has a first gate section with a first workfunction and a first thickness. The metal gate also has a second gate section with a second workfunction and a second thickness. The first thickness level is different from the second thickness level and the sum of the first thickness level and the second thickness level is equal to the gate length. The ratio of the first thickness level to the second thickness level for the gate length was chosen to achieve a threshold voltage level for the semiconductor device.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Chia-Wen Liu, Wei-Hao Wu, Chih-Hao Wang, Carlos H. Diaz
  • Patent number: 9514998
    Abstract: A method of forming a polysilicon resistor in replacement metal gate (RMG) processing of finFET devices includes forming a plurality of semiconductor fins over a buried oxide layer of a silicon-on-insulator substrate; forming a trench in the buried oxide layer; forming a polysilicon layer over the semiconductor fins and in the trench, the polysilicon layer having a depression corresponding to a location of the trench; forming an insulating layer over the polysilicon layer, and performing a planarizing operation to remove the insulating layer except for a portion of the insulating layer formed in the depression, thereby defining a protective island; patterning the polysilicon layer to define both a dummy gate structure over the fins and the polysilicon resistor; and etching the polysilicon layer to remove the dummy gate structure, wherein the protective island prevents the polysilicon resistor from being removed.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: December 6, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Huiming Bu, Tenko Yamashita
  • Patent number: 9502313
    Abstract: A method of forming a polysilicon resistor in replacement metal gate (RMG) processing of finFET devices includes forming a plurality of semiconductor fins over a buried oxide layer of a silicon-on-insulator substrate; forming a trench in the buried oxide layer; forming a polysilicon layer over the semiconductor fins and in the trench, the polysilicon layer having a depression corresponding to a location of the trench; forming an insulating layer over the polysilicon layer, and performing a planarizing operation to remove the insulating layer except for a portion of the insulating layer formed in the depression, thereby defining a protective island; patterning the polysilicon layer to define both a dummy gate structure over the fins and the polysilicon resistor; and etching the polysilicon layer to remove the dummy gate structure, wherein the protective island prevents the polysilicon resistor from being removed.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: November 22, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Huiming Bu, Tenko Yamashita
  • Patent number: 9484445
    Abstract: An n-type low lifetime adjustment region is provided in a portion inside an n? type drift region deeper than the bottom surface of a termination p-type base region or p-type guard ring from a substrate front surface, separated from the termination p-type base region and the p-type guard ring. The carrier lifetime of the n-type low lifetime adjustment region is shorter than the carrier lifetime of the n? type drift region. Because of this, it is possible to provide a reverse blocking IGBT such that it is possible to suppress both a high temperature reverse leakage current and an increase in turn-off loss, while suppressing deterioration in the trade-off relationship between the turn-off loss and the on-state voltage.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: November 1, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hong-fei Lu
  • Patent number: 9337151
    Abstract: Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate having a contact region. An interlayer insulating layer is disposed on the semiconductor substrate. A lower contact plug passing through the interlayer insulating layer and electrically connected to the contact region is disposed. An interconnection structure is disposed on the interlayer insulating layer. An adjacent interconnection spaced apart from the interconnection structure is disposed on the interlayer insulating layer. A bottom surface of the interconnection structure includes a first part overlapping a part of an upper surface of the lower contact plug, and a second part overlapping the interlayer insulating layer.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: May 10, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je-Min Park, Yoo-Sang Hwang
  • Patent number: 9312021
    Abstract: Provided are a cell string and a reading method for the cell string. The cell string includes a semiconductor body formed on a surface of an insulating layer, first and second semiconductor regions formed at respective ends of the semiconductor body and are formed by being doped with different types of impurities, two or more control electrodes which are separated from each other to be electrically isolated, and a gate insulating film stack which is formed between the semiconductor body and the control electrodes, wherein the semiconductor body is configured to include at least two layers, and adjacent layers of the semiconductor body have different energy band gaps, wherein the semiconductor body is formed by an intrinsic semiconductor or a semiconductor being doped with impurities, and wherein the first and second semiconductor regions are doped with impurities of which concentration is higher than that of the semiconductor body.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: April 12, 2016
    Assignee: SNU R&DB FOUNDATION
    Inventors: Jong-Ho Lee, Sung-Min Joe
  • Publication number: 20150085585
    Abstract: A nonvolatile memory (“NVM”) bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The transistor is used to read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read, write, and/or erase operations.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 26, 2015
    Applicant: Synopsys, Inc.
    Inventors: Andrew E. Horch, Troy N. Gilliland
  • Patent number: 8975128
    Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: March 10, 2015
    Assignee: SuVolta, Inc.
    Inventors: Scott E. Thompson, Damodar R. Thummalapally
  • Patent number: 8952462
    Abstract: The present disclosure provides an apparatus that includes a semiconductor device. The semiconductor device includes a substrate. The semiconductor device also includes a first gate dielectric layer that is disposed over the substrate. The first gate dielectric layer includes a first material. The first gate dielectric layer has a first thickness that is less than a threshold thickness at which a portion of the first material of the first gate dielectric layer begins to crystallize. The semiconductor device also includes a second gate dielectric layer that is disposed over the first gate dielectric layer. The second gate dielectric layer includes a second material that is different from the first material. The second gate dielectric layer has a second thickness that is less than a threshold thickness at which a portion of the second material of the second gate dielectric layer begins to crystallize.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Hao Chen, Da-Yuan Lee, Kuang-Yuan Hsu
  • Patent number: 8928062
    Abstract: A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells formed on a semiconductor substrate, each memory cell including source and drain regions separately formed on a surface portion of the substrate, buried insulating films formed in portions of the substrate that lie under the source and drain regions and each having a dielectric constant smaller than that of the substrate, a tunnel insulating film formed on a channel region formed between the source and drain regions, a charge storage layer formed of a dielectric body on the tunnel insulating film, a block insulating film formed on the charge storage layer, and a control gate electrode formed on the block insulating film.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: January 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoki Yasuda
  • Patent number: 8890223
    Abstract: An integrated circuit includes isolation capacitors which include a silicon dioxide dielectric layer and a polymer dielectric layer over the layer of silicon dioxide. The silicon dioxide dielectric layer and the polymer dielectric layer extend across the integrated circuit. Top plates of the isolation capacitors have bond pads for wire bonds or bump bonds. Bottom plates of the isolation capacitors are connected to components of the integrated circuit. Other bond pads are connected to components in the integrated circuit through vias through the silicon dioxide dielectric layer and the polymer dielectric layer.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: November 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas Dyer Bonifield, Byron Williams, Shrinivasan Jaganathan
  • Publication number: 20140299927
    Abstract: Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS); correcting circuits (34, 36) connected between an input terminal (IN) inputted with an input signal and control terminals (gates) of the first transistors; capacitors (C2, C3) connected between the control terminals and the input terminal; diode-connected second transistors (35, 37) that are provided between nodes (N5, N6) between the capacitors and the control terminals and the power supply potentials and have the substantially same threshold voltage as the first transistors; and switches (SW2, SW3) connected in series with the second transistors.
    Type: Application
    Filed: April 11, 2014
    Publication date: October 9, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 8816419
    Abstract: Provided is a semiconductor device having a high switching speed. A semiconductor device is provided with an n-type epitaxial layer having a plurality of trenches arranged at prescribed intervals; an embedded electrode formed on an inner surface of the trench through a silicon oxide film to embed each trench; and a metal layer, which is capacitively coupled with the embedded electrode by being arranged above the embedded electrode through a silicon oxide film. In the semiconductor device, a region between the adjacent trenches operates as a channel (current path). A current flowing in the channel is interrupted by covering the region with a depletion layer formed at the periphery of the trenches, and the current is permitted to flow through the channel by eliminating the depletion layer at the periphery of the trenches.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: August 26, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Patent number: 8809922
    Abstract: Disclosed is a solid-state image sensing device including: a first photoelectric conversion element having a first semiconductor region of a first conductivity type formed inside a semiconductor substrate; a second photoelectric conversion element having a second semiconductor region of a first conductivity type formed at a deeper position of the semiconductor substrate than the first photoelectric conversion element; a gate electrode laminated on the semiconductor substrate and to which a predetermined voltage is applied at a charge transfer time; a floating diffusion region to which the charges accumulated in the first photoelectric conversion element and the second photoelectric conversion element are transferred at the charge transfer time; and a third semiconductor region of a first conductivity type arranged between the first semiconductor region and the second semiconductor region in a depth direction of the semiconductor.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: August 19, 2014
    Assignee: Sony Corporation
    Inventors: Hitoshi Moriya, Hiroaki Ishiwata, Kazuyoshi Yamashita, Hiroyuki Mori
  • Patent number: 8809929
    Abstract: Memory devices comprise a lower layer that extends across a cell array region and across a peripheral region and that includes a flat outer surface from the cell array region to the peripheral region. A signal transfer conductor layer extends in the cell array region beneath the flat outer surface of the lower layer and extends in the peripheral region above the flat outer surface of the lower layer. An insulating layer is provided on the lower layer, including a flat outer surface from the cell array region to the peripheral region. A flat stopper layer is provided on the flat outer surface of the insulating layer and extending across the cell array region and the peripheral region. Related methods are also provided.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wonmo Park, Hyunchul Kim, Hyodong Ban, Hyunju Lee
  • Patent number: 8785998
    Abstract: A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung-woo Chung, Yong-chul Oh, Yoo-sang Hwang, Gyo-young Jin, Hyeong-sun Hong, Dae-ik Kim
  • Patent number: 8759875
    Abstract: A memory cell is disclosed. The memory cell includes a vertical base disposed on a substrate. The vertical base includes first and second channels between top and bottom terminals. The memory cell also includes a first gate surrounding the first channel and a second gate surrounding the second channel. The first and second gates form a gate-all-around transistor of the memory cell.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: June 24, 2014
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Ping Zheng, Eng Huat Toh, Yuan Sun
  • Patent number: 8728919
    Abstract: A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Megumi Ishiduki, Yosuke Komori, Hiroyasu Tanaka, Ryota Katsumata, Hideaki Aochi
  • Patent number: 8723242
    Abstract: A non-volatile semiconductor memory device and a method of manufacturing the same of the embodiments are provided. The non-volatile semiconductor memory device includes: drain contact plugs formed in memory cell regions and having bottom ends joined to drain diffusion layers of the respective memory cells; a local interconnect provided to extend in a WL direction across the memory cell regions and a shunt region, and having a bottom end joined commonly to plural source diffusion layers; drain via plugs formed in the memory cell regions and having bottom ends joined to the top ends of the respective drain contact plugs; and a power supply via for source formed in the shunt region to extend in a BL direction, and having a bottom end joined to the top end of the local interconnect.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuhiro Asada
  • Patent number: 8643110
    Abstract: A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: February 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, John K. Zahurak
  • Patent number: 8604530
    Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 10, 2013
    Assignee: SuVolta, Inc.
    Inventors: Scott E. Thompson, Damodar R. Thummalapally
  • Patent number: 8598642
    Abstract: An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type. A floating gate rests on top of the well, and extends over a channel region, and at least a portion of the source and drain regions. The drain region comprises additional carriers of a second conductivity type, allowing band to band tunneling. The source region comprises additional carriers of a first conductivity type, thereby increasing source-gate capacitance. Thus, the bitcell incorporates a select device, thereby decreasing the overall size of the bitcell. The bitcell may be created without any additional CMOS process steps, or through the addition of a single extra mask step.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: December 3, 2013
    Assignee: Synopsys, Inc.
    Inventor: Andrew E. Horch
  • Patent number: 8592883
    Abstract: An embodiment may be a semiconductor structure, comprising; a workpiece having a front side and a back side; and a capacitor disposed in the workpiece, the capacitor including a bottom electrode electrically coupled to a back side of said workpiece. In an embodiment, the bottom electrode may form a conductive pathway to the front side of the workpiece. In an embodiment, the capacitor may be a trench capacitor.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: November 26, 2013
    Assignee: Infineon Technologies AG
    Inventors: Dieter Claeys, Bernd Eisener, Guenter Pfeifer, Detlef Wilhelm
  • Patent number: 8536638
    Abstract: A semiconductor device includes a bit line that is provided in a semiconductor substrate, a silicide layer that has side faces and a bottom face surrounded by the bit line and is provided within the bit line, an ONO film that is provided on the semiconductor substrate, and sidewalls that are in contact with the side faces of a trapping layer in the ONO film over the portions of the bit line located on both sides of the silicide layer, the sidewalls being formed with silicon oxide films including phosphorus.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: September 17, 2013
    Assignee: Spansion LLC
    Inventors: Yukihiro Utsuno, Namjin Heo
  • Patent number: 8536625
    Abstract: An electronic image sensor includes a semiconductor substrate having a first surface configured for accepting illumination to a pixel array disposed in the substrate. An electrically-doped channel region for each pixel is disposed at a second substrate surface opposite the first substrate surface. The channel regions are for collecting photogenerated charge in the substrate. An electrically-doped channel stop region is at the second substrate surface between each channel region. An electrically-doped shutter buried layer, disposed in the substrate at a depth from the second substrate surface that is greater than that of the pixel channel regions, extends across the pixel array. An electrically-doped photogenerated-charge-extinguishment layer, at the first substrate surface, extends across the pixel array.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: September 17, 2013
    Assignee: Massachusetts Institute of Technology
    Inventor: Barry E. Burke
  • Patent number: 8450783
    Abstract: The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: May 28, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato, Shuhei Nagatsuka, Takanori Matsuzaki, Hiroki Inoue
  • Patent number: 8435873
    Abstract: One embodiment of the invention relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric interface surface that laterally extends around a perimeter of the recessed region. The diode further includes an anode that conforms to the recessed region. A dielectric layer extends over the dielectric interface surface of the cathode and further extends over a portion of the anode near the perimeter. Other devices and methods are also disclosed.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: May 7, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Vladimir Frank Drobny
  • Patent number: 8415749
    Abstract: Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: April 9, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Tsung Huang, Kou-Cheng Wu, Carlos H. Diaz
  • Patent number: 8357953
    Abstract: Embodiments of the present invention provide a bipolar transistor with low resistance base contact and method of manufacturing the same. The bipolar transistor includes an emitter, a collector, and an intrinsic base between the emitter and the collector. The intrinsic base extends laterally to an extrinsic base. The extrinsic base further includes a first semiconductor material with a first bandgap and a second semiconductor material with a second bandgap that is smaller than the first bandgap.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: January 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Francois Pagette, Kathryn Turner Schonenberg
  • Patent number: 8357963
    Abstract: A semiconductor device includes a material with which off-state current of a transistor can be sufficiently small; for example, an oxide semiconductor material is used. Further, transistors of memory cells of the semiconductor device, which include an oxide semiconductor material, are connected in series. Further, the same wiring (the j-th word line (j is a natural number greater than or equal to 2 and less than or equal to m)) is used as a wiring electrically connected to one of terminals of a capacitor of the j-th memory cell and a wiring electrically connected to a gate terminal of a transistor, in which a channel is formed in an oxide semiconductor layer, of the (j?1)-th memory cell. Therefore, the number of wirings per memory cell and the area occupied by one memory cell are reduced.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: January 22, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Takanori Matsuzaki
  • Patent number: 8354660
    Abstract: In a first aspect, an MIM stack is provided that includes (1) a first conductive layer comprising a first metal-silicide layer and a second metal-silicide layer; (2) a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer; and (3) a second conductive layer formed above the resistivity-switching layer. A memory cell may be formed from the MIM stack. Numerous other aspects are provided.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: January 15, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Deepak Chandra Sekar, Franz Kreupl, Raghuveer S. Makala
  • Patent number: 8330198
    Abstract: A device for preventing current-leakage is located between a transistor and a capacitor of a memory cell. The two terminals of the device for preventing current-leakage are respectively connected with a slave terminal of the transistor and an electric pole of the capacitor. The device for preventing current-leakage has at least two p-n junctions. The device for preventing current-leakage is a lateral silicon controlled rectifier, a diode for alternating current, or a silicon controlled rectifier. By utilizing the driving characteristic of the device for preventing current-leakage, electric charge stored in the capacitor hardly passes through the device for preventing current-leakage when the transistor is turned off to improve the current-leakage problem.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: December 11, 2012
    Assignee: Inotera Memories, Inc.
    Inventors: Shin Bin Huang, Chung-Lin Huang, Ching-Nan Hsiao, Tzung Han Lee
  • Patent number: 8278692
    Abstract: In some embodiments, complementary charge-collecting diffusions (transistor diffusions, e.g., drain or source areas) are disposed close to each other. In some embodiments, dummy (“off”) transistors are incorporated to bring complementary diffusions (diffusions of the same charge type and having complementary digital logic levels) closer to each other than otherwise might be possible and thus, to enhance common-mode charge collection for the complementary diffusion areas.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: October 2, 2012
    Assignee: Intel Corporation
    Inventors: Vinod J. Ambrose, Jeffrey D. Pickholtz, Randy L. Allmon
  • Patent number: 8273648
    Abstract: Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Choongyeun Cho, Daeik Kim, Jonghae Kim, Moon Ju Kim, James R. Moulic
  • Patent number: 8263462
    Abstract: A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: September 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ting Hung, Cheng-Hung Chang, Chen-Yi Lee, Chen-Nan Yeh, Chen-Hua Yu
  • Patent number: 8227846
    Abstract: A decoupling capacitor includes a pair of MOS capacitors formed in wells of opposite plurality. Each MOS capacitor has a set of well-ties and a high-dose implant, allowing high frequency performance under accumulation or depletion biasing. The top conductor of each MOS capacitor is electrically coupled to the well-ties of the other MOS capacitor and biased consistently with logic transistor wells. The well-ties and/or the high-dose implants of the MOS capacitors exhibit asymmetry with respect to their dopant polarities.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: July 24, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Andrew E. Carlson
  • Patent number: 8193568
    Abstract: Some embodiments include memory cells that contain a dynamic random access memory (DRAM) element and a nonvolatile memory (NVM) element. The DRAM element contains two types of DRAM nanoparticles that differ in work function. The NVM contains two types of NVM nanoparticles that differ in trapping depth. The NVM nanoparticles may be in vertically displaced charge-trapping planes. The memory cell contains a tunnel dielectric, and one of the charge-trapping planes of the NVM may be further from the tunnel dielectric than the other. The NVM charge-trapping plane that is further from the tunnel dielectric may contain larger NVM nanoparticles than the other NVM charge-trapping plane. The DRAM element may contain a single charge-trapping plane that has both types of DRAM nanoparticles therein. The memory cells may be incorporated into electronic systems.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: June 5, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 8164128
    Abstract: Techniques for forming a magnetic device are provided. In one aspect, a magnetic device includes a magnetic tunnel junction and a dielectric layer formed over at least a portion of the magnetic tunnel junction. The dielectric layer is configured to have an underlayer proximate to the magnetic tunnel junction, and an overlayer on a side of the underlayer opposite the magnetic tunnel junction. The magnetic device further includes a via hole running substantially vertically through the dielectric layer and being self-aligned with the magnetic tunnel junction.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: April 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Sivananda K. Kanakasabapathy, Michael C. Gaidis
  • Patent number: 8159014
    Abstract: A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: April 17, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, John K. Zahurak
  • Publication number: 20120074478
    Abstract: As for a bypass capacitor, a first capacitor insulating film, together with a tunnel insulating film of a storage element, is formed of a first insulating film, a first electrode being a lower electrode, together with floating gate electrodes of the storage element, is formed of a doped·amorphous silicon film (a crystallized one), a second capacitor insulating film, together with a gate insulating film of transistors of 5 V in a peripheral circuit, is formed of a second insulating film, and a second electrode being an upper electrode, together with control gate electrodes of the storage element and gate electrodes of the transistors in the peripheral circuit, is formed of a polycrystalline silicon film.
    Type: Application
    Filed: June 28, 2011
    Publication date: March 29, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Tatsuya Sugimachi
  • Patent number: 8143664
    Abstract: A semiconductor device includes a bit line that is provided in a semiconductor substrate, a silicide layer that has side faces and a bottom face surrounded by the bit line and is provided within the bit line, an ONO film that is provided on the semiconductor substrate, and sidewalls that are in contact with the side faces of a trapping layer in the ONO film over the portions of the bit line located on both sides of the silicide layer, the sidewalls being formed with silicon oxide films including phosphorus.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: March 27, 2012
    Assignee: Spansion LLC
    Inventors: Yukihiro Utsuno, Namjin Heo
  • Patent number: 8138563
    Abstract: Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Choongyeun Cho, Daeik Kim, Jonghae Kim, Moon Ju Kim, James R. Moulic