Abstract: Provided are a resonance tunneling device and a method of manufacturing the resonance tunneling device. The resonance tunneling device includes a substrate, a plurality of electrodes disposed on the substrate, and a nanoparticle layer disposed between the electrodes, and doped with an impurity. The nanoparticle layer uses the impurity to exhibit resonance tunneling where a current peak occurs at a target bias voltage applied between the electrodes.

Abstract: A technique for a nanodevice is provided. A reservoir is separated into two parts by a membrane. A nanopore is formed through the membrane, and the nanopore connects the two parts of the reservoir. The nanopore and the two parts of the reservoir are filled with ionic buffer. The membrane includes a graphene layer and insulating layers. The graphene layer is wired to first and second metal pads to form a graphene transistor in which transistor current flowing through the graphene transistor is modulated by charges passing through the nanopore.

Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region.

Abstract: A nanogap sensor includes a first layer in which a micropore is formed; a graphene sheet disposed on the first layer and including a nanoelectrode region in which a nanogap is formed, the nanogap aligned with the micropore; a first electrode formed on the grapheme sheet; and a second electrode formed on the graphene sheet, wherein the first electrode and the second electrode are connected to respective ends of the nanoelectrode region.

Abstract: Patterns of a nonvolatile memory device include a semiconductor substrate including active regions extending in a longitudinal direction, an isolation structure formed between the active regions, a tunnel insulating layer formed on the active regions, a charge trap layer formed on the tunnel insulating layer, a first dielectric layer formed on the charge trap layer and the isolation structure, wherein the first dielectric layer is extended along a lateral direction, a control gate layer formed on the first dielectric layer, wherein the control gate layer is extended along the lateral direction, and a second dielectric layer formed on a sidewall of the control gate layer along the lateral direction and coupled to the first dielectric layer.

Abstract: A semiconductor device includes a substrate, first plural contacts formed in the substrate, a graphene layer formed on the substrate and on the first plural contacts and second plural contacts formed on the graphene layer such that the graphene layer is formed between the first plural contacts and the second plural contacts.

Abstract: Graphene FETs exhibit low power consumption and high switching rates taking advantage of the excellent mobility in graphene deposited on a rocksalt oxide (111) by chemical vapor deposition, plasma vapor deposition or molecular beam epitaxy. A source, drain and electrical contacts are formed on the graphene layer. These devices exhibit band gap phenomena on the order of greater than about 0.5 eV, easily high enough to serve as high speed low power logic devices. Integration of this construction technology, based on the successful deposition of few layer graphene on the rocksalt oxide (111) with SI CMOS is straightforward.

Abstract: A nanopore device comprising a channel unit comprising a micro channel defined by a bottom surface and an insulator lateral wall; and a cover unit covering the micro channel, wherein the cover unit comprises a nanopore extending through the cover unit and connected to the micro channel; a first source/drain electrode disposed on an upper surface of the cover unit and adjacent to an inlet of the nanopore; an opening extending through the cover unit and connected to the micro channel; and a second source/drain electrode disposed on the upper surface of the cover unit and adjacent to the opening; as well as a method for fabricating and using the device.

Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.

Abstract: A method includes thinning a first region of an active layer, for form a stepped surface in the active layer defined by the first region and a second region of the active layer, depositing an planarizing layer on the active layer that defines a planar surface disposed on the active layer, etching to define nanowires and pads in the first region of the active layer, suspending the nanowires over the BOX layer, etching fins in the second region of the active layer forming a first gate stack that surrounds portion of each of the nanowires, forming a second gate stack covering a portion of the fins, and growing an epitaxial material wherein the epitaxial material defines source and drain regions of the nanowire FET and source and drain regions of the finFET.

Abstract: A semiconductor structure which includes a substrate; a graphene layer on the substrate; a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension; a nitride layer on the graphene layer between the source electrode and drain electrode; and a gate electrode on the nitride layer, wherein the nitride layer is a gate dielectric for the gate electrode.

Abstract: An embodiment of the invention discloses a graphene device comprising a plurality of graphene channels and a gate, wherein one end of all the graphene channels is connected to one terminal, all the graphene channels are in contact with and electrically connected with the gate, and the angles between the graphene channels and the gate are mutually different. Due to a different incident wave angle for a different graphene channel, each of the graphene channels has a different tunneling probability, each of the graphene channels has a different conduction condition, and the graphene device may be used as a device such as a multiplexer or a demultiplexer, etc.

Abstract: The invention provides a manufacturing method of a graphene-on-insulator substrate which is mass productive, of high quality, and yet is directly usable for manufacture of semiconductor devices at a low manufacturing cost. According to the manufacturing method of a graphene substrate of the invention, a metal layer and a carbide layer are heated with the metal layer in contact with the carbide layer so that carbon in the carbide layer is dissolved into the metal layer, and then the metal layer and the carbide layer are cooled so that the carbon in the metal layer is segregated as graphene on the surface of the carbide layer.

Abstract: In a method for fabricating a graphene structure, there is formed on a fabrication substrate a pattern of a plurality of distinct graphene catalyst materials. In one graphene synthesis step, different numbers of graphene layers are formed on the catalyst materials in the formed pattern. In a method for fabricating a graphene transistor, on a fabrication substrate at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor channel and at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor source, and at a substrate region specified for synthesizing a graphene transistor drain. Then in one graphene synthesis step, at least one layer of graphene is formed at the substrate region for the graphene transistor channel, and at the regions for the transistor source and drain there are formed a plurality of layers of graphene.

Abstract: A method of manufacturing a graphene device may include forming a device portion including a graphene layer on the first substrate; attaching a second substrate on the device portion of the first substrate; and removing the first substrate. The removing of the first substrate may include etching a sacrificial layer between the first substrate and the graphene layer. After removing the first substrate, a third substrate may be attached on the device portion. After attaching the third substrate, the second substrate may be removed.

Abstract: Transistors and methods of manufacturing the same may include a gate on a substrate, a channel layer having a three-dimensional (3D) channel region covering at least a portion of a gate, a source electrode over a first region of the channel layer, and a drain electrode over a second region of the channel layer.

Abstract: Semiconductor nano-devices, such as nano-probe and nano-knife devices, which are constructed using graphene films that are suspended between open cavities of a semiconductor structure. The suspended graphene films serve as electro-mechanical membranes that can be made very thin, from one or few atoms in thickness, to greatly improve the sensitivity and reliability of semiconductor nano-probe and nano-knife devices.

Abstract: A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.

Abstract: A transistor includes at least three terminals comprising a gate electrode, a source electrode and a drain electrode, an insulating layer disposed on a substrate, and a semiconductor layer disposed on the substrate, wherein a current which flows between the source electrode and the drain electrode is controlled by application of a voltage to the gate electrode, where the semiconductor layer includes a graphene layer and at least one of a metal atomic layer and a metal ion layer, and where the metal atomic layer or the metal ion layer is interposed between the graphene layer and the insulating layer.

Abstract: Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circuits in either two-dimension or three-dimensional (stacked) layouts. Design equations based upon consideration of the electrical characteristics of the nanotubes are described which permit optimization of circuit design layout based upon constants that are indicative of the current carrying capacity of the nanotube fabrics of different FETs.

Abstract: Disclosed is a carbon nanotube field effect transistor which stably exhibits excellent electrical conduction properties. Also disclosed are a method for manufacturing the carbon nanotube field effect transistor, and a biosensor comprising the carbon nanotube field effect transistor. First of all, an silicon oxide film is formed on a contact region of a silicon substrate by an LOCOS method. Next, an insulating film, which is thinner than the silicon oxide film on the contact region, is formed on a channel region of the silicon substrate. Then, after arranging a carbon nanotube, which forms a channel, on the silicon substrate, the carbon nanotube is covered with a protective film. Finally, a source electrode and a drain electrode are formed, and the source electrode and the drain electrode are electrically connected to the carbon nanotube, respectively.

Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region.

Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

Abstract: A switching device includes a semiconductor layer, a graphene layer, a gate insulation layer, and a gate formed in a three-dimensional stacking structure between a first electrode and a second electrode formed on a substrate.

Abstract: A thin film transistor (“TFT”) includes a gate electrode, a gate insulating layer, a source electrode, a drain electrode and a semiconductor layer. The gate insulating layer is disposed on the gate electrode. The source electrode is disposed on the gate insulating layer. The drain electrode is disposed on the gate insulating layer. The drain electrode is spaced apart from the source electrode. The semiconductor layer is disposed on the gate insulating layer. The semiconductor layer makes contact with a side surface of the source electrode and a side surface of the drain electrode.

Abstract: A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.

Abstract: Provided are a resonance tunneling device and a method of manufacturing the resonance tunneling device. The resonance tunneling device includes a substrate, a plurality of electrodes disposed on the substrate, and a nanoparticle layer disposed between the electrodes, and doped with an impurity. The nanoparticle layer uses the impurity to exhibit resonance tunneling where a current peak occurs at a target bias voltage applied between the electrodes.

Abstract: An inverter device including a tunable diode device and a diode device that includes a control terminal connected to an input terminal of the inverter device, an anode terminal connected to a high-level voltage terminal, and a cathode terminal connected to an output terminal of the inverter device, wherein the diode device is configured to turn on or off according to a voltage applied to the control terminal.

Abstract: A semiconductor structure having a high Hall mobility is provided that includes a SiC substrate having a miscut angle of 0.1° or less and a graphene layer located on an upper surface of the SiC substrate. Also, provided are semiconductor devices that include a SiC substrate having a miscut angle of 0.1° or less and at least one graphene-containing semiconductor device located atop the SiC substrate. The at least one graphene-containing semiconductor device includes a graphene layer overlying and in contact with an upper surface of the SiC substrate.

Abstract: A graphene-on-oxide substrate according to the present invention includes: a substrate having a metal oxide layer formed on its surface; and, formed on the metal oxide layer, a graphene layer including at least one atomic layer of the graphene. The graphene layer is grown generally parallel to the surface of the metal oxide layer, and the inter-atomic-layer distance between the graphene atomic layer adjacent to the surface of the metal oxide layer and the surface atomic layer of the metal oxide layer is 0.34 nm or less. Preferably, the arithmetic mean surface roughness Ra of the metal oxide layer is 1 nm or less.

Abstract: There is provided an organic light-emitting diode luminaire. The luminaire includes a patterned first electrode, a second electrode, and a light-emitting layer therebetween. The light-emitting layer includes a first plurality of pixels having an emission color that is blue; a second plurality of pixels having an emission color that is green, the second plurality of pixels being laterally spaced from the first plurality of pixels; and a third plurality of pixels having an emission color that is red-orange, the third plurality of pixels being laterally spaced from the first and second pluralities of pixels. The additive mixing of all the emitted colors results in an overall emission of white light.

Abstract: A graphene device may include a channel layer including graphene, a first electrode and second electrode on a first region and second region of the channel layer, respectively, and a capping layer covering the channel layer and the first and second electrodes. A region of the channel layer between the first and second electrodes is exposed by an opening in the capping layer. A gate insulating layer may be on the capping layer to cover the region of the channel layer, and a gate may be on the gate insulating layer.

Abstract: An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region.

Abstract: Manufacturing a semiconductor structure including: forming a seed material on an insulator layer; forming a graphene field effect transistor (FET) on the seed material; and forming an air gap under the graphene FET by removing the seed material.

Abstract: The carbon nanotube-based electronic and photonic devices are disclosed. The devices are united by the same technology as well as similar elements for their fabrication. The devices consist of the vertically grown semiconductor nanotube having two Schottky barriers at the nanotube ends and one Schottky barrier at the middle of the nanotube. Depending on the Schottky barrier heights and bias arrangements, the disclosed devices can operate either as transistors, CNT MESFET and CNT Hot Electron Transistor, or as a CNT Photon Emitter.

Abstract: A hexagonal boron nitride sheet having: a two-dimensional planar structure with a sp2 B—N covalent bond, a Van der Waals bond between boron-nitrogen layers, a root mean square surface roughness of about 2 nanometers or less, and a length of about 1 millimeter or greater.

Abstract: A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene.

Abstract: A semiconductor device includes a carbon layer disposed on a substrate, a gate stack disposed on a portion of the carbon layer, a first cavity defined by the carbon layer and the substrate, a second cavity defined by the carbon layer and the substrate, a source region including a first conductive contact disposed in the first cavity, a drain region including a second conductive contact disposed in the second cavity.

Abstract: Some embodiments include switches that have a graphene structure connected to a pair of spaced-apart electrodes. The switches may further include first and second electrically conductive structures on opposing sides of the graphene structure from one another. The first structure may extend from one of the electrodes, and the second structure may extend from the other of the electrodes. Some embodiments include the above-described switches utilized as select devices in memory devices. Some embodiments include methods of selecting memory cells.

Abstract: Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.

Abstract: A method and an apparatus for doping a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility. The method includes selectively applying a dopant to a channel region of a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility of the field-effect transistor device.

Abstract: A method and an apparatus for doping a graphene and nanotube thin-film transistor field-effect transistor device to decrease contact resistance with a metal electrode. The method includes selectively applying a dopant to a metal contact region of a graphene and nanotube field-effect transistor device to decrease the contact resistance of the field-effect transistor device.

Abstract: Methods of making non-volatile field effect devices and arrays of same. Under one embodiment, a method of making a non-volatile field effect device includes providing a substrate with a field effect device formed therein. The field effect device includes a source, drain and gate with a field-modulatable channel between the source and drain. An electromechanically-deflectable, nanotube switching element is formed over the field effect device. Terminals and corresponding interconnect are provided to correspond to each of the source, drain and gate such that the nanotube switching element is electrically positioned between one of the source, drain and gate and its corresponding terminal, and such that the others of said source, drain and gate are directly connected to their corresponding terminals.

Abstract: A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene.

Abstract: An apparatus or method can include forming a graphene layer including a working surface, forming a polyvinyl alcohol (PVA) layer upon the working surface of the graphene layer, and forming a dielectric layer upon the PVA layer. In an example, the PVA layer can be activated and the dielectric layer can be deposited on an activated portion of the PVA layer. In an example, an electronic device can include such apparatus, such as included as a portion of graphene field-effect transistor (GFET), or one or more other devices.

Abstract: RF transistors are fabricated at complete wafer scale using a nanotube deposition technique capable of forming high-density, uniform semiconducting nanotube thin films at complete wafer scale, and electrical characterization reveals that such devices exhibit gigahertz operation, linearity, and large transconductance and current drive.

Abstract: A graphene transistor includes: a gate electrode on a substrate; a gate insulating layer on the gate electrode; a graphene channel on the gate insulating layer; a source electrode and a drain electrode on the graphene channel, the source and drain electrode being separate from each other; and a cover that covers upper surfaces of the source electrode and the drain electrode and forms an air gap above the graphene channel between the source electrode and the drain electrode.

Abstract: A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons.

Abstract: Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed.

Abstract: A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device.