Abstract: A graphene transistor includes: (1) a substrate; (2) a source electrode disposed on the substrate; (3) a drain electrode disposed on the substrate; (4) a graphene channel disposed on the substrate and extending between the source electrode and the drain electrode; and (5) a top gate disposed on the graphene channel and including a nanostructure.

Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.

Abstract: Embodiments of the present invention provide a thin film transistor (TFT) array substrate and a method for manufacturing the same and a display device. The TFT array substrate improves a structure of a TFT array substrate and has a small thickness, and process flow is simplified. The method for manufacturing a thin film transistor (TFT) array substrate comprises: obtaining a gate line and a gate electrode through a first patterning process on a glass substrate; forming a gate insulating layer on the gate line and the gate electrode; forming a graphene layer on the gate insulating layer, and obtaining a semiconductor active layer over the gate electrode by a second patterning process and a hydrogenation treatment; obtaining a data line, a source electrode, a drain electrode and a pixel electrode which are located on the same layer by a third patterning process; and forming a protection layer on the data line, the source electrode, the semiconductor active layer, the drain electrode and the pixel electrode.

Abstract: A separated carbon nanotube-based active matrix organic light-emitting diode (AMOLED) device including a substrate and transistors. Each transistor includes an individual back gate patterned on the substrate and a gate dielectric layer disposed over the substrate. An active channel including a network of separated semiconducting nanotubes is disposed over a functionalized surface of the gate dielectric layer. A source contact and a drain contact are formed on two ends of the active channel, with the network of separated nanotubes between the source contact and the drain contact. An organic light-emitting diode (OLED) display device is coupled to the drain of one of the transistors. A system includes a display control circuit having a substrate, with scan lines, data lines, and AMOLED devices formed on the substrate, with each AMOLED device coupled to one of the scan lines and one of the data lines.

Abstract: A field effect transistor (20) for chemical sensing, comprising an electrically conducting and chemically sensitive channel (2) extending between drain (5) and source (6) electrodes. A gate electrode (7) is separated from the channel (2) by a gap (10) through which a chemical to be sensed can reach the channel (2) which comprises a continuous monocrystalline graphene layer (2a) arranged on an electrically insulating graphene layer substrate (1). The graphene layer (2a) extends between and is electrically connected to the source electrode (5) and the drain electrode (6). The substrate supports the graphene layer, allowing it to stay 2-dimensional and continuous, and enables it to be provided on a well defined surface, and be produced and added to the transistor as a separate part. This is beneficial for reproducibility and reduces the risk of damage to the graphene layer during production and after. Low detection limits with low variability between individual transistors are also enabled.

Abstract: The method of manufacturing a graphene device includes forming an insulating material layer on a substrate, forming first and second metal pads on the insulating material layer spaced apart from each other, forming a graphene layer having a portion defined as an active area between the first and second metal pads on the insulating material layer, forming third and fourth metal pads on the graphene layer spaced apart from each other with the active area therebetween, the third and fourth metal pads extending above the first metal pad and the second metal pad, respectively, forming a first protection layer to cover all the first and second metal pads, the graphene layer, and the third and fourth metal pads, and etching an entire surface of the first protection layer until only a residual layer made of a material for forming the first protection layer remains on the active area.

Abstract: A graphite-based device comprising a substrate with a plurality of zones and one or more graphene stacks overlaying the zones is provided. A first zone comprises a plurality of surfaces. A first surface is adjacent to a second surface in the plurality of surfaces. The one or more graphene stacks comprise a first graphene stack in the first zone. The first graphene stack comprises a plurality of graphene layers, a first of which is formed on the first surface. The first graphene layer is either planar or non-planar. A second graphene layer in the plurality of graphene layers comprises a first portion formed on a top surface of the first graphene layer, a second portion formed on the second surface and a first intermediate portion connecting the first and second portions. The second graphene layer is non-planar. The first and second graphene layers have different characteristic dimensions and different bandgaps.

Abstract: The present disclosure provides an n-doping method of graphene, including supplying a reaction gas containing a carbon source and heat to a substrate and reacting to grow graphene on the substrate; and n-doping the graphene by a doping solution containing an n-type dopant or a vapor containing an n-type dopant, an n-doped graphene produced by the method, and a device including the n-doped graphene.

Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

Abstract: Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.

Abstract: A photodetector includes a waveguide on a substrate, and a photodetection portion connected to the waveguide. The photodetection portion includes a first semiconductor layer, graphene on the semiconductor layer, and a second semiconductor layer on the graphene. A first electrode and a second electrode separated from the first ridge portion and electrically connected to the graphene.

Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region.

Abstract: A thermoelectric structure comprises a thin thermoelectric film extending in a plane between parallel first and second shorting bars. A plurality of curved ballistic scattering guides are formed in a magnetic field region of the thin thermoelectric film subjected to a local, substantially uniform, nonzero magnetic field normal to the plane of the thin thermoelectric film.

Abstract: A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.

Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

Abstract: A hot hole transistor with a graphene base comprises on a substrate an emitter layer, a collector layer, and a base layer that comprises a graphene layer, wherein an emitter barrier layer is arranged between the base layer and the emitter layer, and a collector barrier layer is arranged between the base and the collector layers and adjacent to the graphene layer.

Abstract: An apparatus comprises at least one transistor. The at least one transistor comprises a substrate, a graphene layer formed on the substrate, and first and second source/drain regions spaced apart relative to one another on the substrate. The graphene layer comprises at least a first portion and a second portion, the first portion being in contact with the first source/drain region and the second portion being in contact with the second source/drain region. One or more cuts are formed in at least one of the first and second portions of the graphene layer. The apparatus allows for lowered contact resistance in graphene/metal contacts.

Abstract: Transistors, and methods of manufacturing the transistors, include graphene and a material converted from graphene. The transistor may include a channel layer including graphene and a gate insulating layer including a material converted from graphene. The material converted from the graphene may be fluorinated graphene. The channel layer may include a patterned graphene region. The patterned graphene region may be defined by a region converted from graphene. A gate of the transistor may include graphene.

Abstract: Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a first barrier layer coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier layer, the quantum well channel comprising a first material having a first lattice constant, and a source structure coupled to the quantum well channel, the source structure comprising a second material having a second lattice constant, wherein the second lattice constant is different than the first lattice constant to impart a strain on the quantum well channel. Other embodiments may be described and/or claimed.

Abstract: According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.

Abstract: In one aspect, a FET device is provided. The FET device includes a substrate; a semiconductor material on the substrate; at least one gate on the substrate surrounding a portion of the semiconductor material that serves as a channel region of the device, wherein portions of the semiconductor material extending out from the gate serve as source and drain regions of the device, and wherein the source and drain regions of the device are displaced from the substrate; a planarizing dielectric on the device covering the gate and the semiconductor material; and contacts which extend through the planarizing dielectric and surround the source and drain regions of the device.

Abstract: A semiconductor structure including nanotubes forming an electrical connection between electrodes is disclosed. The semiconductor structure may include an open volume defined by a lower surface of an electrically insulative material and sidewalls of at least a portion of each of a dielectric material and opposing electrodes. The nanotubes may extend between the opposing electrodes, forming a physical and electrical connection therebetween. The nanotubes may be encapsulated within the open volume in the semiconductor structure. A semiconductor structure including nanotubes forming an electrical connection between source and drain regions is also disclosed. The semiconductor structure may include at least one semiconducting carbon nanotube electrically connected to a source and a drain, a dielectric material disposed over the at least one semiconducting carbon nanotube and a gate dielectric overlying a portion of the dielectric material. Methods of forming the semiconductor structures are also disclosed.

Abstract: Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on semiconductor wafers, the CNT-based devices can be combined with the conventional semiconductor circuit elements, thus producing hybrid devices and circuits.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: A complimentary metal oxide semiconductor (CMOS) device includes a wafer having a buried oxide (BOX) layer having a first region with a first thickness and a second region with a second thickness, the first thickness is less than the second thickness, a nanowire field effect transistor (FET) arranged on the BOX layer in the first region, the nanowire FET, and a finFET arranged on the BOX layer in the second region.

Abstract: A composition of graphene-based nanomaterials and a method of preparing the composition are provided. A carbon-based precursor is dissolved in water to form a precursor suspension. The precursor suspension is placed onto a substrate, thereby forming a precursor assembly. The precursor assembly is annealed, thereby forming the graphene-based nanomaterials. The graphene-based nanomaterials are crystallographically ordered at least in part and configured to form a plurality of diffraction rings when probed by an incident electron beam. In one aspect, the graphene-based nanomaterials are semiconducting. In one aspect, a method of engineering an energy bandgap of graphene monoxide generally includes providing at least one atomic layer of graphene monoxide having a first energy bandgap, and applying a substantially planar strain is applied to the graphene monoxide, thereby tuning the first energy band gap to a second energy bandgap.

Abstract: A solid state Klystron structure is fabricated by forming a source contact and a drain contact to both ends of a conducting wire and by forming a bias gate and a signal gate on the conducting wire. The conducting wire may be at least one carbon nanotube or at least one semiconductor wire with long ballistic mean free paths. By applying a signal at a frequency that corresponds to an integer multiple of the transit time of the ballistic carriers between adjacent fingers of the signal gate, the carriers are bunched within the conducting wire, thus amplifying the current through the solid state Klystron at a frequency of the signal to the signal gate, thus achieving a power gain.

Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.

Abstract: An apparatus comprises at least one transistor. The at least one transistor comprises a substrate, a graphene layer formed on the substrate, and first and second source/drain regions spaced apart relative to one another on the substrate. The graphene layer comprises at least a first portion and a second portion, the first portion being in contact with the first source/drain region and the second portion being in contact with the second source/drain region. One or more cuts are formed in at least one of the first and second portions of the graphene layer. The apparatus allows for lowered contact resistance in graphene/metal contacts.

Abstract: A graphene-based electrically tunable nanoconstriction device and a non-transitory tangible computer readable medium encoded with a program for fabricating the device that includes a back-gate dielectric layer over a conductive substrate are described. The back-gate dielectric layer may be hexagonal boron nitride, mica, SiOx, SiNx, BNx, HfOx or AlOx. A graphene layer is an AB-stacked bi-layer graphene layer, an ABC-stacked tri-layer graphene layer or a stacked few-layer graphene layer. Contacts formed over a portion of the graphene layer include at least one source contact, at least one drain contact and at least one set of side-gate contacts. A graphene channel with graphene side gates is formed in the graphene layer between at least one source contact, at least one the drain contact and at least one set of side-gate contacts. A top-gate dielectric layer is formed over the graphene layer. A top-gate electrode is formed on the top-gate dielectric layer.

Abstract: A photodetector includes: a substrate; a first dielectric material positioned on the substrate; an optical waveguide positioned on the first dielectric material; a second dielectric material positioned on the optical waveguide; a graphene layer positioned on the second dielectric material; and a first electrode and a second electrode that are positioned on the graphene layer.

Abstract: Graphene- and/or carbon nanotube-based radiation-hard transistor devices and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating a radiation-hard transistor is provided. The method includes the following steps. A radiation-hard substrate is provided. A carbon-based material is formed on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor. Contacts are formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor. A gate dielectric is deposited over the portion of the carbon-based material that serves as the channel region of the transistor. A top-gate contact is formed on the gate dielectric.

Abstract: Provided are a photodetector (PD) using a graphene thin film and nanoparticles and a method of fabricating the same. The PD includes a graphene thin film having a sheet shape formed by means of a graphene deposition process using a vapor-phase carbon (C) source and a nanoparticle layer formed on the graphene thin film and patterned to define an electrode region of the graphene thin film, the nanoparticle layer being formed of nanoparticles without a matrix material. The PD has a planar structure using the graphene thin film as a channel and an electrode and using nanoparticles as a photovoltaic material (capable of forming electron-hole pairs due to photoelectron-motive force caused by ultraviolet (UV) light). Since the PD has a very simple structure, the PD may be fabricated at low cost with high productivity. Also, the PD includes the graphene thin film to reduce power consumption.

Abstract: A semiconductor device is provided comprising a bilayer graphene comprising a first and a second adjacent graphene layer, and a first electrically insulating layer contacting the first graphene layer, the first electrically insulating layer comprising an electrically insulating material, and a substance suitable for creating free charge carriers of a first type in the first graphene layer, the semiconductor device further comprising an electrically insulating region contacting the second graphene layer and suitable for creating free charge carriers of a second type, opposite to the first type, in the second graphene layer.

Abstract: Provided are a method of fabricating a graphene electronic device and the graphene electronic device fabricated thereby. The method may include forming a first electrode and a second electrode spaced apart from each other, on a substrate, forming supporting patterns on the first electrode and the second electrode, coating the supporting patterns with graphene-oxide-containing solution to form composite patterns, and separating the supporting patterns from the composite patterns.

Abstract: The transistor (100) comprises a nanowire (101) at least partially forming a channel of the transistor (100), a source contact (102) arranged at a first longitudinal end (103) of the nanowire (101), a drain contact (104) arranged at a second longitudinal end (105) of the nanowire (101), and a gate (106) arranged on the nanowire (101) between the source contact (102) and the drain contact (104). Furthermore, a portion of the gate (106) covers, with the interposition of a dielectric material (107), a corresponding portion of the source contact (102) and/or of the drain contact (104) arranged along the nanowire (101) between its two longitudinal ends (103, 105).

Abstract: This invention describes a novel electronic device consisting of one—or more—vertically stacked gate-all-around silicon nanowire field effect transistor (SNWFET) with two independent gate electrodes. One of the two gate electrodes, acting on the central section of the transistor channel, controls on/off behavior of the channel. The second gate, acting on the regions in proximity to the source and the drain of the transistor, defines the polarity of the devices, i.e. p or n type. The electric field of the second gate acts either at the interface of the nanowire-to-source/drain region or anywhere in close proximity to the depleted region of the SiNW body, modulating the bending of the Schottky barriers at the contacts, eventually screening one type of charge carrier to pass through the channel of the transistor. This is achieved by controlling the majority carriers passing through the transistor channel by regulating the Schottky barrier thicknesses at the source and drain contacts.

Abstract: A 3D M-CNT structure with at least one tri-state CNT NEM switch comprising at least an electrode as a source, an electrode as a gate and an electrode as a drain, a conductive carbon nanotube which is able to take three positions depending on a voltage application to said electrodes.

Abstract: Graphene transistor devices and methods of their fabrication are disclosed. One such graphene transistor device includes source and drain electrodes and a gate structure including a dielectric sidewall spacer that is disposed between the source and drain electrodes. The device further includes a graphene layer that is adjacent to at least one of the source and drain electrodes, where an interface between the source/drain electrode(s) and the graphene layer maintains a consistent degree of electrical conductivity throughout the interface.

Abstract: Part of a material layer is deposited on a deposition target surface of a second substrate by steps of providing a first substrate having a light absorption layer and a material layer in contact with the light absorption layer over one of surfaces; making a surface of the first substrate over which the material layer is formed and a deposition target surface of a second substrate face to each other; depositing part of the material layer on the deposition target surface of the second substrate in such a manner that irradiation with laser light of which repetition rate is greater than or equal to 10 MHz and pulse width is greater than or equal to 100 fs and less than or equal to 10 ns is performed from the other surface side of the first substrate to selectively heat part of the material layer overlapping with the light absorption layer.

Abstract: Provided are a resonance tunneling device and a method of manufacturing the resonance tunneling device. The resonance tunneling device includes a substrate, a plurality of electrodes disposed on the substrate, and a nanoparticle layer disposed between the electrodes, and doped with an impurity. The nanoparticle layer uses the impurity to exhibit resonance tunneling where a current peak occurs at a target bias voltage applied between the electrodes.

Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.

Abstract: An SiC crystal has Fe concentration not higher than 0.1 ppm and Al concentration not higher than 100 ppm. A method of manufacturing an SiC crystal includes the following steps. SiC powders for polishing are prepared as a first source material. A first SiC crystal is grown by sublimating the first source material through heating and precipitating an SiC crystal. A second source material is formed by crushing the first SiC crystal. A second SiC crystal is grown by sublimating the second source material through heating and precipitating an SiC crystal. Thus, an SiC crystal and a method of manufacturing an SiC crystal capable of achieving suppressed lowering in quality can be obtained.

Abstract: A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.

Abstract: Provided is a field effect transistor including a drain region, a source region, and a channel region. The field effect transistor may further include a gate electrode on or surrounding at least a portion of the channel region, and a gate dielectric layer between the channel region and the gate electrode. A portion of the channel region adjacent the source region has a sectional area smaller than that of another portion of the channel region adjacent the drain region.

Abstract: A photodetector using graphene includes: a gate electrode; a graphene channel layer which is opposite to and spaced apart from the gate electrode and does not have ?-binding; a first electrode which contacts a first side of the graphene channel layer; and a second electrode which contacts a side of the graphene channel layer, where the first and second sides are opposite to each other, and where the graphene channel layer includes a first graphene layer and a first nanoparticle disposed on the first graphene layer. The first graphene layer may include a single graphene layer, or the first graphene layer may include a plurality of single graphene layers, which is sequentially stacked and does not have ?-binding.

Abstract: Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.

Abstract: Methods for fabricating passivated silicon nanowires and an electronic arrangement thus obtained are described. Such arrangements may comprise a metal-oxide-semiconductor (MOS) structure such that the arrangements may be utilized for MOS field-effect transistors (MOSFETs) or opto-electronic switches.

Abstract: A graphene switching device includes a first electrode and an insulating layer in first and second regions of the semiconductor substrate, respectively, a plurality of metal particles on a surface of the semiconductor substrate between the first and second regions, a graphene layer on the plurality of metal particles and extending on the insulating layer, a second electrode on the graphene layer in the second region and configured to face the insulating layer, a gate insulating layer configured to cover the graphene layer, and a gate electrode on the gate insulating layer. The semiconductor substrate forms an energy barrier between the graphene layer and the first electrode.

Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.