Ballistic Transport Device (e.g., Hot Electron Transistor) Patents (Class 257/29)
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Patent number: 8785912Abstract: Graphene electronic devices may include a gate electrode on a substrate, a first gate insulating film covering the gate electrode, a plurality of graphene channel layers on the substrate, a second gate insulating film between the plurality of graphene channel layers, and a source electrode and a drain electrode connected to both edges of each of the plurality of graphene channel layers.Type: GrantFiled: September 6, 2011Date of Patent: July 22, 2014Assignees: Samsung Electronics Co., Ltd., SNU R&DB FoundationInventors: Hyun-jong Chung, Jae-hong Lee, Jae-ho Lee, Hyung-cheol Shin, Sun-ae Seo, Sung-hoon Lee, Jin-seong Heo, Hee-jun Yang
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Publication number: 20140197377Abstract: Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance.Type: ApplicationFiled: December 23, 2011Publication date: July 17, 2014Inventors: Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Annalisa Cappellani, Stephen M. Cea, Rafael Rios, Glenn A. Glass
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Patent number: 8779414Abstract: A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.Type: GrantFiled: June 21, 2013Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Paul Chang, Michael A. Guillorn, Philip S. Waggoner
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Publication number: 20140191197Abstract: An electronic structure comprising: (a) a first metal layer; (b) a second metal layer; (c) and at least one insulator layer located between the first metal layer and the second metal layer, wherein at least one of the metal layers comprises an amorphous multi-component metallic film. In certain embodiments, the construct is a metal-insulator-metal (MIM) diode.Type: ApplicationFiled: April 23, 2013Publication date: July 10, 2014Applicant: The State of Oregon Acting by and Through the State Board of Higher Education on Behalf of OregoInventor: The State of Oregon Acting by and Through the State Board of Higher Education on Behalf of Oregon
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Publication number: 20140191199Abstract: QCA assemblies, in which basic cells are formed on the basis of graphene in order to provide a coupling field distribution in the form of an electrostatic field, a magnetic field, and the like which allows a unique association between field distribution and logic state. Moreover, the corresponding energy structure may be selected so as to allow operation of the QCA assemblies at ambient temperature. Hence, the signal processing capabilities of QCA assemblies may be obtained at significantly reduced complexity compared to conventional quantum-based QCA assemblies, which typically operate at very low temperatures.Type: ApplicationFiled: December 31, 2013Publication date: July 10, 2014Applicant: STMicroelectronics S.r.l.Inventor: Domenico Porto
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Publication number: 20140191198Abstract: A graphene electronic device includes: a first conductive layer and a semiconductor layer on a first region of an intermediate layer; a second conductive layer on a second region of the intermediate layer; a graphene layer on the intermediate layer, the semiconductor layer, and the second conductive layer; and a first gate structure and a second gate structure on the graphene layer.Type: ApplicationFiled: August 26, 2013Publication date: July 10, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-sung KIM, Chang-seung LEE, Joo-ho LEE
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Patent number: 8772767Abstract: There is provided an organic light-emitting diode luminaire. The luminaire includes a patterned first electrode, a second electrode, and a light-emitting layer therebetween. The light-emitting layer includes a first plurality of pixels having an emission color that is blue; a second plurality of pixels having an emission color that is green, the second plurality of pixels being laterally spaced from the first plurality of pixels; and a third plurality of pixels having an emission color that is red-orange, the third plurality of pixels being laterally spaced from the first and second pluralities of pixels. The additive mixing of all the emitted colors results in an overall emission of white light.Type: GrantFiled: May 22, 2013Date of Patent: July 8, 2014Assignee: E I du Pont de Nemours and CompanyInventors: Kerwin D Dobbs, Norman Herron, Vsevolod Rostovtsev
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Publication number: 20140183453Abstract: A field effect transistor (FET) includes first and second channels stacked on a substrate, the first and second channels formed of a transition metal dichalcogenide, a source electrode and a drain electrode contacting both the first channel and the second channel, each of the source electrode and the drain electrode having one end between the first channel and the second channel, and a first gate electrode corresponding to at least one of the first channel and the second channel.Type: ApplicationFiled: July 16, 2013Publication date: July 3, 2014Inventors: Eok-su KIM, Sun-hee LEE
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Publication number: 20140176186Abstract: A graphene multiple-valued logic device and a fabrication method thereof are disclosed. The graphene multiple-valued logic device includes a substrate, a graphene channel layer disposed on the substrate, source and drain electrodes disposed at both ends of the graphene channel layer, respectively, an insulator film formed on the graphene channel layer; and at least two gate electrodes disposed on the insulator film with a predetermined gap defined therebetween. The device allows adjustment of conductivity and resistance of the graphene channel layer depending on a gate voltage, whereby electric current flowing in the device can be variously changed when applied to a multiple-valued logic system.Type: ApplicationFiled: December 20, 2013Publication date: June 26, 2014Applicant: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Byoung Hun LEE, Hyeon Jun HWANG, Yoon Ji KIM
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Publication number: 20140166982Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.Type: ApplicationFiled: December 18, 2012Publication date: June 19, 2014Applicant: International Business Machines CorporationInventors: Guy Cohen, Michael A. Guillorn, Alfred Grill, Leathen Shi
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Publication number: 20140166983Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.Type: ApplicationFiled: August 26, 2013Publication date: June 19, 2014Applicant: International Business Machines CorporationInventors: Guy Cohen, Michael A. Guillorn, Alfred Grill, Leathen Shi
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Patent number: 8754403Abstract: A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.Type: GrantFiled: August 2, 2012Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Paul Chang, Vijay Narayanan, Jeffrey W. Sleight
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Patent number: 8754397Abstract: The carbon nanotube-based electronic and photonic devices are disclosed. The devices are united by the same technology as well as similar elements for their fabrication. The devices consist of the vertically grown semiconductor nanotube having two Schottky barriers at the nanotube ends and one Schottky barrier at the middle of the nanotube. Depending on the Schottky barrier heights and bias arrangements, the disclosed devices can operate either as transistors, CNT MESFET and CNT Hot Electron Transistor, or as a CNT Photon Emitter.Type: GrantFiled: December 7, 2011Date of Patent: June 17, 2014Assignee: Nano-Electronic and Photonic Devices and Circuits, LLCInventor: Alexander Kastalsky
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Publication number: 20140158989Abstract: According to example embodiments, an electronic device includes: a semiconductor layer; a graphene directly contacting a desired (and/or alternatively predetermined) area of the semiconductor layer; and a metal layer on the graphene. The desired (and/or alternatively predetermined) area of the semiconductor layer include one of: a constant doping density, a doping density that is equal to or less than 1019 cm?3, and a depletion width of less than or equal to 3 nm.Type: ApplicationFiled: December 11, 2013Publication date: June 12, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung-eun BYUN, Seong-jun PARK, David SEO, Hyun-jae SONG, Jae-ho LEE, Hyun-jong CHUNG, Jin-seong HEO
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Publication number: 20140158988Abstract: Disclosed is a graphene transistor. The graphene transistor includes a source electrode, a drain electrode, a graphene layer, an insulating layer, a gate electrode and at least one doping layer. The graphene layer is disposed between the source electrode and the drain electrode. The gate electrode is separated from the graphene layer, the source electrode and the drain electrode by the insulating layer. The doping layer is disposed on the graphene layer or beneath the graphene layer for providing dopants for the graphene layer. The doping layer includes nonstoichiometric compounds. The graphene transistor of the present invention has a superior air stability and is not easily affected by environment.Type: ApplicationFiled: June 5, 2013Publication date: June 12, 2014Inventors: Chun-wei Chen, Po-hsun Ho
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Publication number: 20140158987Abstract: An apparatus, system, and/or method are described to enable optically transparent reconfigurable integrated electrical components, such as antennas and RF circuits to be integrated into an optically transparent host platform, such as glass. In one embodiment, an Ag NW film may be configured as a transparent conductor for antennas and/or as interconnects for passive circuit components, such as capacitors or resistors. Ag NW may also be used as transmission lines and/or interconnect overlays for devices. A graphene film may also be configured as active channel material for making active RF devices, such as amplifiers and switches.Type: ApplicationFiled: December 6, 2012Publication date: June 12, 2014Applicant: HRL LABORATORIES, LLCInventor: HRL Laboratories, LLC
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Patent number: 8748871Abstract: A three-dimensional integrated circuit includes a semiconductor device, an insulator formed on the semiconductor device, an interconnect formed in the insulator, and a graphene device formed on the insulator.Type: GrantFiled: January 18, 2012Date of Patent: June 10, 2014Assignee: International Business Machines CorporationInventors: Phaedon Avouris, Josephine B. Chang, Wilfried E. Haensch, Fei Liu, Zihong Liu, Yanqing Wu, Wenjuan Zhu
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Patent number: 8748950Abstract: A reconfigurable device includes a first insulating layer, a second insulating layer, and a nanoscale quasi one- or zero-dimensional electron gas region disposed at an interface between the first and second insulating layers. The device is reconfigurable by applying an external electrical field to the electron gas, thereby changing the conductivity of the electron gas region. A method for forming and erasing nanoscale-conducting structures employs tools, such as the tip of a conducting atomic force microscope (AFM), to form local electric fields. The method allows both isolated and continuous conducting features to be formed with a length well below 5 nm.Type: GrantFiled: November 17, 2010Date of Patent: June 10, 2014Assignee: University of Pittsburgh—Of the Commonwealth System of Higher EducationInventors: Jeremy Levy, Cheng Cen, Patrick Irvin
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Patent number: 8748957Abstract: A coherent spin field effect transistor is provided by depositing a ferromagnetic base like cobalt on a substrate. A magnetic oxide layer is formed on the cobalt by annealing at temperatures on the order of 1000° K to provide a few monolayer thick layer. Where the gate is cobalt, the resulting magnetic oxide is Co3O4(111). Other magnetic materials and oxides may be employed. A few ML field of graphene is deposited on the cobalt (III) oxide by molecular beam epitaxy, and a source and drain are deposited of base material. The resulting device is scalable, provides high on/off rates, is stable and operable at room temperature and easily fabricated with existing technology.Type: GrantFiled: January 5, 2012Date of Patent: June 10, 2014Assignee: Quantum Devices, LLCInventors: Jeffry Kelber, Peter Dowben
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Publication number: 20140151641Abstract: Three-dimensional integrated circuits and method for fabricating the same include forming one or more passive components in a passive-layer dielectric; depositing additional dielectric material on the passive-layer dielectric; forming a gate structure in the additional dielectric material; forming a gate dielectric layer on the gate structure and the additional dielectric material; forming a thin channel material on the gate dielectric; forming source and drain regions in electrical contact with the thin channel material to form a transistor; and passivating the transistor and providing electrical access to the source and drain regions.Type: ApplicationFiled: December 5, 2012Publication date: June 5, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shu-Jen Han, Alberto Valdes Garcia
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Publication number: 20140151640Abstract: A method of fabricating a semiconducting device is disclosed. A graphene sheet is formed on a substrate. At least one slot is formed in the graphene sheet, wherein the at least one slot has a width that allows an etchant to pass through the graphene sheet. An etchant is applied to the substrate through the at least one slot formed in the graphene sheet to etch the substrate.Type: ApplicationFiled: December 4, 2012Publication date: June 5, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Damon B. Farmer, Aaron D. Franklin, Joshua T. Smith
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Publication number: 20140151642Abstract: Three-dimensional integrated circuits include an active layer having one or more active components formed with carbon-based channel material; a passive layer monolithically formed with the active layer, having one or more sub-layers and each sub-layer having one or more passive components, where the passive components have monolithically formed vertical interconnects to components on other layers; and a surface layer monolithically formed with the passive layer, including one or more surface components connected to one or more of the passive components through monolithically formed vias.Type: ApplicationFiled: August 15, 2013Publication date: June 5, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: SHU-JEN HAN, ALBERTO VALDES GARCIA
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Publication number: 20140151643Abstract: A method of fabricating a semiconducting device is disclosed. A graphene sheet is formed on a substrate. At least one slot is formed in the graphene sheet, wherein the at least one slot has a width that allows an etchant to pass through the graphene sheet. An etchant is applied to the substrate through the at least one slot formed in the graphene sheet to etch the substrate.Type: ApplicationFiled: August 20, 2013Publication date: June 5, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Damon B. Farmer, Aaron D. Franklin, Joshua T. Smith
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Patent number: 8742400Abstract: A graphene switching device includes a first electrode and an insulating layer in first and second regions of the semiconductor substrate, respectively, a plurality of metal particles on a surface of the semiconductor substrate between the first and second regions, a graphene layer on the plurality of metal particles and extending on the insulating layer, a second electrode on the graphene layer in the second region and configured to face the insulating layer, a gate insulating layer configured to cover the graphene layer, and a gate electrode on the gate insulating layer. The semiconductor substrate forms an energy barrier between the graphene layer and the first electrode.Type: GrantFiled: April 12, 2013Date of Patent: June 3, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: David Seo, Sang-wook Kim, Seong-jun Park, Young-jun Yun, Yung-hee Yvette Lee, Chang-seung Lee
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FIELD EFFECT TRANSISTOR USING GRAPHENE, PHOSPHORUS-DOPED GRAPHENE, AND METHODS OF PRODUCING THE SAME
Publication number: 20140145148Abstract: A field effect transistor using a channel layer including a phosphorus-doped graphene and a method of fabricating the same are provided. Further, a phosphorus-doped graphene and a method of producing the same are provided. The field effect transistor includes: a source electrode and a drain electrode formed on a substrate; and a channel layer comprising a phosphorus-doped graphene, the channel layer electrically connected to the source electrode and the drain electrode.Type: ApplicationFiled: August 7, 2013Publication date: May 29, 2014Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITYInventor: Hyoyoung LEE -
Publication number: 20140138623Abstract: A carbon nanotube field-effect transistor is disclosed. The carbon nanotube field-effect transistor includes a first carbon nanotube film, a first gate layer coupled to the first carbon nanotube film and a second carbon nanotube film coupled to the first gate layer opposite the first gate layer. The first gate layer is configured to influence an electric field within the first carbon nanotube film as well as to influence an electric field of the second carbon nanotube film. At least one of a source contact and a drain contact are coupled to the first and second carbon nanotube film and are separated from the first gate layer by an underlap region.Type: ApplicationFiled: November 16, 2012Publication date: May 22, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Aaron D. Franklin, Joshua T. Smith, George S. Tulevski
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Publication number: 20140138625Abstract: A carbon nanotube field-effect transistor is disclosed. The carbon nanotube field-effect transistor includes a first carbon nanotube film, a first gate layer coupled to the first carbon nanotube film and a second carbon nanotube film coupled to the first gate layer opposite the first gate layer. The first gate layer is configured to influence an electric field within the first carbon nanotube film as well as to influence an electric field of the second carbon nanotube film. At least one of a source contact and a drain contact are coupled to the first and second carbon nanotube film and are separated from the first gate layer by an underlap region.Type: ApplicationFiled: August 20, 2013Publication date: May 22, 2014Applicant: International Business Machines CorporationInventors: Aaron D. Franklin, Joshua T. Smith, George S. Tulevski
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Publication number: 20140138626Abstract: A graphene field-effect transistor is disclosed. The graphene field-effect transistor includes a first graphene sheet, a first gate layer coupled to the first graphene sheet and a second graphene sheet coupled to the first gate layer opposite the first gate layer. The first gate layer is configured to influence an electric field within the first graphene sheet as well as to influence an electric field of the second graphene sheet.Type: ApplicationFiled: August 20, 2013Publication date: May 22, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Damon B. Farmer, Aaron D. Franklin, Sataoshi Oida, Joshua T. Smith
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Publication number: 20140138624Abstract: A graphene field-effect transistor is disclosed. The graphene field-effect transistor includes a first graphene sheet, a first gate layer coupled to the first graphene sheet and a second graphene sheet coupled to the first gate layer opposite the first gate layer. The first gate layer is configured to influence an electric field within the first graphene sheet as well as to influence an electric field of the second graphene sheet.Type: ApplicationFiled: November 21, 2012Publication date: May 22, 2014Applicant: International Business Machines CorporationInventors: Damon B. Farmer, Aaron D. Franklin, Sataoshi Oida, Joshua T. Smith
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Patent number: 8728880Abstract: A graphene electronic device includes a graphene channel layer on a substrate, a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer, a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, and a gate electrode on the gate oxide. The gate oxide has substantially the same shape as the graphene channel layer between the source electrode and the drain electrode.Type: GrantFiled: December 19, 2011Date of Patent: May 20, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-jong Chung, Jin-seong Heo, Hee-jun Yang, Sun-ae Seo, Sung-hoon Lee
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Publication number: 20140131662Abstract: Methods of forming a graphene-based device are provided. According to an embodiment, a graphene-based device can be formed by subjecting a substrate having a dielectric formed thereon to a chemical vapor deposition (CVD) process using a cracked hydrocarbon or a physical vapor deposition (PVD) process using a graphite source; and performing an annealing process. The annealing process can be performed to temperatures of 1000 K or more. The cracked hydrocarbon of the CVD process can be cracked ethylene. In accordance with one embodiment, the application of the cracked ethylene to a MgO(111) surface followed by an annealing under ultra high vacuum conditions can result in a structure on the MgO(111) surface of an ordered graphene film with an oxidized carbon-containing interfacial layer therebetween. In another embodiment, the PVD process can be used to form single or multiple monolayers of graphene.Type: ApplicationFiled: January 16, 2014Publication date: May 15, 2014Applicant: University of North TexasInventors: Jeffry A. Kelber, Sneha Sen Gaddam, Cameron L. BJELKEVIG
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Publication number: 20140125322Abstract: A nanogap device which may include a first insulation layer having a nanopore formed therein, a first channel layer which may be on the first insulation layer, a first source electrode and a first drain electrode which may be respectively in contact with both ends of the first channel layer, a second insulation layer which may cover the first channel layer, the first source electrode, and the first drain electrode, and a first nanogap electrode which may be on the second insulation layer and may be divided into two parts with a nanogap, which faces the nanopore, interposed between the two parts.Type: ApplicationFiled: April 3, 2013Publication date: May 8, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-seung LEE, Yong-sung KIM, Jeo-young SHIM, Joo-ho LEE
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Publication number: 20140124737Abstract: This disclosure provides systems, methods, and apparatus for flexible thin-film transistors. In one aspect, a device includes a polymer substrate, a gate electrode disposed on the polymer substrate, a dielectric layer disposed on the gate electrode and on exposed portions of the polymer substrate, a carbon nanotube network disposed on the dielectric layer, and a source electrode and a drain electrode disposed on the carbon nanotube network.Type: ApplicationFiled: October 28, 2013Publication date: May 8, 2014Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Kuniharu Takei, Toshitake Takahashi, Ali Javey
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Publication number: 20140124738Abstract: A small gap semiconductor system comprises: two parallel semiconductor sheets formed of atomically thin small gap semiconductor, one sheet containing electrons and the other containing holes; a dielectric insulating barrier arranged parallel to and separating the two semiconductor sheets; independent electrical contacts to each of the semiconductor sheets; two dielectric layers above and below the two semiconductor sheets respectively; and two conducting gates sandwiching the two semiconductor sheets and separated from the respective semiconductor sheets by the respective dielectric layers.Type: ApplicationFiled: November 7, 2013Publication date: May 8, 2014Inventors: Alexander R. HAMILTON, Andrea PERALI, David NEILSON
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Publication number: 20140125310Abstract: A nanogap device includes a first insulation layer having a nanopore formed therein, a first nanogap electrode which may be formed on the first insulation layer and may be divided into two parts with a nanogap interposed between the two parts, the nanogap facing the nanopore, a second insulation layer formed on the first nanogap electrode, a first graphene layer formed on the second insulation layer, a first semiconductor layer formed on the first graphene layer, a first drain electrode formed on the first semiconductor layer, and a first source electrode formed on the first graphene layer such as to be apart from the first semiconductor layer.Type: ApplicationFiled: April 3, 2013Publication date: May 8, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-seung LEE, Yong-sung KIM, Jeo-young SHIM, Joo-ho LEE
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Publication number: 20140117312Abstract: A method of creating a semiconductor device is disclosed. An end of a carbon nanotube is unzipped to provide a substantially flat surface. A contact of the semiconductor device is formed. The substantially flat surface of the carbon nanotube is coupled to the contact to create the semiconductor device. An energy gap in the unzipped end of the carbon nanotube may be less than an energy gap in a region of the carbon nanotube outside of the unzipped end region.Type: ApplicationFiled: November 27, 2012Publication date: May 1, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Damon B. Farmer, Aaron D. Franklin, Joshua T. Smith, George S. Tulevski
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Publication number: 20140117313Abstract: According to example embodiments, a graphene switching devices having a tunable barrier includes a semiconductor substrate that includes a first well doped with an impurity, a first electrode on a first area of the semiconductor substrate, an insulation layer on a second area of the semiconductor substrate, a graphene layer on the insulation layer and extending onto the semiconductor substrate toward the first electrode, a second electrode on the graphene layer and insulation layer, a gate insulation layer on the graphene layer, and a gate electrode on the gate insulation layer. The first area and the second area of the semiconductor substrate may be spaced apart from each other. The graphene layer is spaced apart from the first electrode. A lower portion of the graphene layer may contact the first well. The first well is configured to form an energy barrier between the graphene layer and the first electrode.Type: ApplicationFiled: August 12, 2013Publication date: May 1, 2014Applicants: SEOUL NATIONAL UNIVERSITY R & DB FOUNDATION, SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-ho LEE, Seong-jun PARK, Kyung-eun BYUN, David SEO, Hyun-jae SONG, Hyung-cheol SHIN, Jae-hong LEE, Hyun-jong CHUNG, Jin-seong HEO
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Publication number: 20140110671Abstract: A light source module includes at least one light emitting device and a thermoelectric device coupled to the at least one light emitting device. The thermoelectric devices includes a plurality of conductive layers, made of a resin material containing a thermoelectric conversion material, and a plurality of insulating layers laminated to the conductive layers. The thermoelectric device generates electricity by using heat from the light emitting device.Type: ApplicationFiled: June 25, 2013Publication date: April 24, 2014Inventor: Jung Hoon KIM
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Publication number: 20140110670Abstract: A hydrophobic organic layer may be formed on a surface of a graphene doped with a dopant to improve stability of the doped graphene with respect to moisture and temperature. Thus, the transparent electrode having the doped graphene containing the hydrophobic organic layer may be usefully applied in solar cells or display devices.Type: ApplicationFiled: March 20, 2013Publication date: April 24, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seon-mi YOON, Hyeon-jin SHIN, Jae-young CHOI, Won-mook CHOI, Soo-min KIM, Young-hee LEE
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Publication number: 20140103298Abstract: An environmental sensor comprises a graphene thin-film as an environmentally responsive material. Such graphene films exhibit negative temperature coefficients (NTC), resulting in rapid decreases in electrical resistance as temperature increases, as well as a much faster response time than any other NTC material reported in the literature. The graphene film is also mechanically stable under bending, and, therefore, can be adapted for use in a mechanical sensor or pressure sensor, because the electrical resistance of the graphene film changes upon deflection and/or changes in pressure. The electrical resistance of the graphene film also increases in response to increases in environmental humidity. The electrical resistance changes of the graphene film can also be used as a sensing mechanism for changes in chemical and biological parameters in the environment of the sensor.Type: ApplicationFiled: October 14, 2013Publication date: April 17, 2014Inventors: Woo Young Lee, Linh Tung Le, De Kong
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Publication number: 20140103297Abstract: Various methods and apparatuses involve the provision of graphitic material. As consistent with one or more aspects herein, an organic material template is used to restrict growth, in a width dimension, of graphitic material grown from the organic material template. Graphitic material is therein provided, having a set of characteristics including electrical behavior and shape, with a representative width defined by the width dimension, based on the organic material template.Type: ApplicationFiled: August 30, 2013Publication date: April 17, 2014Applicant: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Anatoliy N. Sokolov, Fung Ling Yap, Zhenan Bao, Nan Liu
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Publication number: 20140103299Abstract: Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on semiconductor wafers, the CNT-based devices can be combined with the conventional semiconductor circuit elements, thus producing hybrid devices and circuits.Type: ApplicationFiled: December 16, 2013Publication date: April 17, 2014Inventor: ALEXANDER KASTALSKY
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Publication number: 20140103296Abstract: Provided is a graphene nanoribbon sensor. The sensor includes a substrate, a graphene layer formed on the substrate in a first direction, and an upper dielectric layer on the graphene layer. Here, the graphene layer may have a plurality of electrode regions respectively separated in the first direction and a channel between the plurality of electrode regions.Type: ApplicationFiled: March 12, 2013Publication date: April 17, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Young-Jun YU, Choon Gi Choi
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Patent number: 8698129Abstract: An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region.Type: GrantFiled: December 20, 2012Date of Patent: April 15, 2014Assignees: IMEC, Katholieke Universiteit Leuven, KU Leuven R&DInventors: Geert Hellings, Geert Eneman
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Publication number: 20140097404Abstract: A memory device includes a graphene switching device having a source electrode, a drain electrode and a gate electrode. The graphene switching device includes a Schottky barrier formed between the drain electrode and a channel in a direction from the source electrode toward the drain electrode. The memory device need not include additional storage element.Type: ApplicationFiled: July 16, 2013Publication date: April 10, 2014Inventors: David SEO, Ho-jung KIM, Hyun-jong CHUNG, Seong-jun PARK, Kyung-eun BYUN, Hyun-jae SONG, Jin-seong HEO
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Patent number: 8692230Abstract: A high performance field-effect transistor includes a substrate, a nanomaterial thin film disposed on the substrate, a source electrode and a drain electrode formed on the nanomaterial thin film, and a channel area defined between the source electrode and the drain electrode. A unitary self-aligned gate electrode extends from the nanomaterial thin film in the channel area between the source electrode and the drain electrode, the gate electrode having an outer dielectric layer and including a foot region and a head region, the foot region in contact with a portion of the nanomaterial thin film in the channel area. A metal layer is disposed over the source electrode, the drain electrode, the head region of the gate electrode, and portions of the nanomaterial thin film proximate the source electrode and the drain electrode in the channel area.Type: GrantFiled: March 26, 2012Date of Patent: April 8, 2014Assignee: University of Southern CaliforniaInventors: Chongwu Zhou, Alexander Badmaev, Chuan Wang, Yuchi Che
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Publication number: 20140091280Abstract: Embodiments of the present invention provide an array substrate, a manufacturing method thereof and a display device. The manufacturing method of an array substrate, comprising: forming a gate electrode on a base substrate by a first patterning process, and then depositing a gate insulating layer on the base substrate on which the gate electrode is formed; forming source and drain electrodes on the base substrate obtained after the above step, by a second patterning process; forming an active layer formed of a graphene layer, and a protective layer disposed on the active layer, on the base substrate obtained after the above steps, by a third patterning process; and forming a planarizing layer on the base substrate, obtained after the above steps, by a fourth patterning process, in which the planarizing layer is provided with a through hole through which the source or drain electrode is exposed.Type: ApplicationFiled: September 30, 2013Publication date: April 3, 2014Applicant: BOE Technology Group Co., Ltd.Inventor: Tuo Sun
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Publication number: 20140084249Abstract: A nanowire field effect transistor device includes a first nanowire having a first distal end connected to a source region, a second distal end connected to a drain region, and a channel region therebetween, the source region and the drain region arranged on a substrate, and a second nanowire having a first distal end connected to the source region and a second distal end connected to the drain region, and a channel region therebetween, a longitudinal axis of the first nanowire and a longitudinal axis of the second nanowire defining a plane, the plane arranged substantially orthogonal to a plane defined by a planar surface of the substrate.Type: ApplicationFiled: October 23, 2012Publication date: March 27, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan S. Basker, Tenko Yamashita, Chun-chen Yeh
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Publication number: 20140084250Abstract: According to one embodiment, a semiconductor device includes a catalyst underlying layer formed on a substrate including semiconductor elements formed thereon and processed in a wiring pattern, a catalyst metal layer that is formed on the catalyst underlying layer and whose width is narrower than that of the catalyst underlying layer, and a graphene layer growing with a sidewall of the catalyst metal layer set as a growth origin and formed to surround the catalyst metal layer.Type: ApplicationFiled: March 18, 2013Publication date: March 27, 2014Inventors: Makoto WADA, Yuichi YAMAZAKI, Akihiro KAJITA, Atsunobu ISOBAYASHI, Tatsuro SAITO
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Patent number: 8679976Abstract: A method of manufacturing graphene includes forming a germanium layer on a surface of a substrate, and forming the graphene directly on the germanium layer by supplying carbon-containing gas into a chamber in which the substrate is disposed.Type: GrantFiled: December 22, 2010Date of Patent: March 25, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-kyung Lee, Byoung-Iyong Choi, Dong-mok Whang, Jae-hyun Lee