Abstract: Various embodiments are provided for graphite and/or graphene based semiconductor devices. In one embodiment, a semiconductor device includes a semiconductor layer and a semimetal stack. In another embodiment, the semiconductor device includes a semiconductor layer and a zero gap semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the semiconductor layer, which forms a Schottky barrier. In another embodiment, a semiconductor device includes first and second semiconductor layers and a semimetal stack. In another embodiment, a semiconductor device includes first and second semiconductor layers and a zero gap semiconductor layer. The first semiconductor layer includes a first semiconducting material and the second semi conductor layer includes a second semiconducting material formed on the first semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the second semiconductor layer, which forms a Schottky barrier.

Abstract: A set of buried electrodes are embedded in a dielectric material layer, and a graphene layer having a doping of a first conductivity type are formed thereupon. A first upper electrode is formed over a center portion of each buried electrode. Second upper electrodes are formed in regions that do not overlie the buried electrodes. A bias voltage is applied to the set of buried electrodes to form a charged region including minority charge carriers over each of the buried electrodes, and to form a p-n junction around each portion of the graphene layer overlying a buried electrode. Charge carriers generated at the p-n junctions are collected by the first upper electrodes and the second upper electrodes, and are subsequently measured by a current measurement device or a voltage measurement device.

Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.

Abstract: A technique is provided for base recognition in an integrated device is provided. A target molecule is driven into a nanopore of the integrated device. The integrated device includes a nanowire separated into a left nanowire part and a right nanowire part to form a nanogap in between, a source pad connected to the right nanowire part, a drain pad connected to the left nanowire part, and the nanopore. The source pad, the drain pad, the right nanowire part, the left nanowire part, and the nanogap together form a transistor. The nanogap is part of the nanopore. A transistor current is measured while a single base of the target molecule is in the nanogap of the nanopore, and the single base affects the transistor current. An identity of the single base is determined according to a change in the transistor current.

Abstract: Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.

Abstract: The invention refers to a nanodevice for generating electromagnetic radiation in the terahertz frequency range, the nanodevice comprising a substrate (3) made of a dielectric material, a first graphene layer (1) arranged on the substrate (3), having a first longitudinal end being electrically connected with a source contact (source 1) and having a second longitudinal end being connected with a drain contact (drain 1), an electrically conducting layer (2) having a periodic grating structure with grating stripes (6) extending substantially in transversal direction (y), and a dielectric layer (4) arranged between the first graphene layer (1) and the conducting layer (2).

Abstract: A field-effect transistor includes a semiconductor layer containing carbon nanomaterials; a first electrode and a second electrode formed in contact with the semiconductor layer; a third electrode for controlling current flowing between the first electrode and the second electrode; and an insulating layer formed between the semiconductor layer and the third electrode. The insulating layer contains an aromatic polyamide comprising a substituent containing 1 to 20 carbon atoms.

Abstract: Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed.

Abstract: An integrated graphene-based structure comprises an N-dimensional array of elements formed on a surface of a substrate. The N-dimensional array of elements includes a plurality of rows. Each respective row in the plurality of rows comprises a corresponding plurality of elements formed along a first dimension. Each element in the corresponding plurality of elements comprising at least one graphene stack and separated from an adjacent element along the first dimension by a first average spatial separation thereby resulting in a first periodicity in lateral spacing along the first dimension. Each respective row in the plurality of rows is separated from an adjacent row along a second dimension by a second average spatial separation, thereby resulting in a second periodicity in lateral spacing along the second dimension. The N-dimensional array exhibits a set of characteristic electromagnetic interference properties in response to electromagnetic radiation incident on the N-dimensional array.

Abstract: An integrated graphene-based structure comprises an N-dimensional array of elements formed on a surface of a substrate. The N-dimensional array of elements includes a plurality of rows. Each respective row in the plurality of rows comprises a corresponding plurality of elements formed along a first dimension. Each element in the corresponding plurality of elements comprising at least one graphene stack and separated from an adjacent element along the first dimension by a first average spatial separation thereby resulting in a first periodicity in lateral spacing along the first dimension. Each respective row in the plurality of rows is separated from an adjacent row along a second dimension by a second average spatial separation, thereby resulting in a second periodicity in lateral spacing along the second dimension. The N-dimensional array exhibits a set of characteristic electromagnetic interference properties in response to electromagnetic radiation incident on the N-dimensional array.

Abstract: An integrated graphene-based structure comprises an N-dimensional array of elements formed on a surface of a substrate. The N-dimensional array of elements includes a plurality of rows. Each respective row in the plurality of rows comprises a corresponding plurality of elements formed along a first dimension. Each element in the corresponding plurality of elements comprising at least one graphene stack and separated from an adjacent element along the first dimension by a first average spatial separation thereby resulting in a first periodicity in lateral spacing along the first dimension. Each respective row in the plurality of rows is separated from an adjacent row along a second dimension by a second average spatial separation, thereby resulting in a second periodicity in lateral spacing along the second dimension. The N-dimensional array exhibits a set of characteristic electromagnetic interference properties in response to electromagnetic radiation incident on the N-dimensional array.

Abstract: An integrated graphene-based structure comprises an N-dimensional array of elements formed on a surface of a substrate. The N-dimensional array of elements includes a plurality of rows. Each respective row in the plurality of rows comprises a corresponding plurality of elements formed along a first dimension. Each element in the corresponding plurality of elements comprising at least one graphene stack and separated from an adjacent element along the first dimension by a first average spatial separation thereby resulting in a first periodicity in lateral spacing along the first dimension. Each respective row in the plurality of rows is separated from an adjacent row along a second dimension by a second average spatial separation, thereby resulting in a second periodicity in lateral spacing along the second dimension. The N-dimensional array exhibits a set of characteristic electromagnetic interference properties in response to electromagnetic radiation incident on the N-dimensional array.

Abstract: A vertical semiconductor power field effect transistor device includes a SiC semiconductor body, at least part of the SiC semiconductor body constituting a drift zone, a first contact at a first side of the SiC semiconductor body, the first contact being a contact to one of a source and drain of the field effect transistor device, a second contact at a second side of the SiC semiconductor body, the first side being opposite the second side, the second contact being a contact to the other one of the source and drain, and a current path between the first contact and the second contact and which includes at least one graphene layer. A lateral channel region at the first side includes the at least one graphene layer.

Abstract: An integrated graphene-based structure comprises an N-dimensional array of elements formed on a surface of a substrate. The N-dimensional array of elements includes a plurality of rows. Each respective row in the plurality of rows comprises a corresponding plurality of elements formed along a first dimension. Each element in the corresponding plurality of elements comprising at least one graphene stack and separated from an adjacent element along the first dimension by a first average spatial separation thereby resulting in a first periodicity in lateral spacing along the first dimension. Each respective row in the plurality of rows is separated from an adjacent row along a second dimension by a second average spatial separation, thereby resulting in a second periodicity in lateral spacing along the second dimension. The N-dimensional array exhibits a set of characteristic electromagnetic interference properties in response to electromagnetic radiation incident on the N-dimensional array.

Abstract: We introduce a new technology for Manufactureable, High Power Density, High Volume Utilization Nuclear Batteries. Betavoltaic batteries are an excellent choice for battery applications which require long life, high power density, or the ability to operate in harsh environments. In order to optimize the performance of betavoltaic batteries for these applications or any other application, it is desirable to maximize the efficiency of beta particle energy conversion into power, while at the same time increasing the power density of an overall device. Various devices and methods to solve the current industry problems and limitations are presented here.

Abstract: In various embodiments, an electronic component is provided. The electronic component may include a dielectric structure; and a two-dimensional material containing structure over the dielectric structure. The dielectric structure is doped with dopants to change the electric characteristic of the two-dimensional material containing structure.

Abstract: A thin film transistor is provided. The thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, an insulating layer and a gate electrode. The insulating layer has a first surface and a second surface opposite to the first surface. The gate electrode is located on the first surface of the insulating layer. The source electrode, the drain electrode, and the semiconductor layer are located on the second surface of the insulating layer. The gate electrode, the source electrode, and the drain electrode include a first carbon nanotube layer. The semiconductor layer includes a second carbon nanotube layer. A first film resistor of the first carbon nanotube layer is smaller than or equal to 10 k? per square. A second film resistor of the second carbon nanotube layer is greater than or equal to 100 k? per square.

Abstract: A graphene laminate includes a first piezoelectric material layer having a negatively-charged surface and a positively-charged surface, a first graphene layer under the first piezoelectric material layer, the first graphene layer contacting the positively-charged surface of the first piezoelectric material layer, a second graphene layer underlying the first graphene layer, and a second piezoelectric material layer under the second graphene layer, the second piezoelectric material layer having a negatively-charged surface and a positively-charged surface, the negatively-charged surface contacting the second graphene layer.

Abstract: A semiconductor device comprising a graphene layer, a graphene oxide layer overlaying the graphene layer, and a high-k dielectric layer overlaying the graphene oxide layer is provided, as well as a method for producing the same. The method results in a graphene chemical functionalization that efficiently and uniformly seeds ALD growth, preserves the underlying graphene structure, and achieves desirable dielectric properties such as low leakage current and high capacitance.

Abstract: Methods of forming and resulting devices are described that include graphene devices on boron nitride. Selected methods of forming and resulting devices include graphene field effect transistors (GFETs) including boron nitride.

Abstract: A surface of a single crystalline semiconductor-carbon alloy layer having a surface normal along or close to a major crystallographic direction is provided by mechanical means such as cutting and/or polishing. Such a surface has naturally formed irregular surface features. Small semiconductor islands are deposited on the surface of single crystalline semiconductor-carbon alloy layer. Another single crystalline semiconductor-carbon alloy structure may be placed on the small semiconductor islands, and the assembly of the two semiconductor-carbon alloy layers with the semiconductor islands therebetween is annealed. During the initial phase of the anneal, surface diffusion of the semiconductor material proceeds to form vicinal surfaces while graphitization is suppressed because the space between the two semiconductor-carbon alloy layers maintains a high vapor pressure of the semiconductor material.

Abstract: The carbon nanotube-based electronic and photonic devices are disclosed. The devices are united by the same technology as well as similar elements for their fabrication. The devices consist of the vertically grown semiconductor nanotube having two Schottky barriers at the nanotube ends and one Schottky barrier at the middle of the nanotube. Depending on the Schottky barrier heights and bias arrangements, the disclosed devices can operate either as transistors, CNT MESFET and CNT Hot Electron Transistor, or as a CNT Photon Emitter.

Abstract: Semiconductor devices and methods of making thereof are disclosed. A field effect transistor (FET) is provided comprising a substrate, a first layer disposed above the substrate, the first layer being operable as a gate electrode, a second layer disposed above the first layer, the second layer comprising a dielectric material, a third layer disposed above the second layer, the third layer comprising a semiconductor, and a fourth layer comprising one or more conductive materials and operable as source and drain electrodes disposed above the third layer. In some embodiments, the dielectric material comprises a high-? dielectric. In some embodiments, the source and drain electrodes comprise one or more metals. The source and drain electrodes are each in ohmic contact with an area of the top surface of the third layer, and substantially all of the current through the transistor flows through the ohmic contacts.

Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures andor drain the structures, when the material used in the fabrication of the source structures andor the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures andor the drain structures may be prevented.

Abstract: A method of manufacturing a heterogeneous layered structure includes growing a hexagonal boron nitride sheet directly on a metal substrate in a chamber, increasing a temperature of the chamber to about 300° C. to about 1500° C., and forming a graphene sheet on the hexagonal boron nitride sheet by supplying a carbon source into the chamber while thermally treating the hexagonal boron nitride sheet at the increased temperature.

Abstract: The invention provides a manufacturing method of a graphene-on-insulator substrate which is mass productive, of high quality, and yet is directly usable for manufacture of semiconductor devices at a low manufacturing cost. According to the manufacturing method of a graphene substrate of the invention, a metal layer and a carbide layer are heated with the metal layer in contact with the carbide layer so that carbon in the carbide layer is dissolved into the metal layer, and then the metal layer and the carbide layer are cooled so that the carbon in the metal layer is segregated as graphene on the surface of the carbide layer.

Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy (SPE) process is performed to crystallise the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The fin has a cross-sectional thickness in at least one direction less than a minimum feature size. The transistor body is formed in the crystallised semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.

Abstract: An electronic structure comprising: (a) a first metal layer; (b) a second metal layer; (c) and at least one insulator layer located between the first metal layer and the second metal layer, wherein at least one of the metal layers comprises an amorphous multi-component metallic film. In certain embodiments, the construct is a metal-insulator-metal (MIM) diode.

Abstract: A method of manufacturing a graphene laminated structure includes plasma-treating a surface of a hexagonal boron nitride sheet using a fluorine-based gas plasma, depositing the hexagonal boron nitride sheet on a graphene sheet, and forming an insulating layer on a surface of the surface-treated hexagonal boron nitride sheet.

Abstract: A field effect transistor includes a substrate, a first graphene (Gr) layer on the substrate, a second graphene (Gr) layer on the substrate, a fluorographene (GrF) layer on the substrate and between the first and second graphene layers, a first ohmic contact on the first graphene layer, a second ohmic contact on the second graphene layer, a gate aligned over the fluorographene layer, and a gate dielectric between the gate and the fluorographene layer and between the gate and the first and second ohmic contacts.

Abstract: One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin, and an insulating material formed on the gate electrode.

Abstract: In accordance with an embodiment of the invention, there is provided a graphene ferroelectric device. The device comprises a graphene transistor channel and a ferroelectric gate of the graphene transistor channel, the ferroelectric gate comprising a linear polarization at a first applied gate voltage less than a threshold voltage, and a hysteretic polarization at a second applied gate voltage greater than the threshold voltage. The device may be configured to undergo optical switching of the graphene transistor channel between a high resistance state and a low resistance state in response to photoillumination of the device.

Abstract: A graphene device and an electronic apparatus including the same are provided. According to example embodiments, the graphene device includes a transistor including a source, a gate, and a drain, an active layer through which carriers move, and a graphene layer between the gate and the active layer. The graphene layer may be configured to function both as an electrode of the active layer and a channel layer of the transistor.

Abstract: According to one embodiment, a semiconductor device using multi-layered graphene wires includes a substrate having semiconductor elements formed therein, a first graphene wire formed above the substrate and including a multi-layered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate and including a multi-layered graphene layer into which the preset impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.

Abstract: Graphene transistor devices and methods of their fabrication are disclosed. In accordance with one method, a resist is deposited to pattern a gate structure area over a graphene channel on a substrate. In addition, gate dielectric material and gate electrode material are deposited over the graphene channel and the resist. Further, the resist and the electrode and dielectric materials that are disposed above the resist are lifted-off to form a gate structure including a gate electrode and a gate dielectric spacer and to expose portions of the graphene channel that are adjacent to the gate structure. Additionally, source and drain electrodes are formed over the exposed portions of the graphene channel.

Abstract: A graphene electronic device includes a graphene channel layer on a substrate, a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer, a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, and a gate electrode on the gate oxide. The gate oxide has substantially the same shape as the graphene channel layer between the source electrode and the drain electrode.

Abstract: An electronic device (1) includes a semiconductor substrate (3) having a front surface (7), a first electrode (8) and a second electrode (9) disposed on the front surface (7) of the substrate (3), wherein the first electrode (8) and the second electrode (9) each have at least one epitaxial graphene monolayer (10). The at least one epitaxial graphene monolayer (10) of the first electrode (8) forms an ohmic contact with the substrate (3) and the at least one epitaxial graphene monolayer (10) of the second electrode (9) forms a Schottky barrier with the substrate (3).

Abstract: A nanostructure, an optical device including the nanostructure, and methods of manufacturing the nanostructure and the optical device. A method of manufacturing a nanostructure may include forming a block copolymer template layer and a precursor pattern of metal coupled to the block copolymer template layer on a graphene layer, and forming a metal nanopattern on the graphene layer by removing the block copolymer template layer and reducing the precursor pattern.

Abstract: Graphene transistor devices and methods of their fabrication are disclosed. One such graphene transistor device includes source and drain electrodes and a gate structure including a dielectric sidewall spacer that is disposed between the source and drain electrodes. The device further includes a graphene layer that is adjacent to at least one of the source and drain electrodes, where an interface between the source/drain electrode(s) and the graphene layer maintains a consistent degree of electrical conductivity throughout the interface.

Abstract: An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.

Abstract: A method of fabricating a semiconducting device is disclosed. A graphene sheet is formed on a substrate. At least one slot is formed in the graphene sheet, wherein the at least one slot has a width that allows an etchant to pass through the graphene sheet. An etchant is applied to the substrate through the at least one slot formed in the graphene sheet to etch the substrate.

Abstract: Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.

Abstract: In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack.

Abstract: A semiconductor device and methods of making a semiconductor device using graphene are described. A monolithic three dimensional integrated circuit device includes a first layer having first active devices. The monolithic three dimensional integrated circuit device also includes a second layer having second active devices that each include a graphene portion. The second layer can be fabricated on the first layer to form a stack of active devices. A base substrate may support the stack of active devices.

Abstract: A thin-film transistor (TFT) substrate includes a semiconductor pattern, a conductive pattern, a first wiring pattern, an insulation pattern and a second wiring pattern. The semiconductor pattern is formed on a substrate. The conductive pattern is formed as a layer identical to the semiconductor pattern on the substrate. The first wiring pattern is formed on the semiconductor pattern. The first wiring pattern includes a source electrode and a drain electrode spaced apart from the source electrode. The insulation pattern is formed on the substrate having the first wiring pattern to cover the first wiring pattern. The second wiring pattern is formed on the insulation pattern. The second wiring pattern includes a gate electrode formed on the source and drain electrodes. Therefore, a TFT substrate is manufactured using two or three masks, so that manufacturing costs may be decreased.

Abstract: A method of fabricating a semiconducting device is disclosed. A graphene sheet is formed on a substrate. At least one slot is formed in the graphene sheet, wherein the at least one slot has a width that allows an etchant to pass through the graphene sheet. An etchant is applied to the substrate through the at least one slot formed in the graphene sheet to etch the substrate.

Abstract: A method of fabricating an electronic device includes the following steps. At least one first set and at least one second set of nanowires and pads are etched in an SOI layer of an SOI wafer. A first gate stack is formed that surrounds at least a portion of each of the first set of nanowires that serves as a channel region of a capacitor device. A second gate stack is formed that surrounds at least a portion of each of the second set of nanowires that serves as a channel region of a FET device. Source and drain regions of the FET device are selectively doped. A first silicide is formed on the source and drain regions of the capacitor device that extends at least to an edge of the first gate stack. A second silicide is formed on the source and drain regions of the FET device.

Abstract: Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.

Abstract: In one embodiment, a semiconductor device includes a first diffusion layer of a first conductive type and a second diffusion layer of a second conductive type which is a reverse conductive type of the first conductive type, the first conductive type first diffusion layer and the second conductive type diffusion layer being spaced apart and provided in a semiconductor layer, a pocket region of the second conductive type which is provided on a surface portion of the semiconductor layer adjacently to the first diffusion layer, and a first extension region of the first conductive type which is provided in the semiconductor layer to cover at least a portion of the pocket region. A second diffusion layer side end portion of the first extension region is positioned closer to a second diffusion layer side than a second diffusion layer side end portion of the pocket region.

Abstract: Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.