Abstract: Type-switching transistors, electronic devices including the same, and methods of operating thereof are provided. A type-switching transistor may include a plurality of gates corresponding to a channel layer. The plurality of gates may include a first gate for switching a type of the transistor and a second gate for controlling ON/OFF characteristics of the channel layer. The first and second gates may be disposed on one side of the channel layer so that the channel layer is not disposed between the first and second gates.

Abstract: A tunnel field-effect transistor (TFET) device includes first and second semiconductor contact regions separated by a semiconductor channel region; a channel gate overlying the channel region; and first and second doping gates overlying the first and second contact regions respectively; wherein application of a positive voltage level at the first doping gate and a negative voltage level at the second doping gate produces an n-type first contact region and a p-type second contact region, and reversing the voltage levels at the doping gates produces a p-type first contact region and an n-type second contact region.

Abstract: A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material.

Abstract: An apparatus, system, and/or method are described to enable optically transparent reconfigurable integrated electrical components, such as antennas and RF circuits to be integrated into an optically transparent host platform, such as glass. In one embodiment, an Ag NW film may be configured as a transparent conductor for antennas and/or as interconnects for passive circuit components, such as capacitors or resistors. Ag NW may also be used as transmission lines and/or interconnect overlays for devices. A graphene film may also be configured as active channel material for making active RF devices, such as amplifiers and switches.

Abstract: A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

Abstract: Thin-film transistors comprising buckled films comprising carbon nanotubes as the conductive channel are provided. Also provided are methods of fabricating the transistors. The transistors, which are highly stretchable and bendable, exhibit stable performance even when operated under high tensile strains.

Abstract: A carbon-based semiconductor structure includes a substrate and a gate stack. The gate stack includes a carbon-based gate electrode formed on the substrate. The gate stack also includes a gate dielectric formed on the carbon-based gate electrode. The gate stack further includes a carbon-based channel formed on the gate dielectric.

Abstract: A composition of matter comprising a plurality of nanowires on a substrate, said nanowires having been grown epitaxially on said substrate in the presence of a metal catalyst such that a catalyst deposit is located at the top of at least some of said nanowires, wherein said nanowires comprise at least one group III-V compound or at least one group II-VI compound or comprises at least one non carbon group IV element; and wherein a graphitic layer is in contact with at least some of the catalyst deposits on top of said nanowires.

Abstract: A semiconductor device of an embodiment includes a layered substance formed by laminating two-dimensional substances in two or more layers. The layered substance includes at least either one of a p-type region having a first intercalation substance between layers of the layered substance and an n-type region having a second intercalation substance between layers of the layered substance. The layered substance includes a conductive region that is adjacent to at least either one of the p-type region and the n-type region. The conductive region includes neither the first intercalation substance nor the second intercalation substance. A sealing member is formed on the conductive region, or on the conductive region and an end of the layered substance.

Abstract: A system includes a semiconductor substrate having at least two electrodes disposed thereon, a dielectric layer disposed over the electrodes, a graphene layer disposed over the dielectric layer and electrically isolated from the electrodes, and a differential amplifier operatively connected to the electrodes and electrically isolated from the graphene layer. A radiation-sensitive layer may be disposed over the graphene layer and a voltage source may be operatively connected to two of the electrodes. The system may be contained on an integrated circuit and may be used to sense radiation in liquid and gas form.

Abstract: Provided is a graphene nanoribbon sensor. The sensor includes a substrate, a graphene layer formed on the substrate in a first direction, and an upper dielectric layer on the graphene layer. Here, the graphene layer may have a plurality of electrode regions respectively separated in the first direction and a channel between the plurality of electrode regions.

Abstract: Provided are a nanowire field-effect transistor and a method for manufacturing the same. The nanowire field-effect transistor can enable a source region to be positioned, with respect to an asymmetrical nanowire channel, adjacent to a region in which the diameter of the nanowire channel is large, can enable a drain region to be positioned adjacent to a region in which the diameter of the nanowire channel is small, can enable an ON current to be increased in a state in which a threshold voltage level is kept the same, and can enable the current drivability of a gate electrode to be improved.

Abstract: Provided are a nanopore device with resolution improved by graphene nanopores, and a method of manufacturing the same. The nanopore device includes: a first insulating layer; a graphene layer disposed on the first insulating layer and having a nanopore formed at a center portion of the graphene layer; and first and second electrode layers disposed respectively at both sides of the nanopore on a top surface of the graphene layer, wherein a center region of the first insulating layer is removed such that the center portion of the graphene layer is exposed to the outside.

Abstract: An infrared detector includes a detecting element, a first electrode and a second electrode. The detecting element includes an absorbing part and a non-absorbing part. A first end is located in the absorbing part. A second end is located in the non-absorbing part. An angle between the absorbing part and the non-absorbing part is less than 90 degrees. A first electrode is electrically connected with the first end. A second electrode is electrically connected with the second end.

Abstract: The electrical properties of graphene and molybdenum sulfide semiconductor devices are improved by incorporating a fluoropolymer capping layer that is in contact with the graphene or molybdenum sulfide layer.

Abstract: Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material.

Abstract: A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

Abstract: Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.

Abstract: Various embodiments are provided for graphite and/or graphene based semiconductor devices. In one embodiment, a semiconductor device includes a semiconductor layer and a semimetal stack. In another embodiment, the semiconductor device includes a semiconductor layer and a zero gap semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the semiconductor layer, which forms a Schottky barrier. In another embodiment, a semiconductor device includes first and second semiconductor layers and a semimetal stack. In another embodiment, a semiconductor device includes first and second semiconductor layers and a zero gap semiconductor layer. The first semiconductor layer includes a first semiconducting material and the second semi conductor layer includes a second semiconducting material formed on the first semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the second semiconductor layer, which forms a Schottky barrier.

Abstract: Thin-film transistors comprising buckled films comprising carbon nanotubes as the conductive channel are provided. Also provided are methods of fabricating the transistors. The transistors, which are highly stretchable and bendable, exhibit stable performance even when operated under high tensile strains.

Abstract: A vertical III-V nanowire Field-Effect Transistor (FET). The FET includes multiple nanowires or nanopillars directly connected to a drain contact, where each of the nanopillars includes a channel of undoped III-V semiconductor material. The FET further includes a gate dielectric layer surrounding the plurality of nanopillars and a gate contact disposed on a gate metal which is connected to the gate dielectric layer. Additionally, the FET includes a substrate of doped III-V semiconductor material connected to the nanopillars via a layer of doped III-V semiconductor material. In addition, the FET contains a source contact directly connected to the bottom of the substrate. By having such a structure, electrostatic control and integration density is improved. Furthermore, by using III-V materials as opposed to silicon, the current drive capacity is improved. Additionally, the FET is fabricated using nanosphere lithography which is less costly than the conventional photo lithography process.

Abstract: A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween.

Abstract: Various methods and apparatuses involve the provision of graphitic material. As consistent with one or more aspects herein, an organic material template is used to restrict growth, in a width dimension, of graphitic material grown from the organic material template. Graphitic material is therein provided, having a set of characteristics including electrical behavior and shape, with a representative width defined by the width dimension, based on the organic material template.

Abstract: An example embodiment relates to a semiconductor device including a semiconductor element. The semiconductor element may include a plurality of unit layers spaced apart from each other in a vertical direction. Each unit layer may include a patterned graphene layer. The patterned graphene layer may be a layer patterned in a nanoscale. The patterned graphene layer may have a nanomesh or nanoribbon structure. The semiconductor device may be a transistor or a diode. An example embodiment relates to a method of making a semiconductor device including a semiconductor element.

Abstract: An apparatus, system, and/or method are described to enable optically transparent reconfigurable integrated electrical components, such as antennas and RF circuits to be integrated into an optically transparent host platform, such as glass. In one embodiment, an Ag NW film may be configured as a transparent conductor for antennas and/or as interconnects for passive circuit components, such as capacitors or resistors. Ag NW may also be used as transmission lines and/or interconnect overlays for devices. A graphene film may also be configured as active channel material for making active RF devices, such as amplifiers and switches.

Abstract: A light detecting array structure and a light detecting module are provided. The light detecting array structure includes a plurality of first electrodes, a plurality of second electrodes, a first carrier selective layer, a second carrier selective layer, and a light-absorbing active layer. The second electrodes are disposed on one side of the first electrodes. Between the first electrodes and the second electrodes, a first carrier selective layer, a light-absorbing active layer and a second carrier selective layer are disposed. The light detecting module includes the light detecting array structure and a control unit. The control unit is coupled to the first electrodes and second electrodes, selectively provides at least two cross voltages between each of the first electrodes and each of the second electrodes, and reads photocurrents flowing through the first electrodes and second electrodes.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.

Abstract: A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconductive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.

Abstract: The method of manufacturing a graphene device includes forming an insulating material layer on a substrate, forming first and second metal pads on the insulating material layer spaced apart from each other, forming a graphene layer having a portion defined as an active area between the first and second metal pads on the insulating material layer, forming third and fourth metal pads on the graphene layer spaced apart from each other with the active area therebetween, the third and fourth metal pads extending above the first metal pad and the second metal pad, respectively, forming a first protection layer to cover all the first and second metal pads, the graphene layer, and the third and fourth metal pads, and etching an entire surface of the first protection layer until only a residual layer made of a material for forming the first protection layer remains on the active area.

Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.

Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.

Abstract: Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.

Abstract: An apparatus having reduced phononic coupling between a graphene monolayer and a substrate is provided. The apparatus includes an aerogel substrate and a monolayer of graphene coupled to the aerogel substrate.

Abstract: The present disclosure relates to a graphene roll-to-roll transfer method, a graphene roll-to-roll transfer apparatus, a graphene roll manufactured by the graphene roll-to-roll transfer method, and uses thereof.

Abstract: A graphene-based device can be characterized as including a first electrode comprising graphene, a second electrode comprising graphene, and a potential barrier. The first electrode is physically separated from the second electrode by the potential barrier. The first electrode, second electrode and potential barrier are configured such that the graphene-based device can exhibit non-linear I-V characteristics under application of a voltage bias between the first electrode and the second electrode.

Abstract: Provided is a process for preparing graphene on a SiC substrate, based on metal film-assisted annealing, comprising the following steps: subjecting a SiC substrate to a standard cleaning process; placing the cleaned SiC substrate into a quartz tube and heating the quartz tube up to a temperature of 750 to 1150° C.; introducing CCl4vapor into the quartz tube to react with SiC for a period of 20 to 100 minutes so as to generate a double-layered carbon film, wherein the CCl4 vapor is carried by Ar gas; forming a metal film with a thickness of 350 to 600 nm on a Si substrate by electron beam deposition; placing the obtained double-layered carbon film sample onto the metal film; subsequently annealing them in an Ar atmosphere at a temperature of 900 to 1100° C. for 10-30 minutes so as to reconstitute the double-layered carbon film into double-layered graphene; and removing the metal film from the double-layered graphene, thereby obtaining double-layered graphene.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to connect part of the semiconductor elements to the graphene wires.

Abstract: A voltage-controlled switch comprises a first electrode, a second electrode, a switching junction situated between the first electrode and the second electrode, a conducting channel extending from adjacent to the origin through the switching junction and having a channel end situated near the second electrode, and a layer of dopants situated adjacent to an interface between the switching junction and the second electrode, wherein the dopants are capable of being activated to form switching centers.

Abstract: A thin film transistor includes a gate electrode configured to receive a control voltage, a source electrode insulated from the gate electrode, and configured to receive an input voltage, a drain electrode insulated from the gate electrode, and configured to receive an output voltage, at least two carbon nanotube patterns formed in a channel region between the source electrode and the drain electrode, wherein the carbon nanotube patterns are separated from each other, and at least one floating electrode connecting the two carbon nanotube patterns to each other.

Abstract: A self-aligned carbon nanostructure transistor is formed by a method that includes providing a material stack including a gate dielectric material having a dielectric constant of greater than silicon oxide and a sacrificial gate material. Next, a carbon nanostructure is formed on an exposed surface of the gate dielectric material. After forming the carbon nanostructure, metal semiconductor alloy portions are formed self-aligned to the material stack. The sacrificial gate material is then replaced with a conductive metal.

Abstract: A self-aligned carbon nanostructure transistor is formed by a method that includes providing a material stack including a gate dielectric material having a dielectric constant of greater than silicon oxide and a sacrificial gate material. Next, a carbon nanostructure is formed on an exposed surface of the gate dielectric material. After forming the carbon nanostructure, metal semiconductor alloy portions are formed self-aligned to the material stack. The sacrificial gate material is then replaced with a conductive metal.

Abstract: A transistor using a single crystal silicon nanowire and a method for fabricating the transistor is disclosed. The transistor using a single crystal silicon nanowire comprises a substrate and a single crystal silicon nanowire formed on the substrate. Here, the single crystal silicon nanowire comprises a source region and a drain region formed longitudinally with the single crystal silicon nanowire and separate from each other, and a channel region located between the source region and the drain region, wherein the perpendicular thickness of the channel region to the longitudinal direction is thinner than the thickness of the source region and the drain region.

Abstract: Disclosed herein is an isolable colloidal particle comprising a nanoparticle and an inorganic capping agent bound to the surface of the nanoparticle, a method for making the same in a biphasic solvent mixture, and the formation of structures and solids from the isolable colloidal particle. The process can yield photovoltaic cells, piezoelectric crystals, thermoelectric layers, optoelectronic layers, light emitting diodes, ferroelectric layers, thin film transistors, floating gate memory devices, phase change layers, and sensor devices.

Abstract: An integrated graphene-based structure comprises an N-dimensional array of elements formed on a surface of a substrate. The N-dimensional array of elements includes a plurality of rows. Each respective row in the plurality of rows comprises a corresponding plurality of elements formed along a first dimension. Each element in the corresponding plurality of elements comprising at least one graphene stack and separated from an adjacent element along the first dimension by a first average spatial separation thereby resulting in a first periodicity in lateral spacing along the first dimension. Each respective row in the plurality of rows is separated from an adjacent row along a second dimension by a second average spatial separation, thereby resulting in a second periodicity in lateral spacing along the second dimension. The N-dimensional array exhibits a set of characteristic electromagnetic interference properties in response to electromagnetic radiation incident on the N-dimensional array.

Abstract: The invention relates inter alia to an arrangement comprising a carrier (10), a layer and a material (20) enclosed between the carrier and the layer. According to the invention, it is provided that the layer is formed by a single two-dimensionally crosslinked layer (40) or by a plurality of two-dimensionally crosslinked layers which are indirectly or directly connected to one another.

Abstract: A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material.

Abstract: A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a first substrate. The spreading layer has at least one monolayer. A stressor layer is formed on the spreading layer. The stressor layer is configured to apply stress to a closest monolayer of the spreading layer. The closest monolayer is exfoliated by mechanically splitting the spreading layer wherein at least the closest monolayer remains on the stressor layer. The at least one monolayer is stamped against a second substrate to adhere remnants of the two-dimensional material on the at least one monolayer to the second substrate to provide a single monolayer on the stressor layer. The single monolayer is transferred to a third substrate.

Abstract: Various embodiments are provided for graphite and/or graphene based semiconductor devices. In one embodiment, a semiconductor device includes a semiconductor layer and a semimetal stack. In another embodiment, the semiconductor device includes a semiconductor layer and a zero gap semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the semiconductor layer, which forms a Schottky barrier. In another embodiment, a semiconductor device includes first and second semiconductor layers and a semimetal stack. In another embodiment, a semiconductor device includes first and second semiconductor layers and a zero gap semiconductor layer. The first semiconductor layer includes a first semiconducting material and the second semi conductor layer includes a second semiconducting material formed on the first semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the second semiconductor layer, which forms a Schottky barrier.

Abstract: A set of buried electrodes are embedded in a dielectric material layer, and a graphene layer having a doping of a first conductivity type are formed thereupon. A first upper electrode is formed over a center portion of each buried electrode. Second upper electrodes are formed in regions that do not overlie the buried electrodes. A bias voltage is applied to the set of buried electrodes to form a charged region including minority charge carriers over each of the buried electrodes, and to form a p-n junction around each portion of the graphene layer overlying a buried electrode. Charge carriers generated at the p-n junctions are collected by the first upper electrodes and the second upper electrodes, and are subsequently measured by a current measurement device or a voltage measurement device.