Abstract: A capacitor of a semiconductor memory device includes a substrate having a cell pad exposed through a buried contact hole of an interlayer insulating layer; a storage electrode having a bar pattern formed on the interlayer insulating layer for making an electrical connection with the cell pad through the buried contact hole and conductive spacers formed on the side walls of the bar pattern; a dielectric layer formed on the storage electrode; and a plate electrode formed on the storage electrodes with the dielectric layer being between the storage electrode (including the spacers) and the plate electrode.

Abstract: The invention relates to a memory cell that has a trench. A trench capacitor is configured in the trench. In addition, a vertical transistor is formed in the trench, above the trench capacitor. To connect the gate material of the vertical transistor to a word line, a dielectric layer (12) having an internal opening (13) is provided in the trench (3) above the gate material (23). The dielectric layer is in the form of a dielectric ring. The dielectric ring allows self-aligned connection of the word line to the gate material of the vertical transistor.

Abstract: A method of fabricating a self-aligned shallow trench isolation. A mask layer, two deep trenches and two internal electrodes of a capacitor are sequentially formed on a substrate. Two conductive layers are used to completely fill the two deep trenches. Then, two spacers are formed on exposed sides of the two conductive layers, and two doped regions are formed in a portion of the substrate located next to the two conductive layers. A patterned photoresist layer is formed to expose at least the spacers located in between the two deep trenches and the mask layer. The photoresist layer and the spacers are utilized as masks to etch away the exposed mask layer. The photoresist layer is utilized again as a mask to etch the exposed spacers and a portion of the exposed substrate. Sequentially, a remained portion of the photoresist layer and a portion of the conductive layers are removed. A remained mask layer is used as a mask to remove a portion of the exposed substrate, and a trench is thus formed.

Abstract: For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

Abstract: A semiconductor device has a diffusion layer formed on a silicon substrate, an interlayer insulator which covers a surface of the silicon substrate and whose surface is planarized, and a dielectric capacitor composed of a lower electrode connected to the diffusion layer via a buried conductive layer which is buried within a contact hole opened in the interlayer insulator and which is formed of a barrier metal layer composed of a contact plug, a low resistance layer and tantalum silicon nitride, and a dielectric film formed on the lower electrode, and an upper electrode. The lower electrode has a side-wall sloped configuration that its cross-sectional area monotonously increases from the buried conductive layer side toward the. upper dielectric film. Thus, a high-integration semiconductor device which allows the lower electrode to be micro-fabricated and enables lower-voltage operation and higher reliability can be obtained.

Abstract: A semiconductor processing method of forming dynamic random access memory circuitry includes, a) providing an electrically conductive capacitor cell plate substrate; b) providing an electrically insulative layer over the cell plate; c) providing a layer of semiconductive material on the insulative layer thereby defining a semiconductor-on-insulator (SOI) layer; d) patterning and etching the SOI layer to define active area region islands and isolation trenches between the islands; e) filling the isolation trenches with insulative material; f) providing capacitor openings through the SOI layer and insulative layer into the cell plate substrate; g) providing a capacitor dielectric layer over the cell plate substrate within the capacitor openings; h) providing respective capacitor storage nodes over the dielectric layer within the capacitor openings, the respective storage nodes being in ohmic connection with the SOI layer; i) after providing the storage nodes, filling any remaining portions of the capacitor cont

Abstract: An integrated circuit capacitor containing a thin film of dielectric metal oxide is formed above a silicon germanium substrate. A silicon nitride diffusion barrier layer is deposited on a silicon germanium substrate to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer is deposited on the diffusion barrier layer. A bottom electrode is formed on the stress reduction layer, then a liquid precursor is spun on the bottom electrode, dried at about 400° C., and annealed at between 600° C. and 850° C. to form a BST capacitor dielectric. A top electrode is deposited on the dielectric and annealed. The integrated circuit may also include a BiCMOS device, a HBT device or a MOSFET.

Abstract: There is provided a semiconductor device having a COB type DRAM, which comprises a first insulating film formed on a semiconductor substrate, first wiring trenches formed in a first insulating film in the first region, second wiring trenches formed in the first insulating film in the second region to have a substantially same depth as the first wiring trenches, first wirings buried in lower portions of the first wiring trenches, a second insulating film buried in upper portions of the first wiring trenches and formed of material different from the first insulating film, and second wirings formed of same conductive material as the first wirings in the second wiring trenches and formed thicker than the first wirings. Accordingly, the pattern precision of the bit lines and the wirings that have a different film thickness can be increased, and through holes that are formed between the bit lines in the self-alignment manner are formed shallow, and also resistances of the bit lines and the wirings are reduced.

Abstract: A semiconductor integrated circuit comprises a non-volatile semiconductor memory and a capacitor formed respectively on a first region and a second region of a substrate, wherein an insulation film of the non-volatile semiconductor memory has a thickness different from a capacitor insulation film of the capacitor.

Abstract: An integrated circuit includes a semiconductor substrate with semiconductor devices formed therein and thereon, a first wiring layer located over the substrate, a second wiring layer located on the first wiring layer, and a capacitor. The capacitor has metal-based charge-storage electrodes that extend through the second wiring layer and at least part of the first wiring layer. The wiring layers have interconnect wire embedded therein.

Abstract: A semiconductor device preventing contact between a capacitor insulator and a plug material even when an upper surface of the plug is exposed by misregistration in lithography and manufacturing method thereof are obtained. The semiconductor device includes an interlayer insulating film, a conducting plug, a capacitor lower electrode and a capacitor dielectric, and an end portion of the upper surface of the conducting plug has a portion overlapping a vicinity of an outer periphery of the upper surface of the capacitor lower electrode when viewed two-dimensionally. In the vicinity of the end portion of the upper surface of the conducting plug, a chemically inactive member is formed.

Abstract: An integrated circuit capacitor containing a thin film delectric metal oxide is formed above a silicon germanium substrate. A silicon nitride diffusion barrier layer is deposited on a silicon germanium substrate to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer is deposited on the diffusion barrier layer. A bottom electrode is formed on the stress reduction layer, then a liquid precursor is spun on the bottom electrode, dried at about 400° C., and annealed at between 600° C. and 850° C. to form a BST capacitor dielectric. A top electrode is deposited on the dielectric and annealed. The integrated circuit may also include a BiCMOS device, a HBT device or a MOSFET.

Abstract: Crystal lattice dislocations in material surrounding trench capacitors and other trench structures are avoided by alteration of stresses such as decreasing compressive stresses and/or development of persistent tensile forces within material deposited in the trench and thus at the material interface formed by the trench. Such alteration of stresses is achieved by volume reduction of a film deposited in the trench. The material is preferably a hydrogenated nitride of silicon, boron or silicon-carbon alloy which may be reduced in volume by partial or substantially complete dehydrogenation during subsequent heat treatment at temperatures where the film will exhibit substantial creep resistance. The amount of volume reduction can be closely controlled by control of concentration of hydrogen or other gas or volatile material in the film.

Abstract: There are provided a semiconductor device a semiconductor device capable of preventing the deterioration of characteristics of a capacitor of a stacked semiconductor memory device using a ferroelectric or high-dielectric film for the capacitor of the memory cell thereof, without preventing the scale down for high density integration, and a method for manufacturing the same.

Abstract: The present invention relates to a wide-bit memory output structure that comprises a chip having a plurality of output driver circuit cells. Each of the output driver circuit cells includes a power node, a ground node, and a signal node that are connected to respectively a first power line, a first ground line, and a first signal line. An extremity of each first power, ground, and signal line is exposed on the chip. The chip is provided with a thick metal structure thereupon, which comprises a wide power bus and a wide ground bus that are connected to respectively a plurality of second power lines and a plurality of second ground lines. Finally, the first and second power lines, first and second ground lines, and first and second signal lines are respectively connected to one another. An extremity of respectively the wide power bus, the ground bus and the second signal lines is equally exposed externally from the thick metal structure.

Abstract: A method of forming a side wall contact on a side wall of a contact hole in an inter-layer insulator structure by an etch-back process The method includes forming a first insulation film on a top insulation layer of the inter-layer insulator structure, forming a second insulation film to extend on the side wall and a bottom of the contact hole as well as on a surface of the first insulation film. The first insulation film has a higher etching selectivity than the top insulation layer of the inter-layer insulator structure and the second insulation film has a lower etching selectivity than the top insulation layer of the inter-layer insulator structure. The second insulation film is lower in etching selectivity than the first insulation film.

Abstract: A ferroelectric memory is composed of a wiring layer, a bottom electrode coupled to the wiring layer, a ferroelectric film formed on the bottom electrode, a top electrode formed on the ferroelectric film, and a metal silicide layer coupled to the top electrode and located above the ferroelectric film. The wiring layer includes substantially no silicon.

Abstract: A semiconductor memory device that is capable of reducing the probability of a bridge being generated between storage node electrodes, and a mask pattern for defining the storage node electrodes, are provided. The semiconductor memory device includes a plurality of storage node electrodes that are vertically and horizontally arranged a predetermined distance apart in columns and rows, respectively. Among the plurality of storage node electrodes, storage node electrodes belonging to even-numbered columns are shifted up or down a predetermined distance. The shifted storage node electrodes are shifted in a gap between vertically adjacent storage node electrodes belonging to a same column.

Abstract: A cylindrical capacitor structure and a corresponding method of manufacture. To form the cylindrical capacitor, a conductive section, an etching stop layer, a first insulation layer, a bit line structure and a second insulation layer are sequentially formed over a substrate. A portion of the second insulation layer and the first insulation layer is removed until the etching stop layer is exposed. Ultimately, a plurality of gap-connected cylindrical openings and node contact openings between spacers are sequentially formed. Conductive spacers are formed on the sidewalls of the cylindrical openings and the node contact openings. In the meantime, material similar to the conductive spacers fills the small gaps, thereby forming an upper electrode for the capacitor. A dielectric layer is formed over the capacitor electrode. The exposed etching stop layer at the bottom of the contact opening is removed to expose the conductive section above the substrate.

Abstract: A stacked capacitor that has a large capacitance per unit area (Co), very low voltage coefficient (Kv), and an acceptable parasitic capacitance factor (Kp) is described that uses only one polysilicon layer. The stacked capacitor is formed at the surface of a semiconductor substrate of a first conductivity type. The stacked capacitor has a bottom plate that is formed by a lightly doped well diffused into the surface of the semiconductor substrate. The bottom plate also has a first plurality of interconnected conductive layers of a first conductive material disposed above and aligned with the well, whereby a first conductive layer of the first plurality of conductive layers is connected to the well by multiple contacts distributed over an area of the well.

Abstract: A method for fabricating a MIM capacitor of a MDL logic or analog circuit of a semiconductor device. A conductivity layer is formed on a semiconductor substrate having a first inter-level insulating layer. A capping metal layer having an etching rate higher than an oxide layer is formed on the conductivity layer. A lower electrode comprising a “conductivity layer/capping metal layer” deposition is formed by selectively etching the capping metal layer and the conductivity layer in order to expose a predetermined part of the surface of the first inter-level insulating layer. A second inter-level insulating layer is formed on the first inter-level insulating layer covering the lower electrode. A via hole is formed by selectively etching both the second inter-level insulating layer and the lower electrode thereby to expose a portion of the lower electrode so that a tapered capping metal layer remains along the lower edges of the via hole.

Abstract: A method for controlling isolation layer thickness in deep trenches for semiconductor memories in accordance with the present invention includes the steps of providing a deep trench having a storage node formed therein, the storage node having a buried strap, depositing an isolation layer on the buried strap for providing electrical isolation for the storage node, forming a masking layer on the isolation layer to mask a portion of the isolation layer in contact with the buried strap and removing the isolation layer except the portion masked by the mask layer such that control of a thickness of the isolation layer is improved. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.

Abstract: A conductive composition of tantalum nitride is disclosed for use as a conductive element in integrated circuits. The layer is shown employed in a memory cell, and in particular in a cell incorporating a high dielectric constant material such as Ta2O5. The tantalum nitride can serve as a barrier layer protecting an underlying contact plug, or can serve as the top or bottom electrode of the memory cell capacitor. The titanium nitride has a nitrogen content of between about 7% and 40%, thereby balancing susceptibility to oxidation with conductivity. In an illustrative embodiment, the titanium nitride layer is a bilayer formed of a thick portion having a low nitrogen concentration, and thin portion with a higher nitrogen concentration. The thick portion thus carries the bulk of the current with low resistivity, while the thinner portion is highly resistant to oxidation.

Abstract: An electrical contact includes a non-conductive spacer surrounding conductive plug material along the full height of the contact. The spacer inhibits oxide and other diffusion through the contact. In the illustrated embodiment, the contact includes metals or metal oxides which are resistant to oxidation, and additional conductive barrier layers. The contact is particularly useful in integrated circuits which include high dielectric constant materials.

Abstract: A semiconductor memory cell comprising (1) a first transistor of a first conductivity type for read-out having source/drain regions composed of a surface region of a third region and a second region and a channel forming region composed of a surface region of a first region, (2) a second transistor of a second conductivity type for write-in having source/drain regions composed of the first region and a fourth region and a channel forming region composed of a surface region of the third region, and (3) a junction-field-effect transistor of a first conductivity type for current control having gate regions composed of the fourth region and a portion of the first region facing the fourth region, a channel region composed of the third region sandwiched by the fourth region and the first region and source/drain regions composed of the third region.

Abstract: The present invention provides a semiconductor memory device and a fabrication method capable of preventing the contact between a dielectric layer of a capacitor and a diffusion barrier. The plug comprises a diffusion barrier layer and a seed layer for forming a lower electrode of a capacitor. Accordingly, it is possible to prevent the dielectric layer being contacted with the diffusion barrier, whereby the leakage current may be reduced, and the capacitance of the capacitor may be increased.

Abstract: A non-volatile memory (NVM) system includes a NVM cell having: a semiconductor region having a first conductivity type; a gate dielectric layer located over the semiconductor region; a gate electrode located over the gate dielectric layer; a source region and a drain region of a second conductivity type, opposite the first conductivity type, located in the semiconductor region and aligned with the gate electrode; a crown electrode having a base that contacts the gate electrode and walls that extend vertically from the base region, away from the gate electrode; a dielectric layer located over the crown electrode, wherein the dielectric layer extends over at least interior surfaces of the walls; and a plate electrode located over the dielectric layer, wherein the plate electrode extends over at least interior surfaces of the walls.

Abstract: Methods of forming a channel region between isolation regions of an integrated circuit substrate are disclosed. In particular, a mask can be formed on an isolation region that extends onto a portion of the substrate adjacent to the isolation region to provide a shielded portion of the substrate adjacent to the isolation region and an exposed portion of the substrate spaced apart from the isolation region having the shielded portion therebetween. A channel region can be formed in the exposed portion of the substrate. Related integrated circuits are also discussed.

Abstract: In a method of fabricating a COB DRAM cell, a polysilicon plug is formed on the source and drain in self-alignment with the gate electrode. A bit line contact and a storage electrode contact are formed on the polysilicon plug thereby to reduce the aspect ratio of both the bit line contact and the storage electrode contact. With the polysilicon plug formed in self-alignment with the gate electrode, short-circuiting of contacts of adjacent element regions and short-circuiting of the plugs of the source and drain will not occur, leading to high protection against misregistration. Moreover, an independent lithography process is not required for forming the polysilicon plug, and, therefore, the number of fabrication steps is reduced.

Abstract: A liquid precursor for forming a layered superlattice material is applied to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid ramping anneal (“RRA”) technique with a ramping rate of 50° C./second at a hold temperature of 650° C. for a holding time of 30 minutes.

Abstract: A semiconductor memory device is provided, which prevents the characteristic of storage capacitors from degrading without chip-area increase of memory cells. Each of storage capacitors has a dielectric sandwiched by lower and upper electrodes. The lower electrodes are formed by a patterned, common electrically-conductive layer. The dielectrics are formed by a patterned, common ferroelectric layer formed on the common electrically-conductive layer which is entirely overlapped with the common electrically-conductive layer. The upper electrodes are regularly arranged on the common ferroelectric layer and are located outside the rows and columns of a matrix array where the windows of the common electrically-conductive layer and common ferroelectric layer are aligned. Wiring lines are formed over the upper electrodes through an interlayer insulating layer covering the storage capacitors, thereby electrically connecting the upper electrodes and select transistors.

Abstract: A capacitive element structure in a semiconductor device having an interconnection structure. The capacitive element structure includes a capacitive element having a capacitive dielectric film made of an oxide compound. The capacitive element structure is above at least a first level interconnection of the interconnection structure.

Abstract: A method for manufacturing a semiconductor memory device in which a bit line and a storage electrode of a capacitor are connected to an active area of a semiconductor substrate, respectively, via a contact pad formed in a self-aligning manner. The method includes the steps of forming gate electrodes on the semiconductor substrate, the gate electrodes being covered with a nitride spacer. Then, a thermal oxide layer is formed on the exposed surface of the semiconductor substrate between the gate electrodes. Then, an etch stop layer is formed on the entire surface of the resultant structure having the thermal oxide layer to an appropriate thickness such that the space between the gate electrodes is not buried. Then, a first interlayer dielectric (ILD) film covering the space between the gate electrodes and the top of the gate electrodes is formed, and the first ILD film is then patterned to form a landing pad hole which exposes the spacer and the etch stop layer.

Abstract: Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of intrinsically conductive recrystallization barrier layers. The intrinsically conductive layers are preferably used adjacent to conductive strap features in trench capacitors to act as recrystallization barriers.

Abstract: An upper electrode of an FRAM capacitor is connected to a diffusion layer on the surface of a semiconductor substrate via a contact hole, second interconnecting layer, contact hole, first interconnecting layer, and contact hole. The first interconnecting layer is formed at substantially the same level as the FRAM capacitor. This decreases the depth of the contact hole connecting the first interconnecting layer to the surface of the semiconductor substrate and thereby decreases the aspect ratio of this contact hole. This facilitates processing and filling this contact hole and allows micropatterning.

Abstract: A photoresist composition is disclosed having both negative tone and positive tone responses, giving rise to spaces being formed in the areas of diffraction which are exposed to intermediate amounts of radiation energy. This resist material may be used to print doughnut shapes or may be subjected to a second masking step, to print lines. Additionally, larger and smaller features may be obtained using a gray-scale filter in the reticle, to create larger areas of intermediate exposure areas.

Abstract: A semiconductor device has a diffusion layer formed on a silicon substrate, an interlayer insulator which covers a surface of the silicon substrate and whose surface is planarized, and a dielectric capacitor composed of a lower electrode connected to the diffusion layer via a buried conductive layer which is buried within a contact hole opened in the interlayer insulator and which is formed of a barrier metal layer composed of a contact plug, a low resistance layer and tantalum silicon nitride, and a dielectric film formed on the lower electrode, and an upper electrode. The lower electrode has a side-wall sloped configuration that its cross-sectional area monotonously increases from the buried conductive layer side toward the upper dielectric film. Thus, a high-integration semiconductor device which allows the lower electrode to be micro-fabricated and enables lower-voltage operation and higher reliability can be obtained.

Abstract: A new method of fabricating a capacitor and PMOS devices in a mixed-mode product production in which a composite polysilicon top plate electrode is provided which prevents out-diffusion of dopant from the capacitor plate so that there is no auto-doping of the PMOS channel region is described. A layer of gate silicon oxide is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate silicon oxide layer. The first polysilicon layer and gate oxide layer are etched away where they are not covered by a mask to provide a PMOS gate electrode in a first region of the wafer and a bottom plate electrode for the capacitor in a second region of the wafer. A capacitor dielectric layer is deposited over the surface of the wafer. A composite polysilicon layer is deposited overlying the capacitor dielectric layer wherein the composite polysilcon layer comprises a lower doped polysilcon layer and an upper undoped polysilicon layer.

Abstract: Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of active area formed within the semiconductive substrate which are continuous between adjacent memory cells, said adjacent memory cells being isolated from one another relative to the continuous active area formed therebetween by a conductive line formed over said continuous active area between said adjacent memory cells. At least some adjacent lines of continuous active area within the array are isolated from one another by LOCOS field oxide formed therebetween. The respective area consumed by individual of said adjacent memory cells is ideally equal to less than 8F2, where “F” is no greater than 0.

Abstract: Process for producing an integrated semiconductor memory configuration, in particular one suited to the use of ferroelectric materials as storage dielectrics, in which a conductive connection between one electrode of a storage capacitor and a selection transistor is not produced until after the storage dielectric has been deposited; and a semiconductor memory configuration produced using the production process.

Abstract: In a DRAM-logic embedded integrated circuit in which a DRAM including trench capacitors of the deep trench structure and a logic circuit are mixedly formed in a semiconductor substrate, a plurality of capacitors of the deep trench structure are provided in the logic circuit portion. The plurality of capacitors are connected in parallel by wiring portions, whereby a plurality of capacitor blocks are formed. Between the respective capacitor blocks, there are provided fuse elements which selectively connect the respective wiring portions to each other or selectively separate them from each other to thereby vary the capacitance value of the capacitance blocks. These fuse elements are selectively cut off depending on the capacitance value of the capacitors required in view of the circuit design.

Abstract: A semiconductor device having improved reliability is provided. The semiconductor device has a pixel portion. The pixel portion has a TFT and a storage capacitor. The TFT and the storage capacitor has a semiconductor layer which includes first and second regions formed continuously. The TFT has the first region of the semiconductor layer including a channel forming region, a source region and a drain region located outside the channel forming region, a gate insulating film adjacent to the first region of the semiconductor layer, and a gate electrode formed on the gate insulating film. The storage capacitor has the second region of the semiconductor layer, an insulating film formed adjacent to the second region of the semiconductor layer, and a capacitor wiring formed on the insulating film. The second region of the semiconductor layer contains an impurity element for imparting n-type or p-type conductivity.

Abstract: A capacitor of a semiconductor device includes a first insulating layer having a contact hole therethrough and a contact plug that is in the contact hole and electrically connected to a semiconductor substrate. Also, a diffusion barrier layer is on the contact plug and fills the contact hole, and a storage node is on the insulating layer in contact with the diffusion barrier layer. The storage node has a uniform outer surface morphology and a cavity therein. A second insulating layer is on the first insulating layer and separates the storage nodes from adjacent storage nodes, and a fill layer fills the cavities of the storage nodes. A dielectric layer having a large dielectric constant covers the second insulating layer, the fill layer, and the storage nodes, and a plate node is on the dielectric layer. The storage node has a smooth surface adjacent the dielectric layer, which decreases leakage current.

Abstract: A DRAM capacitor contact comprised of a silicon oxide layer with a trench having sidewalls and a form in the silicon oxide layer. A dielectric liner is coated on the sidewalls of the trench. A metal layer is then deposited between the sidewalls and polished to form a bit-line. One or more dielectric layers are deposited above the bit-lines and VIAs are formed in these layers. A sidewall is formed in the VIA above the bit-line and the VIAs are extended down to the silicon substrate and filled with a conductive material and planarized, forming the capacitor contact.

Abstract: A semiconductor device and a method for making a semiconductor device having a pillar-shaped capacitor storage node compatible with a high dielectric film, wherein the pillar shaped capacitor storage node includes a thick conductive metal layer that is easily etched and a thin conductive layer completely coating the thick conductive metal layer. The thin conductive layer protects the thick conductive metal layer during subsequent high dielectric deposition and annealing and various oxidation process.

Abstract: The present invention provides for use with an integrated circuit, an embedded memory having a transistor in contact with an interconnect formed within a dielectric layer overlaying the transistor. In one embodiment, the embedded memory comprises a capacitor located on the dielectric layer that contacts the interconnect. In this particular embodiment, the capacitor includes a first electrode located on the interconnect wherein the first electrode is a layer of aluminum, aluminum alloy or titanium nitride and substantially free of a titanium layer. In one advantageous embodiment, the first electrode layer is an aluminum alloy. Moreover, the thickness of the first electrode may, of course, varying depending on the design. However, in one is particular embodiment, the first electrode may have a thickness ranging from about 10 nm to about 50 nm.

Abstract: There is described the manufacture of a semiconductor device having a storage node or high-yield manufacture of a compact memory IC.

Abstract: In a trench capacitor type semiconductor memory device including a semiconductor substrate having a trench and first and second impurity diffusion source/drain regions, a capacitor electrode buried in the trench, and a substrate-side capacitor electrode and a capacitor insulating layer within the semiconductor substrate and adjacent to a lower portion of the capacitor electrode, a buried insulating layer is formed between the semiconductor substrate and an upper portion of the capacitor electrode. The buried insulating layer is thicker than the capacitor insulating layer. However the buried insulating layer on a surface of the second impurity diffusion source/drain region is thin, or in direct contact with the capacitor electrode. A silicide layer is formed on the second impurity diffusion source/drain region and the capacitor electrode.

Abstract: An improved storage node junction between a doped active area in a semiconductor substrate and an overlying layer of polysilicon, such as the storage node junction in a DRAM memory cell. The area and perimeter of the storage node junction is significantly reduced and the junction is moved away from the adjacent isolation structure. An exemplary semiconductor device incorporating the new junction includes a storage node junction between a conductive polysilicon layer and an active area on a semiconductor substrate, the substrate having been subjected to LOCOS steps to create active areas bounded by a region of field oxide. An insulated gate electrode is formed over an active area on the substrate, which has been doped to a first conductivity type. A contact region comprising a portion of the active area extends laterally between one side of the gate electrode and the field oxide region.

Abstract: A semiconductor memory device includes a semiconductor substrate and first, second, third and fourth spaced apart word lines formed on the semiconductor substrate and extending in a first direction. First, second, and third spaced apart bit lines are formed on the semiconductor substrate and extend in a second direction. An isolated active areas are formed on the semiconductor substrate under the second bit line. A first transfer gate transistor is formed in the active area, the first transfer gate transistor including spaced apart source and drain regions and the second word line being insulatively spaced from a channel region between the source and drain regions. A second transfer gate transistor is formed in the active area, the second transfer gate transistor including spaced apart source and drain regions and the third word line being insulatively spaced from a channel region between the source and drain regions.