Abstract: Methods of forming FRAM devices include the steps of forming first and second field effect access transistors in a semiconductor substrate, forming first and second bit lines (BL) electrically coupled to a drain region of the first field effect access transistor and a drain region of the second field effect access transistor, respectively, and forming first and second ferroelectric capacitors (CF) between the first and second bit lines in order to improve integration density. These first and second ferroelectric capacitors share a first electrode extending between the first and second bit lines and have respective second electrodes electrically coupled to respective source regions of the first and second field effect access transistors. The preferred methods may also include the step of forming a field oxide isolation region adjacent a face of the substrate and extending between the first and second field effect access transistors.

Abstract: In a semiconductor device comprising a cylindrical storage node, the surface area of the storage node is increased by forming silicone grains in an amorphous silicone film by a heat treatment only to an outer wall of the cylindrical portion to thereby form a roughened surface in the outer wall, and the amorphous silicone film is left in an inner wall without conducting a surface roughening treatment to the inner wall whereby the physical strength of the cylindrical portion is maintained and the destruction and the breakage of the cylindrical portion are prevented.

Abstract: Disclosed is a method of forming a self-aligned contact to a semiconductor substrate by use of a sacrificial spacer. The sacrificial spacer has the advantage of self aligning metallization to the semiconductive substrate or to a polysilicon plug material without extra photolithography steps as are required in the prior art.

Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.

Abstract: First conductive layers having structures similar to that of a storage node of a memory cell capacitor are isolated from each other, and are commonly and electrically connected to a third conductive layer. A second conductive layer corresponding to a cell plate of the memory cell capacitor is formed on the first conductive layers with a capacitor insulating film therebetween. Opposed portions of the first and second conductive layers have large areas, so that a large number of parallel unit capacitance elements can be formed within a limited area, and a capacitance element can have a good area efficiency.

Abstract: A data processing system having a DRAM and a non-volatile memory, such as a ROM or a programmable ROM (PROM), is implemented on a single integrated circuit using DRAM data processing techniques. The DRAM is manufactured in accordance with known processing techniques. The non-volatile memory is manufactured using the same DRAM manufacturing techniques, with the addition of a processing step in which a first terminal of a stacked capacitor manufactured in accordance with the DRAM process, is coupled to a known-reference voltage. This stacked capacitor structure may be coupled to a known conductor through the formation of a via and the subsequent coupling of a conductor to the stacked capacitor structure through the via. Alternatively, the stacked capacitor structure may be coupled to the known reference voltage through an internal connection to that reference voltage.

Abstract: A contact in a semiconductor memory device is formed on an active region of a cell array region, rather than on a sloped area between the cell array region and a core region. Preferably, an insulating layer on the active region is etched to form a hole therein and the contact formed through the hole. Preferably, the etching is performed using an etch solution having a high etch selectivity between the insulating layer and a top layer of the active region. Thus, the contact is evenly formed and the area of the cell array region is reduced, thereby enabling cells to be packed on a chip with high density.

Abstract: An analog semiconductor device capable of preventing open of interconnection lines and notching due to step between transistor and capacitor regions is disclosed. An analog semiconductor device according to the present invention, includes a semiconductor substrate; a first, a second, and a third isolating layer of trench type formed on the substrate and defining a transistor region and a capacitor region, respectively; a lower electrode of a capacitor formed in the surface of the substrate of the capacitor region; an oxide layer formed under the lower electrode and insulating the lower electrode and the substrate; an gate insulating layer formed on the substrate of the transistor region; an dielectric layer formed on the lower electrode; a gate formed on the gate insulating layer; an upper electrode of the capacitor formed on the dielectric layer.

Abstract: A semiconductor memory device has a redundancy function using a fuse block arranged in a window. The fuse block includes a plurality of fuse elements selectively cut by a laser beam in the window for decoding the input address of a defective memory cell. Each fuse element has a pair of parallel lead sections, and a bridge section bridging the ends of the lead sections and disposed for laser cutting. The longer sides of the window can be reduced in size for reduction of the occupied area for the pitch of signal lines and thus the chip area.

Abstract: A fin type storage node electrode projects from an inter-level insulating layer so as to use the top, side and back surfaces thereof for accumulation of electric charge, and testing elements for evaluating properties of the layers of the storage node electrode are concurrently formed directly on the inter-level insulating layer, thereby preventing the testing elements from undesirable breakage.

Abstract: An improved storage node junction between a doped active area in a semiconductor substrate and an overlying layer of polysilicon, such as the storage node junction in a DRAM memory cell. The area and perimeter of the storage node junction is significantly reduced and the junction is moved away from the adjacent isolation structure. An exemplary semiconductor device incorporating the new junction includes a storage node junction between a conductive polysilicon layer and an active area on a semiconductor substrate, the substrate having been subjected to LOCOS steps to create active areas bounded by a region of field oxide. An insulated gate electrode is formed over an active area on the substrate, which has been doped to a first conductivity type. A contact region comprising a portion of the active area extends laterally between one side of the gate electrode and the field oxide region.

Abstract: A storage node to be a lower electrode of a capacitor is electrically connected to a polysilicon columnar conductive body filling a contact hole with a second polysilicon film therebetween. The second polysilicon film covers the inside of an opening portion formed in the first polysilicon film. The polysilicon film columnar conductive body is electrically connected to a source/drain region of an MOS transistor at a contact. Thus, a semiconductor device with good electrical connection between the capacitor and the transistor may be provided.

Abstract: A process for making a capacitor for a silicon-on-insulator (SOI) structure. The SOI structure has a p-type silicon base layer, a buried oxide layer, a silicon layer, and an n+ layer formed within a portion of the p-type silicon base layer. The process comprises the steps of forming a buried oxide layer and a silicon layer in the p-type silicon base layer, forming an n+ layer in a portion of the p-type silicon base layer, and forming electrically conductive paths to the p-type silicon base layer and the n+ layer extending through the buried oxide and silicon layers.

Abstract: A semiconductor device has a device isolation oxide film, an interlayer insulating film, hydrogen barrier films, a lower electrode, a capacitor insulating film, an upper electrode, an interlayer insulating film and a wiring layer, formed on a silicon substrate. A gate electrode is formed on a gate oxide film between impurity diffusion regions in the silicon substrate. Further, a capacitor portion, comprising the lower electrode, the capacitor insulating film (ferroelectric or high dielectric substance) and the upper electrode, is completely covered with the hydrogen barrier films. The hydrogen barrier films prevent deterioration of the ferroelectric substance and the high dielectric constant material due to reducing conditions in a hydrogen atmosphere. Other device characteristics, however, are not adversely affected because only the capacitor portion is completely covered with the hydrogen barrier films.

Abstract: A semiconductor structure uses a shallow trench isolation (STI) region to realize a capacitor trench of a reduced size. Consistent with one embodiment of fabricating a memory cell, the invention includes selectively removing portions of a substrate using a patterned mask to form a capacitor trench and an isolation trench at least partially around the capacitor trench. An oxide is formed in the isolation trench and the capacitor trench, and the oxide is selectively removed in the capacitor trench. Portions of the substrate defining the base and sidewalls of the capacitor trench are then doped and a capacitor dielectric is formed in the capacitor trench, leaving a portion of the trench unfilled. A polysilicon layer is formed it the unfilled portion of the capacitor trench and over the capacitor dielectric to form a plate of the storage capacitor.

Abstract: Semiconductor capacitor constructions, DRAM cell constructions, methods of forming semiconductor capacitor constructions, methods of forming DRAM cell constructions, and integrated circuits incorporating capacitor structures and DRAM cell structures are encompassed by the invention. The invention includes a method comprising: a) forming an opening within an insulative layer and over a node location; b) forming a spacer within the opening to narrow the opening, the spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed opening; c) removing a portion of the insulative layer from proximate the outer surface to expose at least a portion of the outer surface; d) forming a storage node layer in electrical connection with the node location, extending along the spacer inner surface, and extending along the exposed spacer outer surface; and e) forming a dielectric layer and a cell plate layer operatively proximate the storage node layer.

Abstract: Source/drain regions of an MOS transistor are formed at a surface of a p-type silicon substrate. A storage node electrically connected to the source/drain regions penetrates a bit line to reach the n-type source/drain region. The storage node and the bit line are insulated from each other by a sidewall insulating layer. Thus, a semiconductor memory device suitable for high integration is obtained in which short-circuit between the storage node and the bit line on a gate electrode layer can be prevented.

Abstract: In a semiconductor memory device such as a DRAM, a conductive film (1.11') is arranged on the rim portion of a isolation insulating film (1.2) in opposition to a semiconductor substrate (1.1) with a thin insulating film in between. This conductive film (1.11') is electrically connected to a lower electrode (1.11) of a storage capacitor. This novel arrangement can control the location of electrical pn junction independently of the location of metallurgical pn junction, thereby realizing a semiconductor memory device having a long data retention time with the increase in leakage current suppressed.

Abstract: An exemplary implementation of the present invention includes a capacitor for a dynamic random access memory cell having a first plate; a second plate; and a dielectric layer interposed between said first and second plates, with the dielectric layer being dominated by electrode-limited conduction, which includes tantalum pentoxide and silicon nitride, or a combination of the two. In a preferred implementation, one of the two capacitor plates is formed from a silicon-germanium layer, the second plate is formed from a metal and the dielectric layer is formed from tantalum pentoxide.

Abstract: The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q of a DRAM and a sheet resistance of bit lines BL.sub.1, BL.sub.2 are, respectively, 2 .OMEGA./.quadrature. or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL.sub.1, BL.sub.2 by which the number of the steps of manufacturing the DRAM can be reduced.

Abstract: A semiconductor device includes a semiconductor substrate having an active area including first and second impurity regions of a transistor, a gate formed over the active area of the semiconductor substrate and isolated from the semiconductor substrate, a first insulating interlayer formed on the semiconductor substrate and having first and second contact holes exposing the first and the second impurity regions, respectively, a capacitor having a storage electrode and a plate electrode, the storage electrode being connected electrically to the first impurity region through the first contact hole, a bit line contact pad connected electrically to the second impurity region through the second contact hole, a second insulating interlayer formed on the plate electrode and having a third contact hole exposing the bit line contact pad, and a bit line formed on the second insulating interlayer and in contact with the bit line contact pad through the third contact hole.

Abstract: A DRAM device includes bit lines formed on an interlayer insulation film which covers gate electrodes on an insulation film on a semiconductor substrate. Each bit line is in contact with the corresponding source region formed in the substrate through an opening in the insulation films. Another insulation film is formed so as to cover the bit lines. A storage electrode is formed on the insulation film covering the bit line, and is in contact with a drain region in the substrate through another opening in the insulation films. The bit line has a vertical layer level lower than that of the storage electrode. The storage electrode is covered with a dielectric film, which is covered with an opposed electrode.

Abstract: A semiconductor device with a memory cell having a transfer transistor and a storage capacitor is provided, which is capable of further miniaturization of the storage capacitor. The transistor is formed in an active region of a semiconductor substrate. An insulating layer is formed on the substrate to cover the active region. The insulating layer has a penetrating opening extending to a source/drain region of the transistor. A first cylindrtical electrode is formed in the opening of the insulating layer to be electrically connected to the first source/drain region. A second cylindrtical electrode is formed in the opening of the insulating layer in the inside of the first electrode to be concentric with the first electrode. A dielectric layer is formed on the insulating layer to cover the surface of the first and second electrodes. A third electrode is formed on the dielectric to be opposite to the first and second elecgrodes through the dielectric layer.

Abstract: A method for reducing the parasitic capacitance and capacitive coupling of nodes (106) in a dielectrically isolated integrated circuit (100) using layout changes. A separate area of floating silicon (110) is created adjacent two or more dielectrically isolated nodes (106). The two or more nodes (106) are chosen that "slew together" (i.e., nodes that are required to change by the same voltage at the same time). The area of floating silicon (110) is created by placing an additional trench (112) around both of the dielectrically isolated nodes (106).

Abstract: There is provided a (Ba, Sr) TiO.sub.3 film of higher dielectric constant and less leakage current for serving as a dielectric thin film of a capacitor in a semiconductor memory. DPM (dipivaloylmethanato) compounds of Ba, Sr and Ti are dissolved in THF (tetrahydrofuran) to obtain Ba(DPM).sub.2 /THF, Sr(DPM).sub.2 /THF and TiO(DPM).sub.2 /THF solutions which are used as source material solutions. A (Ba, Sr) TiO.sub.3 film is formed by a CVD method while increasing a relative percentage of a Ti source material flow rate to a sum of Ba source material flow rate and Sr source material flow rate. The film formation is carried out in multiple steps, and annealing is applied in each step after deposition of the film.

Abstract: A multiple tubular shaped capacitor electrode of a semiconductor capacitor with an increased surface area and a method for fabricating thereof. The multiple tubular shaped capacitor includes at least two tubular shapes whose side portions are overlapped with each other. The multiple tubular shaped capacitor is made by forming an insulating layer over an etch stop layer including a contact plug, partially etching the insulating layer down to the contact plug and etch stop layer to form an opening composed of at least two upright cylindrical openings with side portions that define an overlap, and forming a conductive layer on a bottom and both side walls of the opening to form a storage node composed of at least two upright tubular shapes which are attached together at a vertical side section which defines an overlap portion of both tubular shapes to form a capacitor storage node.

Abstract: An integrated DRAM cell comprises a DRAM capacitor and a transistor. The capacitor of the cell is formed in a first well in a dielectric layer overlying the cell transistor. The top electrode of the capacitor also serves as a barrier layer between an underlying plug in a second well in the dielectric layer. A method of forming the cell comprises the step of using a single mask for formation of the layer which acts as both the top electrode of the capacitor and the barrier layer of the second well.

Abstract: The present invention discloses a novel multiple fin-shaped capacitor for use in semiconductor memories. The capacitor has a plurality of horizontal fins and a crown shape. The capacitor structure comprises a bottom storage electrode. The bottom storage electrode comprises of a plurality of horizontal fins and a crown shape, wherein said crown shape includes two vertical pillars, and said plurality of horizontal fins extend outside from an external surface of said crown shape. A second dielectric layer is formed on the surface of the bottom storage electrode layer. A top storage electrode layer is formed along the surface of second dielectric layer. By including horizontal fins and vertical pillars, the surface area of the capacitor is significantly increased, resulting in increased capacitance.

Abstract: A DRAM device includes bit lines formed on an interlayer insulation film which covers gate electrodes on an insulation film on a semiconductor substrate. Each bit line is in contact with the corresponding source region formed in the substrate through an opening in the insulation films. Another insulation film is formed so as to cover the bit lines. A storage electrode is formed on the insulation film covering the bit line, and is in contact with a drain region in the substrate through another opening in the insulation films. The bit line has a vertical layer level lower than that of the storage electrode. The storage electrode is covered with a dielectric film, which is covered with an opposed electrode.

Abstract: It is an object to compatibly realize a decrease in an on-state voltage and an increase in a current capable of turn-off. An N layer (43) having an impurity concentration higher than that of an N.sup.- layer (42) is formed between the N.sup.- layer (42) and a P base layer (44). In the exposed surface of the P base layer (44) connected to an emitter electrode (51), a P.sup.+ layer (91) having an impurity concentration higher than that of the P base layer (44) is formed. The formation of the N layer (43) allows the carrier distribution in the N.sup.- layer (42) to be close to the carrier distribution of a diode, so that the on-state voltage is decreased while maintaining high the current value capable of turn-off. Furthermore, the P.sup.+ layer (91) allows holes to easily go through form the P base layer (44) to the emitter electrode (51), which increases the current value capable of turn-off.

Abstract: First conductive layers having structures similar to that of a storage node of a memory cell capacitor are isolated from each other, and are commonly and electrically connected to a third conductive layer. A second conductive layer corresponding to a cell plate of the memory cell capacitor is formed on the first conductive layers with a capacitor insulating film therebetween. Opposed portions of the first and second conductive layers have large areas, so that a large number of parallel unit capacitance elements can be formed within a limited area, and a capacitance element can have a good area efficiency.

Abstract: A coverage can be improved when an upper layer is formed on an upper wiring patterned on an interlayer insulation film. A sidewall made of an insulating material is bonded to a side face of the upper wiring patterned on the interlayer insulation film. Consequently, a height difference between the upper wiring and the interlayer insulation film has a small gradient. By flattening a laminated face of the upper layers including surfaces of the upper wiring and the sidewall, a further upper layer to be formed can have a coverage improved.

Abstract: There is provided a semiconductor device, including: a semiconductor substrate having a major surface; a first insulating film formed on the major surface of the semiconductor substrate; a plurality of first conductive members spaced apart from each other on the first insulating film and formed to be connected to the semiconductor substrate; a plurality of storage electrodes formed on the first insulating film at positions respectively corresponding to the first conductive members; a plurality of high-permittivity films respectively stacked on the plurality of storage electrodes; a plurality of first counter electrodes respectively stacked on the plurality of high-permittivity films; a second insulating film, having a permittivity much lower than a permittivity of each of the high-permittivity films, for insulating the first conductive members, the high-permittivity films, and the first counter electrodes, respectively; and a second counter electrode, formed on the second insulating film, for connecting adjac

Abstract: The trench capacitors formed in a semiconductor wafer include trenches formed in said semiconductor substrate, first storage nodes includes doped ion regions and doped polysilicon structures, the doped regions are formed in a surface of the trenches. The doped polysilicon structures are formed on the walls of the trenches. An isolation structure is formed on said substrate between said trenches for isolation. A dielectric layer substantially covers the first storage nodes. A field plate is formed on the isolation structure and Second storage nodes is formed in the trenches and on the dielectric layer.

Abstract: Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers sloping at an angle with of about 80-85 degrees with respect to an underlying silicon substrate. As such, the novel capacitor is formed in a sloped contact opening. The contact area of electrical connection of the lower capacitor plate with an underlying active region has a sufficiently small horizontal cross-section that the contact area will not extend laterally beyond the active region and leakage will not occur. A method for forming the contact opening is disclosed and comprises first, the formation of an active region, preferably located between two insulating bird's beak regions, and covering the active area with a thin layer of oxide etch barrier material. A polysilicon layer is then formed above the oxide etch barrier.

Abstract: Thin film metal-insulator-metal capacitors having enhanced surface area are formed by a substituting metal for silicon in a preformed electrode geometry. The resulting metal structures are advantageous for high-density DRAM applications since they have good conductivity, enhanced surface area and are compatible with capacitor dielectric materials having high dielectric constant.

Abstract: A semiconductor device includes a semiconductor substrate having a major surface; a first interlayer insulating film formed on the semiconductor substrate and having an opening defined therein so as to open at the major surface of the semiconductor substrate; a connecting member made of Si as a principal component and embedded in the opening; a lower capacitor electrode connected electrically with the major surface of the semiconductor substrate through the connecting member; a capacitor dielectric film formed on the lower capacitor electrode; an upper capacitor electrode formed on the capacitor dielectric film; and a second interlayer insulating film formed on the capacitor upper electrode. The lower capacitor electrode referred to above is made of a principal component selected from the group consisting of ruthenium and iridium and contains oxygen in a quantity of 0.001 to 0.1% by atom and/or at least one impurity element in a quantity of 0.1 to 5% by atom.

Abstract: The memory cell in the present invention is formed in a semiconductor substrate with isolations formed upon to separate cells. The cell has an oxide layer between the isolations. The oxide layer includes a pad oxide member, two tunnel oxide members, and two insulating oxide members. The two insulating oxide members are separated from both sides of the pad oxide member by the two tunnel oxide members. The two tunnel oxide members are thinner than the pad oxide member and the two insulating oxide members. The memory cell has a doped junction region in the semiconductor substrate under the two insulating oxide members and the two tunnel oxide members. The cell also has a first conductive layer over the oxide layer and a dielectric layer over the first conductive layer. A second conductive layer is located over the dielectric layer. In addition, the memory cell can further include an undoped hemispherical grain (HSG) silicon film between the first conductive layer and the dielectric layer.

Abstract: A capacitor structure in a semiconductor memory cell includes a lower electrode formed on a base body, a capacitor insulation film which is a ferroelectric thin film formed on the lower electrode, and an upper electrode formed on the capacitor insulation film. The lower electrode is shaped semi-spherical. The capacitor structure has an increased area of the upper electrode in contact with the ferroelectric thin film, local concentration of an electric field in the ferroelectric thin film is unlikely to occur.

Abstract: A semiconductor memory device and method of fabricating the same includes a first insulation layer and a first conductive layer formed on a substrate; conductive sidewall spacers protruding upwardly on the sides of the first conductive layer; a second insulation layer formed on the substrate and covering the conductive sidewall spacers; a second conductive layer, a third insulation layer, a third conductive layer, and a fourth insulation layer sequentially formed on the second insulation layer; a contact hole formed through the second and third conductive layers and the second through fourth insulation layers; insulative sidewall spacers formed on the sidewalls of the contact hole; and a fourth conductive layer formed in the contact hole so as to be in contact with the first conductive layer.

Abstract: A DRAM array having trench capacitor cells of potentially 4F.sup.2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an arrays. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.

Abstract: In a method of fabricating a COB DRAM cell, a polysilicon plug is formed on the source and drain in self-alignment with the gate electrode. A bit line contact and a storage electrode contact are formed on the polysilicon plug thereby to reduce the aspect ratio of both the bit line contact and the storage electrode contact. With the polysilicon plug formed in self-alignment with the gate electrode, short-circuiting of contacts of adjacent element regions and short-circuiting of the plugs of the source and drain will not occur, leading to high protection against misregistration. Moreover, an independent lithography process is not required for forming the polysilicon plug, and, therefore, the number of fabrication steps is reduced.

Abstract: A double layer planar polysilicon capacitor for use within integrated circuits and a method by which that planar polysilicon capacitor is formed. Formed within a semiconductor substrate is a deep trench which is filled with a dielectric material. Formed within the dielectric material within the deep trench is a shallow trench which has a first polysilicon capacitor plate formed therein. The upper surface of the first polysilicon capacitor plate is substantially planar with the semiconductor substrate. Formed upon the first polysilicon capacitor plate is a polysilicon capacitor dielectric layer. Formed upon the polysilicon capacitor dielectric layer is a second polysilicon capacitor plate.

Abstract: Testing elements are disposed to prevent breakage by locating them such that their entire lower surface is formed directly on an insulating layer of a semiconductor device. These testing elements may be used with a fin type storage node electrode projecting from an inter-level insulating layer so as to use the top, side and back surfaces thereof for accumulation of electric charge. These testing elements may be used for evaluating properties of the layers of the storage node electrode and be concurrently formed directly on the inter-level insulating layer, thereby preventing the testing elements from undesirable breakage.

Abstract: A semiconductor memory device having a semiconductor substrate, an insulating layer provided on the substrate, and a memory cell. The memory cell has a switching transistor provided on the substrate and a charge storage element in a trench made in the insulating layer. The charge storage element has a bottom electrode, a dielectric layer and a top electrode deposited one on another in the order mentioned.

Abstract: A capacitor having the pipe structure produced in a semiconductor device, wherein the number of combinations of two pieces of pipe shaped electrodes which face to each other across a pipe shaped dielectric layer is plural, so that the capacitor of this invention is allowed to have a large surface area in which two electrodes face to each other across a dielectric layer, resultantly increasing the amount of electrostatic capacity per unit horizontal area thereof without being accompanied by a decrease in integration and a decrease in the mechanical reliability.

Abstract: A method of forming a storage electrode on a silicon oxide layer is provided wherein a titanium nitride barrier metal layer is formed on an entire surface of the insulation layer. A tungsten storage electrode film is formed on an entire surface of the titanium nitride barrier metal layer. A titanium nitride etch back stopper film is formed on an entire surface of the storage electrode film. The etch back stopper film and the storage electrode film are selectively removed by a dry etching to define a storage electrode body, but leave the barrier metal layer over the entire surface of the silicon oxide layer. A tungsten side wall electrode film is entirely formed. The side wall electrode film is selectively removed by an etch back whereby the side wall electrode films remain only on the side walls of the storage electrode body.

Abstract: A DRAM cell is formed by forming a capped gate line on a substrate, including a gate line insulation layer on the substrate, a gate line on the gate line insulation layer and a gate line cap covering top and sidewall portions of the gate line. Spaced apart source/drain regions are formed in the substrate on opposite sides of the gate line. A dielectric region is formed covering the capped electrode. A storage electrode plug is formed extending from a surface of the dielectric region through the dielectric region and along a first sidewall portion of the gate line cap to contact a first of the source/drain regions. A channel electrode is formed extending from the surface of the dielectric region through the dielectric region and along a second sidewall portion of the gate line cap to contact a second of the source/drain regions.

Abstract: In an element region, in which a memory cell is constituted, on a silicon substrate, a gate electrode with which each of a plurality of the memory cells is individually constituted is individually disposed for each memory cell. A first and a second inter-layer insulating films are formed right upon the gate electrode. A jumping wiring is disposed on the insulating films. The jumping wiring is directly and electrically connected, within the memory pattern region in which the memory cell is formed, with each individual gate electrodes through the jumping contact.

Abstract: A method and structure for a lower capacitor electrode for a dynamic random access integrated circuit. A polysilicon gate layer is formed over a thin layer of oxide in a first region of a semiconductor substrate. Another oxide layer is then formed overlying the polysilicon gate layer. A polysilicon layer which was doped by S/D implant including the lower capacitor electrode self-aligns and forms overlying a second region of the semiconductor substrate and over the oxide layer on the polysilicon gate layer. A nitride layer forms on the lower capacitor electrode portion overlying the second region. Exposed portions of the polysilicon layer are then oxidized. The S/D was formed by driving dopant from implanted second layer polysilicon. Portions of polysilicon under the nitride layer corresponding to the lower capacitor electrode oxidizes at a slower rate than the exposed portions of the polysilicon.