Abstract: A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.

Abstract: The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.

Abstract: Reliability of a semiconductor device is improved. The semiconductor device including a first MISFET group of a plurality of first MISFETs and a second MISFET group of a plurality of second MISFETs has a plurality of trenches each formed in a semiconductor layer and formed of an upper trench part and a lower trench part, and a plurality of gate electrodes formed inside the plurality of trenches. A thinner gate insulator is formed to the upper trench part and a thicker field insulator is formed to the lower trench part. In a trench at the outermost position in the first MISFET group and a trench at the outermost position in the second MISFET group, the gate insulator is not formed in the upper trench part, but the field insulator is formed in the upper trench part and the lower trench part.

Abstract: A semiconductor device according to an embodiment includes: a SiC layer having a first plane and a second plane facing the first plane, the SiC layer including a first trench on a first plane side, an n-type first SiC region, a p-type second SiC region, an n-type third SiC region located in this order from the second plane to the first plane, a p-type fourth SiC region between the first SiC region and the first trench, a fifth SiC region between the first SiC region and the first plane, and a sixth SiC region between the fourth SiC region and the fifth SiC region, and the sixth SiC region having an n-type impurity concentration higher than an n-type impurity concentration of the first SiC region; a gate electrode in the first trench; a first electrode on the first plane side; and a second electrode on a second plane side.

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells.

Abstract: A semiconductor device includes: a semiconductor substrate having a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; rows of spicular-shaped field plate structures formed in the semiconductor substrate, the spicular-shaped field plate structures extending through the source region and the body region into the drift region; stripe-shaped gate structures formed in the semiconductor substrate and separating adjacent rows of the spicular-shaped field plate structures; and a current spread region of the first conductivity type formed below the body region in semiconductor mesas between adjacent ones of the spicular-shaped field plate structures and which are devoid of the stripe-shaped gate structures. The current spread region is configured to increase channel current distribution in the semiconductor mesas.

Abstract: A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.

Abstract: A testing environment includes a first measuring unit connected to a gate of a MOSFET device and a second measuring unit connected to a drain of the MOSFET device. The testing environment is particularly useful for testing gate charge for MOSFET devices. In a first phase, the gate of the device is driven with electrical current while the drain is driven with a constant voltage. As the MOSFET device turns on, the second measuring unit switches from providing the constant voltage to providing a constant current to the drain of the MOSFET, while measuring the drain voltage. The switching of modes is automatic and occurs without user intervention. After the MOSFET device has been driven to VgsMax by the gate current, all of the relevant data is stored, which may be analyzed and presented to a user in a User Interface or presented in other manner.

Abstract: An electronic circuit according to one aspect of the present technology includes an MOS circuit portion and a stabilizing element portion. The MOS circuit portion includes a deep well. The stabilizing element portion includes a first element portion arranged between a power supply source and the deep well, and stabilizes a potential of the deep well.

Abstract: A pulse modulator comprises a solid state power switch having a source, a drain, a gate and a separate gate drive connected to ground. One pulse modulator comprises a plurality of stages connected as an induction adder. Each stage includes a plurality of cells and at least some of the cells each include a solid state power switch having a source, a drain, a gate and a separate gate drive connected to ground to control the discharge of a capacitor. In one embodiment the solid state power switch is a power MOSFET.

Abstract: An apparatus comprising an insulated gate bipolar transistor; and a super-junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor wherein the super-junction metal-oxide semiconductor field effect transistor are structurally coupled and wherein the super-junction metal-oxide semiconductor field effect transistor is configured to switch to an ‘on’ state from an ‘off’ state and an ‘off’ state from an ‘on’ state.

Abstract: A high-voltage switching device that can be fabricated in a standard low-voltage process, such as CMOS, and more specifically SOI CMOS. Embodiments include integrated circuits that combine, in a unitary structure, a FET device and an integrated, co-fabricated modulated resistance region (MRR) controlled by one or more Voltage-Drop Modulation Gates (VDMGs). The VDMGs are generally biased independently of the gate of the FET device, and in such a way as to protect each VDMG from excessive and potentially destructive voltages. In a first embodiment, an integrated circuit high voltage switching device includes a transistor structure including a source, a gate, and an internal drain; an MRR connected to the internal drain of the transistor structure; at least one VDMG that controls the resistance of the MRR; and a drain electrically connected to the MRR. Each VDMG at least partially depletes the MRR upon application of a bias voltage.

Abstract: Provided are a semiconductor element and a semiconductor device capable of reducing possibilities of malfunctions and breakdowns due to temperature rise. A semiconductor element (50) includes a first MOS transistor (Tr1), a second MOS transistor (Tr2), and a temperature detecting element (TD) that are provided on a semiconductor substrate (SB). The first MOS transistor (Tr1) includes an n-type source region (8), an n-type first semiconductor region (21) arranged away from the source region (8) and a p-type well region (31) arranged between the source region (8) and the first semiconductor region (21). The second MOS transistor (Tr2) includes an n-type source region (8) an n-type second semiconductor region (22) arranged away from the source region (8), and a p-type well region (31) arranged between the source region (8) and the second semiconductor region (22). The first semiconductor region (21) is connected to the second semiconductor region (22).

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a semiconductor substrate including a high-frequency-block group and a low-power-block group; high-frequency-type logic standard cells located on the high-frequency-block group, and having a high-frequency-type cell height, a high-frequency-type operating frequency, and a high-frequency-type power; low-power-type logic standard cells located on the low-power-block group, and having a low-power-type cell height, a low-power-type operating frequency, and a low-power-type power. The high-frequency-type cell height is higher than the low-power-type cell height. The high-frequency-type operating frequency is greater than the low-power-type operating frequency. The high-frequency-type power is greater than the low-power-type power. The high-frequency-type logic standard cells include high-frequency-type fins, and the low-power-type logic standard cells include low-power-type fins.

Abstract: A semiconductor device is provided comprising an active portion and a terminating structure. The semiconductor device is provided comprising the active portion provided in the semiconductor substrate and a terminating structure provided at a termination of the front surface side of the semiconductor substrate and that mitigates an electric field of the termination. In the electric field distribution of the front surface side of the terminating structure, during rated voltage application, an electric field at the end portion of the active portion side may be smaller than a maximum value of an electric field distribution of the front surface side. In addition, the electric field distribution of the terminating structure may have a maximum peak of the electric field on the edge side opposite to the active portion with respect to a center of the terminating structure.

Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.

Abstract: A semiconductor device has an active region through which current flows and a termination structure region. At a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. At a surface of the first semiconductor layer, a lower parallel pn structure is provided. At a surface of the lower parallel pn structure, an upper parallel pn structure is provided in the termination structure region and a first semiconductor region of a second conductivity type is provided in the active region. A width of an upper second column is wider than a width of a lower second column. An interval between the upper second columns is wider than an interval between the lower second columns. A thickness of the upper second column is thicker than a thickness of the first semiconductor region.

Abstract: There is a need to provide a semiconductor device and an electronic control system including the same while the semiconductor device is capable of continuing normal operation even when a negative surge voltage is applied. According to an embodiment, a driver IC includes an output transistor, a driver control circuit, a negative potential clamp circuit, and an ESD protection circuit. The output transistor is provided between a battery voltage terminal and an output terminal coupled to a load. The driver control circuit switches on-off state of the output transistor by controlling a gate voltage of the output transistor with reference to a voltage of the output terminal. The negative potential clamp circuit turns on the output transistor regardless of control from the control circuit when a negative voltage lower than a predetermined voltage is applied to the output terminal.

Abstract: Disclosed herein is a MOS transistor embedded substrate that includes first and second MOS transistors each having a source electrode formed on one surface and a drain electrode formed on other surface, and an insulation resin layer in which the first and second MOS transistors are embedded such that the source electrode of the first MOS transistor and the drain electrode of the second MOS transistor face a same direction and that the drain electrode of the first MOS transistor and the source electrode of the second MOS transistor face a same direction.

Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.

Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, and third semiconductor regions, a gate electrode, first, and second conductive parts. The first semiconductor region includes a first region and a second region. The second semiconductor region is provided on the first region. The third semiconductor region is provided on the second semiconductor region. The second electrode is provided on the third semiconductor region. The gate electrode opposes the second semiconductor region in a second direction. The first conductive part is provided on the second region and is provided in a plurality in a third direction. The first conductive parts are arranged with the gate electrode in the second direction. The second conductive part is provided on the second region, and arranged with the gate electrode and the first conductive parts in the third direction.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate, forming a first bottom source/drain region at sides of a first fin of the plurality of fins in a first transistor region, and forming a second bottom source/drain region at sides of a second fin of the plurality of fins in a second transistor region. The first and second bottom source/drain regions are oppositely doped. In the method, a bottom spacer layer is formed on the first and second bottom source/drain regions, and the bottom spacer layer is removed from the second bottom source/drain region. A high-k dielectric layer is formed on the bottom spacer layer in the first transistor region, and directly formed on the second bottom source/drain region in the second transistor region. The method also includes forming a gate conductor on the high-k dielectric layer.

Abstract: A semiconductor device, method of manufacture of a semiconductor device, and electronic system are disclosed. For example, the semiconductor device includes at least one trench disposed in a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate has a first conductivity type. The semiconductor device further includes a polysilicon depleted gate shield disposed in the at least one trench, wherein the polysilicon depleted gate shield has a second conductivity type. The semiconductor device also includes a drift region disposed in the semiconductor substrate adjacent to at least one sidewall of the at least one trench, wherein the drift region has the first conductivity type, and a polysilicon gate disposed over the depleted gate shield in the at least one trench.

Abstract: A semiconductor device, method of manufacture of a semiconductor device, and electronic system are disclosed. For example, the semiconductor device includes at least one trench disposed in a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate has a first conductivity type. The semiconductor device further includes a polysilicon depleted gate shield disposed in the at least one trench, wherein the polysilicon depleted gate shield has a second conductivity type. The semiconductor device also includes a drift region disposed in the semiconductor substrate adjacent to at least one sidewall of the at least one trench, wherein the drift region has the first conductivity type, and a polysilicon gate disposed over the depleted gate shield in the at least one trench.

Abstract: Some embodiments include a method of forming an integrated assembly. A structure is provided to have conductive lines, and to have rails over the conductive lines and extending in a direction which crosses the conductive lines. Each of the rails includes pillars of semiconductor material. The rails have sidewall surfaces along spaces between the rails. The pillars have upper segments, middle segments and lower segments. First-material liners are formed along the sidewall surfaces of the rails. A second material is formed over the liners. First sections of the liners are removed to form gaps between the second material and the sidewall surfaces of the rails. Second sections of the liners remain under the gaps. Conductive material is formed within the gaps. The conductive material is configured as conductive lines which are along the middle segments of the pillars.

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a channel region that protrudes from an upper surface of a substrate in a vertical direction, forming a gate insulator layer on a side of the channel region, after forming the gate insulator layer, forming a top source/drain on the channel region, and forming a gate electrode on the gate insulator layer.

Abstract: A semiconductor device according to an exemplary embodiment of the present invention includes an n? type epitaxial layer disposed on a first surface of a substrate; a p type region disposed on the n? type epitaxial layer, an n+ type region disposed on the p type region, a gate disposed on the n? type epitaxial layer, an oxidation film disposed on the gate, a source electrode disposed on the oxidation film and the n+ type region, and a drain electrode disposed on a second surface of the substrate. The gate includes a PN junction portion.

Abstract: A semiconductor device may include active fins spaced apart from each other by a recess therebetween, each of the active fins protruding from an upper surface of a substrate, an isolation structure including a liner on a lower surface and a sidewall of a lower portion of the recess and a blocking pattern on the liner, the blocking pattern filling a remaining portion of the lower portion of the recess and including a nitride, a carbide or polysilicon, a gate electrode structure on the active fins and the isolation structure, and a source/drain layer on a portion of each of the active fins adjacent to the gate electrode structure.

Abstract: A device is disclosed that includes a first transistor device of a first type and a second transistor device of a second type positioned vertically above the first transistor, wherein the first type and second type of transistors are opposite types. The device also includes a gate structure for the first transistor and the second transistor, wherein the gate structure comprises a first gate electrode for the first transistor and a second gate electrode for the second transistor and a gate stack spacer positioned vertically between the first gate electrode and the second gate electrode so as to electrically isolate the first gate electrode from the second gate electrode.

Abstract: Technologies for selectively etching oxide and nitride materials on a work piece are described. Such technologies include methods for etching a work piece with a remote plasma that is produced by igniting a plasma gas flow. Microelectronic devices including first and second fins that are laterally offset by a fin pitch to define a first field there between are also described. In embodiments the microelectronic devices include a conformal oxide layer and a conformal nitride layer on at least a portion of the first and second fins, where the conformal nitride layer is on at least a portion of the conformal oxide layer and a sacrificial oxide material is disposed within the first field.

Abstract: A semiconductor device according to the present invention includes a first conductive-type semiconductor layer, a second conductive-type base region that is arranged in the front surface portion of the semiconductor layer, a plurality of trenches that extend from a front surface of the semiconductor layer beyond a bottom portion of the base region with an active region being defined therebetween, a plurality of first conductive-type emitter regions that are arranged in the active region, each connecting the trenches adjacent to each other, a gate electrode that is embedded in the trench, an embedding insulating film that is embedded in the trench on the gate electrode and that has an upper surface in the same height position as the front surface of the semiconductor layer or in a height position lower than the front surface and an emitter electrode that covers the active region and the embedding insulating film and that is electrically connected to the base region and the emitter region.

Abstract: In a manufacturing method of a silicon carbide semiconductor device, a semiconductor substrate made of silicon carbide and on which a base layer is formed is prepared, a trench is provided in the base layer, a silicon carbide layer is epitaxially formed on a surface of the base layer while filling the trench with the silicon carbide layer, the sacrificial layer is planarized by reflow after forming the sacrificial layer, and the silicon carbide layer is etched back together with the planarized sacrificial layer by dry etching under an etching condition in which an etching selectivity of the silicon carbide layer to the sacrificial layer is 1.

Abstract: A four-terminal GaN transistor and methods of manufacture, the transistor having source and drain regions and preferably two T-shaped gate electrodes, wherein a stem of one of the two T-shaped gate electrodes is more closely located to the source region than it is to a stem of the other one of the two T-shaped gate electrodes and wherein the stem of the other one of the two T-shaped gate electrodes is more closely located to the drain region than it is to the stem of said one of the two T-shaped gate electrodes. The the gate closer to the source region is a T-gate, and the proximity of the two gates is less than 500 nm from each other. The spacing between the stem of the RF gate and source region and the stem of the DC gate and drain region are preferably defined by self-aligned fabrication techniques. The four-terminal GaN transistor is capable of operation in the W-band (75 to 100 GHz).

Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.

Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.

Abstract: A semiconductor die includes a single power transistor or power diode, a temperature sense diode formed close enough to the single power transistor or power diode to measure an accurate temperature. The temperature sense diode comprises first and second diodes or strings of diodes. A separate integrated circuit is operable to measure first and second voltage drops of both the first and second diodes or strings of diodes using same magnitude currents, and estimate the temperature of the single power transistor or power diode based on the difference between the first and second forward voltage drop measurements. An overall pn junction area of the first diode or string of first diodes is different from an overall pn junction area of the second diode or string of second diodes.

Abstract: A semiconductor device includes a semiconductor layer that has a main surface including a defined region defined by a trench, a trench insulation layer formed in the trench, a field insulation layer that covers the defined region away from the trench, and a bridge insulation layer that is formed in a region between the trench and the field insulation layer in the defined region and that is connected to the trench insulation layer and to the field insulation layer.

Abstract: A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.

Abstract: A field effect transistor semiconductor device having a compact device footprint for use in automotive and hot swap applications. The device includes a plurality of field effect transistor cells with the plurality of transistor cells having at least one low threshold voltage transistor cell and at least one high threshold voltage transistor cell arranged on a substrate. The field effect transistor semiconductor device is configured and arranged to operate the at least one high threshold voltage transistor cell during linear mode operation, and operate both the low threshold voltage transistor cell and the high threshold voltage transistor cell during resistive mode operation. Further provided is a method of operating field effect transistor semiconductor device including a plurality of field effect transistor cells that includes at least one low threshold voltage transistor cell and at least one high threshold voltage transistor cell.

Abstract: Some embodiments include a memory device. The device has a fin with a first source/drain region, a second source/drain region and a channel region. The first source/drain region extends to a first height. The second source/drain region extends to a second height less than the first height. The channel region extends along a trough between the first and second source/drain regions. A charge-storage device is over the first source/drain region. A first sense/access line is along a sidewall of the fin and is spaced from the channel region by dielectric material. A second sense/access line is over the second source/drain region. An uppermost surface of the second sense/access line is beneath an uppermost surface of the first source/drain region. Some embodiments include memory arrays, and some embodiments include methods of forming memory arrays.

Abstract: Device and methods are provided for fabricating semiconductor devices in which metal-insulator-metal (MIM) capacitor devices are integrally formed with vertical field effect transistor (FET) devices. For example, a semiconductor device includes first and second vertical FET devices, and a capacitor device, formed in different device regions of a substrate. A gate electrode of the first FET device and a first capacitor electrode of the capacitor device are patterned from a same first layer of conductive material. A gate electrode of the second FET device and a second capacitor electrode of the capacitor device are patterned from a same second layer of conductive material. A gate dielectric layer of the second FET device and a capacitor insulator layer of the capacitor device are formed from a same layer of dielectric material.

Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.

Abstract: A memory cell comprises first, second, third, and fourth transistors individually comprising a transistor gate. First and second ferroelectric capacitors individually have one capacitor electrode elevationally between the transistor gates of the first, second, third, and fourth transistors. Other memory cells are disclosed, as are arrays of memory cells.

Abstract: Method and structure of forming a vertical FET. The method includes depositing a bottom source-drain layer over a substrate; depositing a first heterostructure layer over the bottom source-drain layer; depositing a channel layer over the first heterostructure layer; depositing a second heterostructure layer over the channel layer; forming a first fin having a hard mask; recessing the first and the second heterostructure layers to narrow them; filling gaps with an inner spacer; laterally trimming the channel layer to a narrower width; depositing a bottom outer spacer over the bottom source-drain layer; depositing a high-k layer on the bottom outer spacer, the first fin, and the hard mask; and depositing a metal gate layer over the high-k and top outer spacer to produce the vertical FET. Forming another structure by recessing the metal gate layer below the second inner spacer.

Abstract: A field effect device includes a semiconductor body separating a source and a drain, both source and drain coupled to the semiconductor body. An insulated control gate is located over the semiconductor body between the source and drain and configured to control a conductive channel extending between the source and drain. First and second doped regions such as highly-doped regions are adjacent to the source. The first or second doped region may be a cathode short region electrically coupled to the source. The cathode short region may be used in a bidirectional power MOSFET.

Abstract: A semiconductor device includes a semiconductor fin that extends from a first source/drain to an opposing second source/drain. The semiconductor fin includes a channel region between the first and second source/drains. The semiconductor device further includes a spacer having an upper surface having the second source/drain formed thereon, and a gate structure a gate structure wrapping around the channel region. The gate structure includes a tapered portion that contacts the spacer.

Abstract: On a front surface side of an n? semiconductor substrate, an emitter electrode and trench gates each including a p base layer, a trench, a gate oxide film and a gate electrode are provided in an IGBT region and a FWD region. Among p base layers each between adjacent trenches, p base layers having an n+ emitter region are the IGBT emitter region and the p base layers not having the n+ emitter region are the FWD anode region. A lateral width of an n+ cathode region is narrower than a lateral width of the FWD anode region. A difference of a lateral width of the FWD anode region and a lateral width of the n+ cathode region is 50 ?m or more. Thus, a semiconductor device may be provided that reduces the forward voltage drop while suppressing waveform oscillation during reverse recovery and having soft recover characteristics.

Abstract: In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.

Abstract: In general, according to one embodiment, a semiconductor device includes a first electrode, a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the first conductivity type in this order. A device region includes a gate electrode inside a first trench. A second trench having a ring-shaped structure forms a first region penetrating through the fourth and third semiconductor layers to the second semiconductor layer and including the device region inside and a second region surrounding the first region outside. A first opening is provided between adjacent ones of the first trenches. A second opening having a wider width than the first opening is provided in the first region outside the device region. A second electrode is electrically connected to the third and fourth semiconductor layers through the first and second openings.