Abstract: An integrated circuit on a substrate includes a peripheral portion that surrounds an active area and is positioned close to a scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in the peripheral portion on different planes of metallizations starting from the substrate and forms an integrated antenna. Magnetic trench structures are provided adjacent the integrated antenna.

Abstract: A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.

Abstract: A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together.

Abstract: A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator.

Abstract: Some embodiments of the present disclosure provide a semiconductor device including a substrate and a gate structure on the substrate. A first well region of a first conductivity type is in the substrate, close to a first sidewall of the gate structure. A second well region of a second conductivity type is also in the substrate close to the second sidewall of the gate structure. A conductive region is disposed in the second well region. The conductive region can be an epitaxy region. A chemical composition inside the second well region between the conductive region and the gate structure is essentially homogeneous as a chemical composition throughout the second well region.

Abstract: In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are in Ohmic contact with the drain metallization. The first p-type pillar regions are in Ohmic contact with the source metallization. An integrated dopant concentration of the first n-type pillar regions substantially matches that of the first p-type pillar regions. A second p-type pillar region is in Ohmic contact with the source metallization, arranged in the peripheral area and has an integrated dopant concentration smaller than that of the first p-type pillar regions divided by a number of the first p-type pillar regions. A second n-type pillar region is arranged between the second p-type pillar region and the first p-type pillar regions, and has an integrated dopant concentration smaller than that of the first n-type pillar regions divided by a number of the first n-type pillar regions.

Abstract: A super junction semiconductor device includes a semiconductor portion including mesa regions protruding from a base section and spatially separated in a lateral direction parallel to a first surface of the semiconductor portion, and a compensation structure covering at least sidewalls of the mesa regions. The compensation structure includes at least two first compensation layers of a first conductivity type, at least two second compensation layers of a complementary second conductivity type, and at least one interdiffusion layer between one of the first and one of the second compensation layers.

Abstract: A semiconductor structure includes a semiconductor substrate, a first doped region, a second doped region and a dielectric. The first doped region and the second doped region respectively has an aspect ratio and a dopant concentration uniformity along a depth in the semiconductor substrate. The dielectric is between the first doped region and the second doped region. The dopant concentration uniformity is within 0.2% and the aspect ratio of the semiconductor substrate is greater than about 10.

Abstract: A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad. The capacitive component region is an insulating film interposed between polysilicon layers. Specifically, a first insulating film, a polysilicon conductive layer, and a second insulating film are sequentially formed on a first main surface of a semiconductor substrate, and the temperature detecting diode, the protective diode, the anode metal wiring line, or the cathode metal wiring line is formed on the upper surface of the second insulating film. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode or the protective diode.

Abstract: An integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin protruding above the insulation regions. The insulation regions have a first portion and a second portion, with the first portion and the second portion on opposite sides of the semiconductor fin. The semiconductor fin has a first height. The integrated circuit device further includes a gate stack over a middle portion of the semiconductor fin, and a fin spacer on a sidewall of an end portion of the semiconductor fin. The fin spacer has a second height. The first height is greater than about two times the second height.

Abstract: A radio frequency LDMOS device, wherein the drift region includes a first injection region and a second injection region; the first injection region situated between a second lateral surface of a polysilicon gate and a second lateral surface of a first Faraday shielding layer; the second injection region situated between the second lateral surface of the first Faraday shielding layer and the drain region and encloses the drain region; the second lateral surface of the second Faraday shielding layer is a surface of a side near the drain region, the maximum electric field strength of the drift region on the bottom of the second lateral surface of the second Faraday shielding layer is regulated via regulation of the doping concentration of the second injection region; the doping concentration of the first injection region is higher than the second injection region.

Abstract: A semiconductor device includes: semiconductor layer having an impurity region of a first conductivity type; a gate insulating layer, at least a part of the gate insulating layer positioned on the semiconductor layer; a gate electrode positioned on the gate insulating layer and having a first surface in contact with the part of the gate insulating film and a second surface opposite to the first surface; an interlayer insulating layer covering the gate electrode; and an electrode in contact with the impurity region. The gate electrode has a recess at a corner in contact with the second surface, in a cross section of the gate electrode perpendicular to a surface of the semiconductor layer. A cavity surrounded by the gate electrode and the interlayer insulating layer is positioned in a region including at least a part of the recess.

Abstract: A semiconductor device includes first to third semiconductor regions, first to fourth electrodes and a first insulating film. The first insulating film is provided between the third electrode and the first semiconductor region, between the third electrode and the second semiconductor region, between the third electrode and the third semiconductor region, and between the fourth electrode and the first semiconductor region. The first insulating film has a first insulating region, a second insulating region and a third insulating region. A first width in the first insulating region is different from a second width in the second insulating region. The first insulating region and the second insulating region are arranged in the direction. A third width of the third insulating region is constant along the second direction.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, a plurality of first regions that are spaced apart from each other along a first direction by portions of the semiconductor layer, each of the first regions including a first semiconductor region of a second conductivity type, a second region between the first regions in the first direction, the second region including a second semiconductor region of the first conductivity type and a first insulator between the second semiconductor region and the semiconductor layer, and a third region between the first region and the second region, the third region including a third semiconductor region of the first conductivity type and a second insulator.

Abstract: A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer. The first semiconductor layer is arranged between the first surface and the second semiconductor layer.

Abstract: A DMOS transistor integrates a trench Schottky diode into the body contact of the transistor where the body region surrounding the Schottky metal layer forms a guard ring for the Schottky diode.

Abstract: A method of fabricating a Fin field effect transistor (FinFET) includes providing a substrate having a first fin and a second fin extending above a substrate top surface, wherein the first fin has a top surface and sidewalls and the second fin has a top surface and sidewalls. The method includes forming an insulation layer between the first and second fins. The method includes forming a first gate dielectric having a first thickness covering the top surface and sidewalls of the first fin using a plasma doping process. The method includes forming a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness. The method includes forming a conductive gate strip traversing over both the first gate dielectric and the second gate dielectric.

Abstract: Disclosed is a technique capable of reducing loss at the time of switching in a diode. A diode disclosed in the present specification includes a cathode electrode, a cathode region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, an anode region made of a second conductivity type semiconductor, an anode electrode made of metal, a barrier region formed between the drift region and the anode region and made of a first conductivity type semiconductor having a concentration higher than that of the drift region, and a pillar region formed so as to connect the barrier region to the anode electrode and made of a first conductivity type semiconductor having a concentration higher than that of the barrier region. The pillar region and the anode are connected through a Schottky junction.

Abstract: A touch screen panel for display apparatus is provided, which includes a substrate; an electrode forming part including a plurality of first electrode serials and a plurality of second electrode serials arranged to cross over the plurality of first electrode serials; a routing wire forming part including a plurality of first routing wires connected to the plurality of first electrode serials, respectively and a plurality of second routing wires connected to the plurality of second electrode serials, respectively; a plurality of first insulation patterns formed at a cross region of the first and second electrode serials to insulate the first electrode serial from the second electrode serial; and at least one buffer pattern to be positioned at least one side of each of the first insulation patterns, and be spaced at a predetermined distance from the first insulation pattern.

Abstract: A vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are positioned adjacent respective sidewalls of the semiconductor substrate. A dielectric material separates the gate electrodes from the source and drain regions.

Abstract: An integrated device has: a structural layer of semiconductor material doped with a first conductivity type and having a top surface defining a plane; a functional region, doped with a second conductivity type, arranged in an active area of the structural layer at the top surface, in the proximity of an edge area of the integrated device, which externally surrounds the active area; and an edge termination region, doped with the second conductivity type, joined to the functional region and arranged in the edge area. The edge termination region has a doping profile and a junction depth that vary in a first direction parallel to the plane.

Abstract: A MOS semiconductor device of a vertical type has: a functional layer, having a first type of conductivity; gate structures, which are formed above the functional layer and have a region of dielectric material and an electrode region; body wells, which have a second type of conductivity, are formed within the functional layer, and are separated by a surface separation region; source regions, which have the first type of conductivity and are formed within the body wells. Each gate structure extends laterally above just one respective body well and does not overlap the surface separation region of the functional layer. The device may further have: at least one shield structure, arranged between adjacent gate structures above the surface separation region; and/or at least one doped control region, having the second type of conductivity, arranged within the surface separation region, which are both set at the source potential.

Abstract: A semiconductor device according to the present invention includes a semiconductor layer provided with a gate trench, a first conductivity type source region formed to be exposed on a surface side of the semiconductor layer, a second conductivity type channel region formed on a side of the source region closer to a back surface of the semiconductor layer to be in contact with the source region, a first conductivity type drain region formed on a side of the channel region closer to the back surface of the semiconductor layer to be in contact with the channel region, a gate insulating film formed on an inner surface of the gate trench, and a gate electrode embedded inside the gate insulating film in the gate trench, while the channel region includes a channel portion formed along the side surface of the gate trench so that a channel is formed in operation and a projection projecting from an end portion of the channel portion closer to the back surface of the semiconductor layer toward the back surface.

Abstract: A nanotube-based flexible field effect transistor and its method of manufacture is provided. The field effect transistor according to the invention comprises at least two contact electrodes, respectively drain and source electrodes, an electrical conduction zone connected to the contact electrodes, said zone comprising a plurality of single-wall carbon nanotubes that are substantially aligned, a gate electrode for controlling the electric current circulating in said zone and a flexible substrate on which the contact and gate electrodes are deposited. The nanotube density in the conduction zone is strictly greater than 10 nanotubes per micrometer.

Abstract: In accordance with one component, a power field effect transistor is proposed, including a substrate, a channel, a gate electrode, and a gate insulator. The gate insulator is arranged at least partly between the gate electrode and the channel and includes a material having a hysteresis with respect to its polarization, such that a switching state of the transistor produced by a voltage applied to the gate electrode is maintained after the voltage has been switched off. Furthermore, a half-bridge circuit is proposed, including a high-side transistor in accordance with the construction according to the disclosure, and a low-side transistor, and also methods and circuits for driving.

Abstract: A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together.

Abstract: A semiconductor device capable of ensuring a withstand voltage of a transistor and reducing a forward voltage of a Schottky barrier diode in a package with the transistor and the Schottky barrier diode formed on chip, and a semiconductor package formed by a resin package covering the semiconductor device are provided. The semiconductor device 1 includes a semiconductor layer 22, a transistor area D formed on the semiconductor layer 22 and constituting the transistor 11, and a diode area C formed on the semiconductor layer 22 and constituting the Schottky barrier diode 10. The semiconductor layer 22 in the diode area C is thinner than the semiconductor layer 22 in the transistor area D.

Abstract: The trench has, in a cross-sectional view, a first corner portion which is an intersection between a first sidewall surface and a bottom portion and a second corner portion which is an intersection between a second sidewall surface and the bottom portion. A first layer has a second-conductivity-type region. In a cross-sectional view, the second-conductivity-type region is arranged to intersect with a line which passes through any of the first corner portion and the second corner portion and is in parallel to a <0001> direction of a silicon carbide crystal forming the silicon carbide layer. A ratio calculated by dividing SP by ST is not lower than 20% and not higher than 130%, where ST represents a total area of the trenches in a boundary surface between the first layer and a second layer and SP represents a total area of the second-conductivity-type regions in a plan view.

Abstract: A diode is provided which includes at least one diode element which has a plurality of N-type regions and a plurality of P-type regions, the N-type regions and the P-type regions being alternately arranged in series to form PN junctions, and an insulated substrate which has electric insulation. The N-type regions and the P-type regions are formed on the insulated substrate.

Abstract: There is provided a super junction semiconductor device. The super junction semiconductor device includes a cell area and a junction termination area disposed on a substrate, and a transition area disposed between the cell area and the junction termination area, and the cell area, the junction termination area, and the transition area each include one or more unit cells comprising a N-type pillar region and a P-type pillar region among a plurality of N-type pillar regions and a P-type pillar regions that are alternated between the cell area and the junction termination area.

Abstract: A power element and a temperature sensing element are formed on the same semiconductor substrate, and one end of a PN junction of the temperature sensing element is connected to a ground potential (VSS) or a power supply potential (VDD) through an intermediation of a resistor. A sum of a potential difference between both ends of the PN junction and a potential difference between both ends of the resistor is used as a temperature detection signal. The temperature sensing element can thus be formed in a recess formed in the power element while avoiding latch-up.

Abstract: A semiconductor device comprising a substrate, an base layer disposed on the substrate having a thickness C in first area and a thickness B in a second area and a hole extending to the substrate filled with semiconductor, a first semiconductor fin disposed on the first area and having a height A, and a second semiconductor fin disposed on the second area and having a height D, wherein (A+C)=(B+D).

Abstract: A tunneling field-effect transistor (TFET) device includes a source region, a gate stack, and a drain region. The TFET device further includes a source contact on the source region, a plurality of gate contacts on a planar portion of the gate stack, and a plurality of drain contacts on the drain region. The gate contacts are aligned on a first plurality of lines that intersect at a common point on the source region from a top view. The drain contacts are aligned on a second plurality of lines that intersect at the common point from the top view.

Abstract: In one general aspect, an apparatus can include a semiconductor region including a silicon carbide material and a junction termination extension implant region disposed in the semiconductor region. The apparatus can include a low interface state density portion of a dielectric layer having at least a portion in contact with the junction termination extension implant region.

Abstract: A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P?45?0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.

Abstract: A vertical high voltage semiconductor apparatus includes a first conductivity semiconductor substrate; a first conductivity semiconductor layer disposed on the semiconductor substrate and having an impurity concentration lower than the semiconductor substrate; a second conductivity semiconductor layer disposed on the first conductivity semiconductor layer; a second conductivity base layer disposed on the first conductivity semiconductor layer and the second conductivity semiconductor layer and, having an impurity concentration lower than the second conductivity semiconductor layer; and a first conductivity source region selectively disposed inside the base layer.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type. A first conductivity type epitaxial layer disposed on a top surface of the substrate includes a surface shielded region above a less heavily doped voltage blocking region. A body region of a second conductivity type opposite the first conductivity type is disposed near a top surface of the surface shielded region. A first conductivity type source region is disposed near the top surface inside the body region. A drain is disposed at a bottom surface of the substrate. A gate overlaps portions of the source and body regions. Gate insulation separates the gate from the source and body regions. First and second trenches formed in the surface shielded region are lined with trench insulation material and filled with electrically conductive trench filling material. Second conductivity type buried doped regions are positioned below the first and second trenches, respectively.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and formed in the substrate, a source well having the first conductivity type and formed in the high-voltage well, a source region formed in the source well, an isolation layer formed above the high-voltage well and spaced apart from the source well, a gate layer formed above the substrate and continuously extending from above an edge portion of the source well to an edge portion of the isolation layer, and a metal layer formed above the substrate and the isolation layer. The metal layer includes a first metal portion overlapping an edge portion of the gate layer and a side portion of the isolation layer, a second metal portion overlapping and conductively contacting the gate layer, and a third metal portion overlapping and conductively contacting the source region.

Abstract: The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method.

Abstract: A semiconductor device has emitter regions disposed in at least one cell region in a first inter-trench region, not disposed in a middle inter-trench region, and disposed in at least one cell region in the second inter-trench region. Each of the emitter regions is disposed at a position that is not in contact with first trenches but is in contact with two second trenches defining the corresponding cell region.

Abstract: The power supply unit includes a lead secondary battery (first battery) that is capable of being charged with power generated by an alternator (power generator); a lithium secondary battery (second battery) that is electrically connected in parallel to the lead secondary battery, capable of being charged with power generated by the alternator (power generator), and has higher output density or higher energy density than the lead secondary battery; and a switching means that is electrically connected between the alternator and the lead secondary battery, and the lithium secondary battery, and switches between conduction and blocking. The switching means is configured by a plurality of MOS-FETs (semiconductor switches) being connected in series such that respective parasitic diodes present in the semiconductor switches face opposite directions.

Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.

Abstract: A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first work function.

Abstract: A silicon carbide semiconductor device that reduces an influence of an off-angle of a silicon carbide substrate on characteristics of the semiconductor device and achieves improved operational stability and reduced resistance. In a trench-gate silicon carbide MOSFET semiconductor device, a high-concentration well region is formed in a well region, and a distance from a first sidewall surface of a trench of the silicon carbide semiconductor to the high-concentration well region is smaller than a distance from a second sidewall surface of the trench to the high-concentration well region, the second sidewall surface facing the first sidewall surface of the trench through the gate electrode.

Abstract: A method for preventing epitaxial growth in a semiconductor device is described. The method includes cutting the fins of FinFET structure to form a set of exposed fin ends. A set of sidewall spacers are formed on the set of exposed fin ends, forming a set of spacer covered fin ends. The set of sidewall spacers prevent epitaxial growth at the set of spacer covered fin ends. A semiconductor device includes a set of fin structures having a set of fin ends. A set of inhibitory layers are disposed at the set of fin ends to inhibit excessive epitaxial growth at the fin ends.

Abstract: A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first work function.

Abstract: A semiconductor device includes a graphene interconnect, an insulation film formed on the graphene interconnect, and a via conducting portion formed in a via hole provided in the graphene interconnect and the insulation film. The graphene interconnect has a region containing an impurity at least around the via hole.

Abstract: An integrated circuit (IC) includes a high-voltage (HV) MOSFET on a substrate. The substrate includes a handle substrate region, an insulating region, and a silicon region. Source region and drain regions, which have a first conductivity type, are disposed in the silicon region and spaced apart from one another. A gate electrode is disposed over an upper region of the silicon region and is arranged between the source and drain regions. A body region, which has a second conductivity type, is arranged under the gate electrode and separates the source and drain regions. A lateral drain extension region, which has the first conductivity type, is disposed in the upper region of the silicon region and extends laterally between the body and drain regions. A breakdown voltage enhancing region, which has the second conductivity type, is disposed in the silicon region under the lateral drain extension region.

Abstract: A method for processing a carrier may include: forming a plurality of structure elements at least one of over and in a carrier, wherein at least two adjacent structure elements of the plurality of structure elements have a first distance between each other; depositing a first layer over the plurality of structure elements having a thickness which equals the first distance between the at least two adjacent structure elements; forming at least one additional layer over the first layer, wherein the at least one additional layer covers an exposed surface of the first layer; removing a portion of the at least one additional layer to expose the first layer partially; and partially removing the first layer, wherein at least one sidewall of the at least two adjacent structure elements is partially exposed.

Abstract: A method of manufacturing super junction for semiconductor device is disclosed. The super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.