Abstract: A semiconductor device is characterized by comprising a semiconductor substrate, a first insuring film formed on the semiconductor substrate, a plurality of cell transistors each having a control gate formed on the semiconductor substrate through the first insulating film, a second insulating film formed on upper and side surfaces of the control gate, and a conductive film formed on at least the side surface of the control gate through the second insulating film.

Abstract: Low capacitance, low threshold voltage annular MOSFET transistors are disclosed. Both low junction capacitance and low threshold voltage are achieved without degradation of drain current due to application of back-bias to the substrate upon which the transistor is formed. A polysilicon annulus, rather than the drain region, abuts field oxide regions, thereby preventing junction capacitance at interface of field oxide and drain (or source). Annular MOSFETs can be fabricated using conventional CMOS processing technology.

Abstract: An improved FET device in which the hot carrier immunity and current driving capability are improved, and the subthreshold leakage current is minimized. The device has a gate electrode with vertical sidewalls, and a thin layer of SiO.sub.2 over the electrode. A first polysilicon spacer is provided on the vertical sidewalls, with a second overlying oxide spacer over the first spacer. The top portion of the SiO.sub.2 layer between the gate electrode and the polysilicon spacer is made conductive enough to keep the gate electrode and the polysilicon spacer at the same potential. Lightly doped source and drain regions are provided.

Abstract: A gate oxide film is formed on the surface of a P-type silicon substrate. A gate electrode is formed on the gate oxide film. Phosphorus is ion-implanted into the P-type silicon substrate, using the gate electrode as a mask. Thus, N.sup.- -type layers of LDD regions are formed in the P-type silicon substrate. Sidewall regions of material having a high dielectric constant are formed on both sides of the gate electrode. The P-type silicon substrate is etched downward adjacent to both the sidewall regions. N.sup.+ -type layers of source and drain regions are formed in the etched surface of the P-type silicon substrate.

Abstract: A new surface counter-doped lightly doped source and drain integrated circuit field effect transistor device is described. A gate silicon oxide layer is formed on the silicon substrate. A layer of polysilicon is deposited over the gate silicon oxide layer and etched to form a gate electrode structure. A first ion implantation is performed at a tilt angle to form lightly doped drain regions in the semiconductor substrate wherein the lightly doped drain regions are partially overlapped by the gate electrode structure. A second ion implantation is performed at a larger tilt angle and lower energy than the first ion implantation wherein the second ion implantation counter-dopes the surface of the lightly doped drain regions to form a very lightly doped drain layer thus making the lightly doped drain regions buried regions.

Abstract: A high-resistant p-silicon layer is formed on a silicon substrate through a silicon oxide film. N-source and n-drain layers are selectively formed in the surface of the high-resistant p-silicon layer. A gate electrode is formed through a gate insulating film on a channel region between the source and drain layers. To induce an n-inverted layer under the gate electrode, a p-base layer is formed in the high-resistant p-silicon layer. A depletion layer extending from a pn junction between the n-drain layer and the high-resistant p-silicon layer reaches the silicon oxide film in a thermal equilibrium state. Part of the high-resistant p-silicon layer extends into a channel region between the drain and base layers. The drain and base layers are connected to each other through part of the depletion layer in the thermal equilibrium state. A field effect transistor having a high-speed operation is provided.

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.3 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Abstract: The present invention provides a gate buffer region between a gate shield region and active cells of a power device. This gate buffer region may, for example, be a relatively narrow, strip-like doped region which extends into an epitaxial layer from an upper surface of the epitaxial layer. The gate shield region is connected to a source electrode of the power device via a relatively high impedance connection. The gate buffer region, on the other hand, is connected to the source electrode with a relatively low impedance connection. This relatively low impedance connection may, for example, be a substantially direct metallized connection from a metal source electrode to the gate buffer region at the surface of the epitaxial layer.

Abstract: The present invention is directed to a charge transfer device formed on a semiconductor substrate which comprises a channel region formed on the semiconductor substrate, at least a set of transfer gate electrodes formed adjacent to each other and insulated from each other, the set of transfer gate electrode formed over the channel region through an insulating film, clock means for providing the transfer gate electrode with multiple clock pulses, and a plurality of resistors provided between each of the transfer gate electrodes and the clock means, the resistors having respective values corresponding to capacitances of the transfer gate electrodes. Therefore, a transfer efficiency of signal charges can be improved without reducing a maximum amount of signal charges handled by a vertical register.

Abstract: The present application is directed to an improved arrangement for a thin silicon SOI transistor having improved source-high performance especially for bridge type circuits. This structure prevents forward current saturation during such source-high operations, and is made by forming the laterally extending silicon layer with a region of thinner thickness over 1/3 to 2/3 of the length of the drift region, or the lateral linear doping region. The field plate is formed with a separation from the gate electrode, and only extends over the thinned portion of the drift region. The gate electrode and field plate are short-circuited by a metal interconnect.

Abstract: A field effect transistor, FET, (11) having a gate dielectric of varying thickness (14, 24) to improve device performance. The FET (11) is made on a substrate (10) and has a control electrode, or gate (16), and two current electrodes, or source and drain regions (28), which are separated by a channel region. The gate (16) is separated from the channel region by a gate dielectric. The gate dielectric has a centrally located first region that is of a first thickness (14) and a second region which is adjacent a perimeter of the first region that is of a second thickness (24). The second thickness (24) is made greater than the first thickness (14).

Abstract: A metal-oxide-semiconductor (MOS) device designed to achieve reduced gate-to-drain capacitance is disclosed. The device has gate-electrode layer consisting of alternating polarity regions, such that regions of the gate-electrode layer not involved in channel operations have a conductivity type different from the conductivity type of the gate-electrode-layer regions actually involved in channel operations. Since the alternating conductivity regions form a capacitance in series to the gate-to-drain capacitance, the gate-to-drain capacitance of the device is reduced. An embodiment of the invention also incorporates increased-thickness regions of the gate-oxide film, which regions are disposed over semiconductor areas at which no channel operation occurs.

Abstract: Disclosed is an LDDMOSFET, in which a gate electrode (2) having a cross-sectional shape having a lower side and an upper side longer than the upper side is formed of only conductive materials, and diffusion layers (5b, 6b) of low concentration and high concentration constituting a drain are both formed so as to be overlapped with portions below the gate electrode (2) utilizing the shape of this gate electrode (2). Since the gate electrode (2) is formed of only the conductive materials, it becomes easy to word the gate electrode (2) so as to be in a desired shape. Since the diffusion layers (5b, 6b) of low concentration and high concentration constituting the drain are both overlapped with the portions below the gate electrode (2), the performance as a transistor is not degraded even if the polarity of the surface of the diffusion layer (5b, 6b) of low concentration is inverted by the effect of hot electrons.