With Means (other Than Self-alignment Of The Gate Electrode) To Decrease Gate Capacitance (e.g., Shield Electrode) Patents (Class 257/340)
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Patent number: 6696354Abstract: A method of forming a salicide. A metal layer is formed on a silicon-based substrate comprising a gate with a spacer on the side wall of the gate and a source/drain is provided. Next, a first thermal treatment is performed to make the portions of the metal layer react with the silicon in the gate and the source/drain to form a salicide. Then, any unreacted metal and the spacer are removed. An ion containing silicon is introduced into the source/drain. Finally, a second thermal treatment is performed.Type: GrantFiled: April 25, 2002Date of Patent: February 24, 2004Assignee: Silicon Integrated Systems Corp.Inventor: Chao-Yuan Huang
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Patent number: 6690062Abstract: The switching behavior of a transistor configuration is improved by providing a shielding electrode in an edge region. The shielding electrode surrounds at least sections of an active cell array. The capacitance between an edge gate structure and a drain zone and hence the gate-drain capacitance CGD of the transistor configuration is reduced by the shielding electrode located in the edge region.Type: GrantFiled: March 19, 2003Date of Patent: February 10, 2004Assignee: Infineon Technologies AGInventors: Ralf Henninger, Franz Hirler, Joachim Krumrey, Walter Rieger, Martin Poelzl
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Publication number: 20040021175Abstract: A field effect transistor includes a drain region (12) having a first portion (18) and a second portion (20), with the second portion being more lightly doped than the first portion. A channel region (14) is adjacent to the second portion and a drain electrode (24) overlies the drain region. A gate electrode (16) overlies the channel region. A shield structure (30) overlies the drain region and has a first section (32) at a first distance (33) from a semiconductor substrate (10) and a second section (34) at a second distance (35) from the semiconductor substrate, the second distance being greater than the first distance. In a particular embodiment the FET includes a shield structure wherein the first and second sections are physically separate. The location of these shield sections may be varied within the FET, and the potential of each section may be independently controlled.Type: ApplicationFiled: July 31, 2002Publication date: February 5, 2004Applicant: Motorola, Inc.Inventor: Helmut Brech
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Publication number: 20030178675Abstract: A method of manufacturing a semiconductor device include a step of forming an insulating layer, which is obtained by building up a first oxide film, a nitride film and a second oxide film on a substrate in the order mentioned, and a Salicide step of forming a Salicide-structure gate electrode on the insulating film. A silicidation reaction between the substrate surface and an N+ diffusion region is prevented in the Salicide step by causing the insulating layer to remain even in a region on the substrate besides that immediately underlying the gate electrode.Type: ApplicationFiled: March 12, 2003Publication date: September 25, 2003Inventors: Teiichiro Nishizaka, Toshikatsu Jinbo, Takaki Kohno
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Publication number: 20030178676Abstract: The switching behavior of a transistor configuration is improved by providing a shielding electrode in an edge region. The shielding electrode surrounds at least sections of an active cell array. The capacitance between an edge gate structure and a drain zone and hence the gate-drain capacitance CGD of the transistor configuration is reduced by the shielding electrode located in the edge region.Type: ApplicationFiled: March 19, 2003Publication date: September 25, 2003Inventors: Ralf Henninger, Franz Hirler, Joachim Krumrey, Walter Rieger, Martin Poelzl
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Publication number: 20030146472Abstract: A method and apparatus thereof for fabricating an integrated circuit on a laminate having a gate electrode layer over a silicon dioxide layer. Detection of the gate etch endpoint signal is improved by maximizing the use of a faster etching dopant material (e.g., n-type dopant) and minimizing the use of a slower etching dopant material (e.g., p-type dopant) in the gate electrode layer. In one embodiment, a first portion of the gate electrode layer, substantially corresponding only to the location at which a gate is to be formed, is doped with the slower etching dopant material. The remaining portion of the gate electrode layer is doped with the faster etching dopant material; thus, more of the gate electrode layer is doped with the faster etching dopant material than with the slower etching dopant material. A gate mask is aligned over the gate electrode layer, and the unmasked portions of the gate electrode layer are removed using an etchant.Type: ApplicationFiled: February 11, 2003Publication date: August 7, 2003Inventors: Calvin Todd Gabriel, Tammy D. Zheng, Emmanuel de Muizon, Linda A. Leard
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Patent number: 6600200Abstract: A MOS transistor and a method for fabricating the same include producing a well doped by a first conductivity type in a semiconductor substrate. An epitaxial layer having a dopant concentration of less than 1017 cm−3 is disposed on a surface of the doped well. Source/drain regions doped by a second conductivity type, opposite to the first conductivity type, and a channel region, are disposed in the epitaxial layer, and their depth is less than or equal to the thickness of the epitaxial layer. A method for fabricating two complementary MOS transistors is also provided.Type: GrantFiled: August 25, 2000Date of Patent: July 29, 2003Assignee: Infineon Technologies AGInventors: Bernhard Lustig, Herbert Schäfer, Lothar Risch
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Patent number: 6597053Abstract: An integrated circuit arrangement having a number of structural elements, at least one of which is surrounded by a metallic shielding structure. This structural element is thus protected against interference due to disturbing impulses from its environment. In particular, the structural elements of the circuit arrangement can be arranged next to or on top of one another. To produce the metallic shielding structure of a structural element of the circuit arrangement, at least one depression which surrounds the structural element is created and then lined with metal. The contacts and electrical connections of the structural element are electrically insulated from the metal of the shielding structure.Type: GrantFiled: October 15, 1999Date of Patent: July 22, 2003Assignee: Siemens AktiengesellschaftInventors: Anton Anthofer, Holger Hübner
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Patent number: 6593621Abstract: A lateral DMOS transistor incorporates one or more enhancement schemes for improving the breakdown voltage characteristics and ruggedness of the transistor. In one embodiment, the drain region of the lateral DMOS transistor is separated from the body region by a first distance in the rectilinear region necessary to achieve a first breakdown voltage, and separated by a second distance in the curved region necessary to achieve at least the first breakdown voltage, the second distance being greater than the first distance. In another embodiment, the gate partially overlies the field oxide region by a third distance in the rectilinear region and by a fourth distance in the curved region, the fourth distance being greater than the third distance. The enhancement schemes optimize the breakdown voltage characteristics and ruggedness of the lateral DMOS transistor in both the rectilinear and curved regions.Type: GrantFiled: August 23, 2001Date of Patent: July 15, 2003Assignee: Micrel, Inc.Inventors: Hideaki Tsuchiko, Bruce Lee Inn, Marty Garnett, Phillip Fischer
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Patent number: 6580123Abstract: A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low RDSON and increased VDSMAX and VGSMAX and a reduced Miller capacitance. The walls of the trench are first lined with nitride to permit the growth of the thick bottom oxide to, for example 1000 Å to 1400 Å and the nitride is subsequently removed and a thin oxide, for example 320 Å is regrown on the side walls. In another embodiment, the trench bottom in amorphized and the trench walls are left as single crystal silicon so that oxide can be grown much faster and thicker on the trench bottom than on the trench walls during an oxide growth step. A reduced channel length of about 0.7 microns is used. The source diffusion is made deeper than the implant damage depth so that the full 0.7 micron channel is along undamaged silicon.Type: GrantFiled: March 21, 2001Date of Patent: June 17, 2003Assignee: International Rectifier CorporationInventor: Naresh Thapar
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Patent number: 6534825Abstract: A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate. The gate structure includes a second portion of a second conductivity type having a polarity that is opposite a polarity of the first conductivity type, for decreasing a capacitance charge under the gate. A second structure for decreasing a capacitance under the gate includes an implant region in the semiconductor substrate between a channel region, where the implant region is doped to have a conductivity opposite the channel region.Type: GrantFiled: August 14, 2002Date of Patent: March 18, 2003Assignee: Fairchild Semiconductor CorporationInventor: Daniel S. Calafut
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Patent number: 6525397Abstract: An integrated fuse element is capable of being programmed to high resistance in low voltage process technology. The fuse includes a stack of an undoped polysilicon layer and a silicide layer. A voltage applied across the stack is increases until a first agglomeration event occurs, whereby a discontinuity is formed in the silicide layer. The current is further increased to cause a second agglomeration event whereby the size of the discontinuity is increased. Each agglomeration event increases the resistance of the fuse. An extended-drain MOS transistor, capable of sustaining high voltage, is connected in series with the fuse for programming the fuse.Type: GrantFiled: August 17, 1999Date of Patent: February 25, 2003Assignee: National Semiconductor CorporationInventors: Alexander Kalnitsky, Pavel Poplevine, Albert Bergemont
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Publication number: 20030020120Abstract: A MOSFET having a new source/drain (S!D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitance. The S/D junction depth is defined by an STI etch step (according to a first method of making the MOSFET) or a silicon etch step (according to a second method of making the MOSFET). By controlling the etch depth, a very shallow junction depth is achieved. There is a low variation of gate length, since the gate area is defined by etching crystal silicon, not by etching polycrystalline silicon. There is a low aspect ratio between the gate and the S/D, since the gate conductor and the source and drain conductors are aligned on same level. A suicide technique is applied to the source and drain for low parasitic resistance; however, this will not result in severe S/D junction leakage, since the source and drain conductors sit on the STI.Type: ApplicationFiled: July 24, 2001Publication date: January 30, 2003Applicant: Infineon Technologies North America Corp.Inventors: Qiuyi Ye, William Tonti, Yujun Li, Jack A. Mandelman
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Patent number: 6512266Abstract: Divot fill methods of incorporating thin SiO2 spacer and/or annealing caps into a complementary metal oxide semiconductor (CMOS) processing flow are provided. In accordance with the present invention, the divot fill processes provide a means for protecting the exposed surfaces of the thin SiO2 spacer and/or annealing cap such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning step. CMOS devices including thin SiO2 spacer and/or annealing caps whose surfaces are protected such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning or other process steps are also provided.Type: GrantFiled: July 11, 2001Date of Patent: January 28, 2003Assignee: International Business Machines CorporationInventors: Sadanand V. Deshpande, Bruce B. Doris, Rajarao Jammy, William H. Ma
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Patent number: 6509233Abstract: Cesium is implanted into the gate oxide layer of a vertical trench-gated MOSFET. The cesium, which is an electropositive material, reduces the threshold voltage of the device and lowers the on-resistance by improving the accumulation region adjacent the bottom of the trench.Type: GrantFiled: March 7, 2002Date of Patent: January 21, 2003Assignee: Siliconix incorporatedInventors: Mike Chang, Sik Lui, Sung-Shan Tai
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Patent number: 6509612Abstract: A method and structure for a metal oxide semiconductor field effect transistor (MOSFET) includes patterning a gate stack (having a gate conductor layer and a gate dielectric) over a substrate and modifying the gate dielectric beneath the gate conductor, such that the gate dielectric has a central portion and modified dielectric regions adjacent the central portion. The modified dielectric regions have a lower dielectric constant than that of the gate dielectric and the central portion is shorter than the gate conductor.Type: GrantFiled: May 4, 2001Date of Patent: January 21, 2003Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Louis L. Hsu, Carl J. Radens, Joseph F. Shepard, Jr.
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Patent number: 6492678Abstract: A high voltage MOS transistor with a gate extension that has a reduced electric field in the drain region near the gate is provided. The high voltage MOS transistor includes a first and second gate layers, and a dielectric layer between the gate layers. The first and second gate layers are electrically coupled together and form the gate of the transistor. The second gate layer extends over the drain of the transistor above the dielectric and gate oxide layers to form the gate extension. The high voltage MOS transistor of the present invention may be fabricated without additional processing steps in BiCMOS and CMOS processes that use dual polysilicon layers and a dielectric layer that are used to form capacitors.Type: GrantFiled: May 3, 2000Date of Patent: December 10, 2002Assignee: Linear Technology CorporationInventor: Francois Hebert
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Publication number: 20020175369Abstract: A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.Type: ApplicationFiled: May 23, 2001Publication date: November 28, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David B. Colavito, Nivo Rovedo, Phung T. Nguyen
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Publication number: 20020163039Abstract: A method and structure for a metal oxide semiconductor field effect transistor (MOSFET) includes patterning a gate stack (having a gate conductor layer and a gate dielectric) over a substrate and modifying the gate dielectric beneath the gate conductor, such that the gate dielectric has a central portion and modified dielectric regions adjacent the central portion. The modified dielectric regions have a lower dielectric constant than that of the gate dielectric and the central portion is shorter than the gate conductor.Type: ApplicationFiled: May 4, 2001Publication date: November 7, 2002Inventors: Lawrence A. Clevenger, Louis L. Hsu, Carl J. Radens, Joseph F. Shepard
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Patent number: 6452226Abstract: A non-volatile semiconductor memory device and a manufacturing method of the same where an etching residue generating short-circuit between gates is made harmless or a device is miniaturized are obtained. The method includes the steps of forming on a semiconductor substrate, a first gate layer and a second gate layer, forming a second gate electrode by etching the second gate layer, forming a first gate electrode by etching the first gate layer using the second gate electrode as a mask, and removing a residue left on a step portion by isotropic etching.Type: GrantFiled: February 23, 2001Date of Patent: September 17, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kenji Kawai, Hajime Kimura, Kazuyuki Ohmi
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Patent number: 6448611Abstract: A high power semiconductor device and its fabrication method in which source and the drain regions are spaced apart from and edge of a field oxide layer. This allows the junction profile to become gently-sloped so that the junction breakdown voltage is increased. Also, since the edge of the field oxide layer is covered by the field plate and a ground voltage or below the ground voltage is applied to the field plate, the distribution of the strong electric field formed at the edge of the field oxide layer is dispersed, to further increase the junction breakdown voltage. Moreover, since the field plate covers the field oxide layer at the side of the drain of the high power semiconductor device, when a high voltage is applied to the drain, the electric field distribution is dispersed, so that the junction breakdown voltage at the edge of the gate electrode at the side of the drain can be increased.Type: GrantFiled: June 6, 2000Date of Patent: September 10, 2002Assignee: Hynix Semiconductor, Inc.Inventor: Han-Su Oh
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Patent number: 6399987Abstract: A MOS transistor having a self-aligned well bias area and a method of fabricating the same provide for efficient application of well bias in a highly integrated semiconductor substrate without causing latch-up. The well bias area is formed at a trench, which is formed by etching a semiconductor substrate in a manner of self-alignment, so that well bias can be efficiently applied to the MOS transistor achieving reduction of the area of a chip without degradation of electrical characteristics.Type: GrantFiled: January 31, 2001Date of Patent: June 4, 2002Assignee: Samsung Electronics, Co., Ltd.Inventor: Gyu-chul Kim
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Patent number: 6399451Abstract: A semiconductor device with a gate spacer containing a conductive layer, and a manufacturing method. A first spacer insulation layer is formed on a semiconductor substrate where a gate electrode is formed. Then, the first spacer insulation layer is etched to cover the side walls of the gate electrode. A conductive spacer film is subsequently formed on the resultant structure and is over-etched to form a conductive spacer that covers the first spacer insulation layer. In this step, the gate electrode is partially consumed to make the top of the first spacer insulation layer higher than the gate electrode. Also, an upper portion of the first spacer insulation layer is not comparatively etched due to an etching selectivity. This structure avoids shorts between the conductive spacer and the gate electrode. A second spacer insulation layer is then formed on the conductive spacer.Type: GrantFiled: September 15, 1999Date of Patent: June 4, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Hoon Lim, Joo-young Kim, Sun-ha Hwang
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Patent number: 6365918Abstract: The present invention relates to a method and device for interconnecting radio frequency power SiC field effect transistors. To improve the parasitic source inductance advantage is taken of the small size of the transistors, wherein the bonding pads are placed on both sides of the die in such a way that most of the source bonding wires (6) go perpendicularly to the gate and drain bonding wires (7, 8). Multiple bonding wires can be connected to the source bonding pads, reducing the source inductance. An additional advantage comes from such arrangement by reducing the mutual inductance between source/gate and between source/drain due to the orthogonal wire placement.Type: GrantFiled: October 12, 1999Date of Patent: April 2, 2002Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Andrej Litwin, Ted Johansson
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Publication number: 20010035554Abstract: In a driving power IC including a starter circuit comprising a main-switch (MS) transistor, a starter switch (SS) for starting the MS transistor and a start resistor (or a resistor element) SR, the start resistor is created on a field insulation film. In a periphery area of a chip for integrating the driving power IC, that is, on a semiconductor substrate's surface beneath the field insulation film, field limiting rings (FLRs) are created, enclosing an active area in a multiplexed state. The resistor element is extended from a start edge on the inner side of a group of said field limiting rings to an end edge on the outer side of the group, having a zigzag shape.Type: ApplicationFiled: April 26, 2001Publication date: November 1, 2001Inventors: Shunichi Yamauchi, Yoshito Nakazawa, Yuji Yatsuda
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Patent number: 6262451Abstract: An electrode structure for semiconductor devices includes first electrode material positioned in overlying relationship to the surface of a substrate so as to define a first side wall perpendicular thereto. A nonconductive side wall spacer is formed on the first side wall and defines a second side wall parallel to and spaced from the first side wall. Second electrode material is formed in overlying relationship to the substrate and on the second side wall so as to define a third side wall parallel to and spaced from the second side wall. The first and second electrode materials are connected as first and second electrodes in a common semiconductor device. Additional electrodes can be formed by forming electrode material on additional side walls.Type: GrantFiled: March 13, 1997Date of Patent: July 17, 2001Assignee: Motorola, Inc.Inventors: Jenn-Hwa Huang, Kurt Eisenbeiser, Yang Wang, Ellen Lan
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Patent number: 6218689Abstract: The present invention provides a method and a NAND-type flash memory device. The method includes forming a select gate oxide layer in a select transistor area of a substrate and a tunnel oxide layer in a memory cell area of the substrate; forming a doped amorphous silicon layer on the select gate oxide layer and the tunnel oxide layer, the doped amorphous silicon layer having a dopant level which simultaneously avoids a select transistor word line high resistance problem and a charge gain/charge loss problem; forming an insulating layer on the doped amorphous silicon layer; forming a control gate layer on the insulating layer; and etching at least the doped amorphous silicon layer, the insulating layer, and the control gate layer to form at least one memory cell stack structure and at least one select transistor stack structure.Type: GrantFiled: August 6, 1999Date of Patent: April 17, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Kent Kuohua Chang, Kenneth Wo-Wai Au, Hao Fang
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Patent number: 6215152Abstract: A MOSFET has a buried shield plate under the gate and over the drain with the gate being formed on the periphery of the buried shield plate as a self-aligned structure with minimal or no overlap of the gate over the shield plate. Methods of fabricating the MOSFET are disclosed.Type: GrantFiled: August 5, 1998Date of Patent: April 10, 2001Assignee: CREE, Inc.Inventor: Francois Hebert
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Patent number: 6211556Abstract: A MOSFET device with buried contact structure on a semiconductor substrate has the following major elements with their relative locations. A gate insulator is on a portion of the substrate and a gate electrode is on the gate insulator. A gate sidewall structure is located on sidewalls of the gate electrode. Inside the substrate, a lightly doped source/drain region is under the gate sidewall structure, and a doped source/drain region is abutting the lightly doped source/drain region and located aside from a region under the gate sidewall structure. In addition, a doped buried contact region is also in the substrate next to the doped source/drain region. On the substrate, a silicon connection is located on a portion of the doped buried contact region, and a shielding block is on the doped buried contact region covering only a region uncovered by the silicon connection.Type: GrantFiled: June 1, 1999Date of Patent: April 3, 2001Assignee: Texas Instruments - Acer IncorporatedInventor: Shye-Lin Wu
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Patent number: 6207994Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: GrantFiled: February 5, 1999Date of Patent: March 27, 2001Assignee: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit
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Patent number: 6198131Abstract: A high voltage metal oxide semiconductor device. The high voltage device comprises a high voltage NMOS, a high voltage PMOS, or a high voltage CMOS. A field oxide layer is used to isolate the gate from the source region, while a diffusion region is formed under the field oxide layer. A channel region around the source drain extends across a first doped well and a second doped well having different dopant concentration. The channel region further comprises two grading regions with different dopant concentrations around the drain region.Type: GrantFiled: December 7, 1998Date of Patent: March 6, 2001Assignee: United Microelectronics Corp.Inventor: Ming-Tsung Tung
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Patent number: 6172400Abstract: A MOS transistor including a gate electrode on a gate oxide over a channel region between a source region and a drain region also includes a shield electrode at least partially on the gate oxide adjacent to, self-aligned with, and at least partially coplanar with the gate electrode and between the gate electrode and drain region. Placing the shield electrode on the gate oxide improves the gate-drain shielding, reduces the gate-drain capacitance, Cgd, and reduces hot electron related reliability hazard.Type: GrantFiled: August 25, 1998Date of Patent: January 9, 2001Assignee: Spectrian CorporationInventors: Sze Him Ng, Francois Hebert
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Patent number: 6137126Abstract: The capacitance between a gate electrode of a transistor and local interconnect is reduced by employing SiC sidewall spacers on the side surfaces of the gate electrode when forming the source/drain regions with shallow extensions. Embodiments include forming SiC sidewall spacers at a width of about 500 .ANG. to about 800 .ANG. having a dielectric constant of less than about 3.2, depositing a silicon oxide inter-dielectric layer, and forming the local interconnect through the inter-dielectric layer. The resulting composite dielectric constant between the gate electrode and local interconnect is about 4.2 to about 4.7.Type: GrantFiled: August 17, 1999Date of Patent: October 24, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Steven C. Avanzino, Minh Van Ngo, Angela T. Hui, Chun Jiang, Hamid Partovi
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Patent number: 6107160Abstract: Gate to drain capacitance in a lateral DMOS and vertical DMOS field effect transistor is minimized by providing a conductive shield plate under the gate and between the gate and the drain of the transistor. In operation, the shield plate is preferably connected to a DC voltage potential and coupled to AC ground for RF power applications. The shield plate is readily fabricated in a conventional polysilicon gate process by adding one additional polysilicon deposition (or other suitable material), one additional mask, and one additional etch step. The shield plate can include a raised portion which provides lateral capacitive isolation between the gate and the drain. Alternatively, a shield contact can be provided above the shield plate and between the gate and drain to provide lateral isolation.Type: GrantFiled: April 22, 1998Date of Patent: August 22, 2000Assignee: Spectrian CorporationInventors: Francois Hebert, Daniel Ng
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Patent number: 6107665Abstract: The present invention includes two transistors every output signal line connected at crosspoints of a plurality of input signal lines and a plurality of output signal lines, with a channel region of one of these transistors being implanted or diffused with an impurity so as to be normally in an active state. By then selectively making electrical connection with one of the plurality of output signal lines, the coded data cannot be easily known because the corresponding relationship of the input signal lines and the output signal lines cannot be confirmed from the wiring layout.Type: GrantFiled: March 2, 1998Date of Patent: August 22, 2000Assignee: Oki Electric Industry Co., Ltd.Inventor: Junichiro Oike
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Patent number: 6091110Abstract: A method of fabricating a MOSFET transistor and resulting structure having a drain-gate feedback capacitance shield formed in a recess between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since one additional non-critical mask is required with selective etch used to create the recess.Type: GrantFiled: October 29, 1999Date of Patent: July 18, 2000Assignee: Spectrian CorporationInventors: Francois Hebert, Szehim Ng
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Patent number: 6051861Abstract: A semiconductor device and a method of producing the same are disclosed. Cavities intervene between a gate electrode and a source and a drain region for reducing a capacitance. The cavities successfully reduce a fringe capacitance between the gate electrode and the source and drain regions. The side walls are lower in height than the gate electrode, so that the electrode protrudes upward over the top of the side walls. Insulation films are etched back in order to expose the surfaces of the gate electrode and source and drain electrodes. Thereafter, silicide is formed on the gate electrode and a substrate. This allows the gate electrode and source and drain electrodes to be wired via the silicide and thereby reduces the resistance of the device.Type: GrantFiled: March 7, 1997Date of Patent: April 18, 2000Assignee: NEC CorporationInventor: Mitsuhiro Togo
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Patent number: 6001710Abstract: A method of fabricating a MOSFET transistor and resulting structure having a drain-gate feedback capacitance shield formed in a recess between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since one additional non-critical mask is required with selective etch used to create the recess.Type: GrantFiled: March 30, 1998Date of Patent: December 14, 1999Assignee: Spectrian, Inc.Inventors: Hebert Francois, Szehim Ng
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Patent number: 6001695Abstract: First, a field oxide region, a pad oxide layer and a first nitride layer are formed on a silicon substrate, respectively. Then, a portion of the first nitride layer is removed. A first oxide layer and a nitride spacer are formed on the substrate, respectively. Portions of the first oxide layer and the pad oxide layer are removed to form a first region of the first oxide layer and a second region of the first oxide layer. Then, an ion implantation is performed to form a punch-through stopping region. Next, a second oxide layer and an amorphous-Si layer are formed on the substrate, respectively.Portions of the a-Si layer are etched back. Next, the first nitride layer and the nitride spacer are removed. An ion implantation is performed to form a source, a drain and a doped region at the bottom of the second region of the first oxide layer. Then, a Rapid Thermal Process is used to drive dopant diffusion to form an extended source/drain junction.Type: GrantFiled: March 2, 1998Date of Patent: December 14, 1999Assignee: Texas Instruments - Acer IncorporatedInventor: Shye-Lin Wu
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Patent number: 5956582Abstract: A two-terminal current limiting component, includes a substrate of a first conductivity type; separated wells of the second conductivity type; a first annular region of the first conductivity type in each well; a second annular region of the first conductivity type having a low doping level between the periphery of each first annular region and the periphery of each well; an insulating layer over the second annular region and the surface portions of the substrate; a first metallization coating the upper surface of the component; and a second metallization coating the lower surface of the component.Type: GrantFiled: June 13, 1997Date of Patent: September 21, 1999Assignee: SGS-Thomson Microelectronics S.A.Inventors: Christophe Ayela, Philippe Leturcq, Jean Jalade, Jean-Louis Sanchez
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Patent number: 5949108Abstract: A process for producing a metal oxide semiconductor (MOS transistor) is provided. The process includes the following steps. At least two trenches are formed at a surface of a first substrate. Oxide is deposited onto the at least two trenches. The at least two trenches each have a surface spaced apart from the surface of the first substrate. A second substrate is placed onto the surface of the first substrate. A layer is delaminated from the first substrate. The layer includes the at least two oxide-filled trenches and a portion of the first substrate. The layer is then bonded to a second substrate. First and second active regions are then formed, in the portion of the first substrate, overlaying the surfaces of the at least two trenches.Type: GrantFiled: June 30, 1997Date of Patent: September 7, 1999Assignee: Intel CorporationInventor: Brian S. Doyle
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Patent number: 5929482Abstract: An n.sup.+ semiconductor substrate (1) using a silicon wafer as a base material and including As includes oxygen of which the concentration is in the range of 12E17 atoms/cm.sup.3 to 20E17 atoms/cm.sup.3. The first epitaxial growth layer (2) of n type and a diffusion layer (3) of p type are formed in sequence on the second major surface (1S2) of the semiconductor substrate (1). The thickness of an epitaxial a growth layer (10) is set to be not more than 20 .mu.m. A trench (6) is formed so as to extend from a surface of the diffusion layer (3) to the inside of the first epitaxial growth layer (2). A gate oxide film (5) is formed on a bottom surface (6B) and a wall surface (6W) of the trench (6) and a conductive layer (11) fills the trench (6). An n-type source layer (4) is formed at a corner (6C) of the trench (6). After that, predetermined electrodes are formed and so on, to complete a device.Type: GrantFiled: April 16, 1998Date of Patent: July 27, 1999Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Minoru Kawakami, Mitsuhiro Yano, Yasunori Yamashita, Hidetoshi Souno
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Patent number: 5924001Abstract: A method for fabricating polycide gate electrodes wherein voids at the silicide/polysilicon interface are eliminated by ion implantation is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. A silicide layer is formed overlying the polysilicon layer. Silicon ions are implanted into the silicide layer. A hard mask layer is deposited over the silicide layer. Because of the presence of the silicon ions in the silicide layer, silicon atoms from the polysilicon layer do not diffuse into the silicide layer causing voids to form in the polysilicon layer. Therefore, the formation of silicon pits in the semiconductor substrate is prevented. The silicide, polysilicon and gate silicon oxide layers are patterned to complete fabrication of a gate electrode in the manufacture of an integrated circuit device.Type: GrantFiled: January 8, 1998Date of Patent: July 13, 1999Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chie-Ming Yang, Jih-Wha Wang, Chien-Jiun Wang, Bou Fun Chen, Liang Szuma
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Patent number: 5918137Abstract: A MOS transistor including a gate electrode on a gate oxide over a channel region between a source region and a drain region also includes a shield electrode at least partially on the gate oxide adjacent to, self-aligned with, and at least partially coplanar with the gate electrode and between the gate electrode and drain region. Placing the shield electrode on the gate oxide improves the gate-drain shielding, reduces the gate-drain capacitance, Cgd, and reduces hot electron related reliability hazard.Type: GrantFiled: April 27, 1998Date of Patent: June 29, 1999Assignee: Spectrian, Inc.Inventors: Sze Him Ng, Francois Hebert
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Patent number: 5912490Abstract: Gate to drain capacitance in a lateral DMOS and vertical DMOS field effect transistor is minimized by providing a conductive shield plate under the gate and between the gate and the drain of the transistor. In operation, the shield plate is preferably connected to a DC voltage potential and coupled to AC ground for RF power applications. The shield plate is readily fabricated in a conventional polysilicon gate process by adding one additional polysilicon deposition (or other suitable material), one additional mask, and one additional etch step. The shield plate can include a raised portion which provides lateral capacitive isolation between the gate and the drain. Alternatively, a shield contact can be provided above the shield plate and between the gate and drain to provide lateral isolation.Type: GrantFiled: August 4, 1997Date of Patent: June 15, 1999Assignee: SpectrianInventors: Francois Hebert, Daniel Ng
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Patent number: 5869866Abstract: An integrated circuit is formed whereby junctions of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD area, at least one MDD area, and a heavy concentration source/drain area. Conversely, the PMOS transistor includes an LDD area and a source/drain area. The NMOS transistor junction is formed dissimilar from the PMOS transistor junction to take into account, inter alia, the less mobile nature of the junction dopants relative to the PMOS dopants. Thus, a lessening of the LDD area and the inclusion of an MDD area provides lower source-drain resistance and higher ohmic connectivity in the NMOS device. The PMOS junction includes a relatively large LDD area so as to draw the highly mobile, heavy concentration boron atoms away from the PMOS channel.Type: GrantFiled: December 6, 1996Date of Patent: February 9, 1999Assignee: Advanced Micro Devices, Inc.Inventors: H. Jim Fulford, Jr., Mark I. Gardner, Derick J. Wristers
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Patent number: 5844274Abstract: A semiconductor device and a method of manufacturing the same provide a structure which can be easily integrated to a higher extent without providing an alignment margin taking an alignment accuracy of photolithography into consideration. In the semiconductor device, a gate electrode and a pair of source/drain electrodes are formed inside a transistor opening formed at first and second insulating films forming a flat element isolating film. Thereby, an end of the gate electrode in the width direction is defined in an aligned manner by the transistor opening in the step of forming the gate electrode so that it is not necessary to provide the alignment margin taking the alignment accuracy into consideration. This allows high integration.Type: GrantFiled: March 28, 1996Date of Patent: December 1, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Toshiaki Tsutsumi
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Patent number: 5814859Abstract: A semiconductor device includes a semiconductor substrate having an epitaxial layer surface opposite a drain contact surface; a semiconductor layer adjacent to the epitaxial layer surface of the substrate, the semiconductor layer including material of a first conductivity type; a patterned refractory dielectric layer adjacent to the semiconductor layer; a base region of implanted ions in the semiconductor layer, the base region being of a second conductivity type; a source region of implanted ions in the base region, the source region being of the first conductivity type; a gate insulator layer adjacent to at least a portion of the source and base regions of the semiconductor layer; and a gate electrode over a portion of the gate insulator layer, adjacent to and in physical contact with an outer edge of the patterned refractory dielectric layer, and over at least a portion of the base region between the source region and the patterned refractory dielectric layer.Type: GrantFiled: November 15, 1995Date of Patent: September 29, 1998Assignee: General Electric CompanyInventors: Mario Ghezzo, Tat-Sing Paul Chow, James William Kretchmer, Richard Joseph Saia, William Andrew Hennessy
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Patent number: 5814869Abstract: A Fermi-threshold field effect transistor includes spaced-apart source and drain regions which extend beyond the Fermi-tub in the depth direction and which may also extend beyond the Fermi-tub in the lateral direction. In order to compensate for the junction with the substrate, the doping density of the substrate region is raised to counteract the shared charge. Furthermore, the proximity of the source and drain regions leads to a potential leakage due to the drain field which can be compensated for by reducing the maximum tub depth compared to a low capacitance Fermi-FET and a contoured-tub Fermi-FET while still satisfying the Fermi-FET criteria. The tub depth is maintained below a maximum tub depth. Short channel effects may also be reduced by providing source and drain extension regions in the substrate, adjacent the source and drain regions and extending towards the channel regions.Type: GrantFiled: July 21, 1995Date of Patent: September 29, 1998Assignee: Thunderbird Technologies, Inc.Inventor: Michael W. Dennen
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Patent number: 5684319Abstract: A DMOS device structure, and method of manufacturing the same features a self-aligned source and body contact structure which requires no additional masks. Polysilicon spacers are used to form the source region at the periphery of the gate polysilicon. The preferred method of manufacturing uses five masks to produce a discrete DMOS semiconductor chip. An N- epitaxial layer is grown on an N+ substrate. Thick field oxide is grown. A first mask is used to etch an active region. Thin gate oxide is grown. Doped polysilicon is then deposited. A second mask is used to etch the polysilicon, thereby forming the gates. Insulating oxide is grown. A blanket P body implantation is performed. A thermal drive-in step laterally and vertically diffuses the implanted P type impurity throughout body regions. The insulating oxide is etched. A polysilicon layer is deposited and doped. A dry etch leaves polyslicon spacers along the edges of the gates.Type: GrantFiled: August 24, 1995Date of Patent: November 4, 1997Assignee: National Semiconductor CorporationInventor: Francois Hebert