Gate Electrode Overlaps The Source Or Drain By No More Than Depth Of Source Or Drain (e.g., Self-aligned Gate) Patents (Class 257/346)
  • Patent number: 10985184
    Abstract: Embodiments of the present disclosure relate to non-planar semiconductor device structures having fins. In one embodiment, a semiconductor device includes a substrate, silicon fins positioned on the substrate, and a germanium layer that is epitaxially grown on an upper region of the silicon fins with the silicon fins and the germanium layer forming a body of the semiconductor device.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Martin D. Giles, Tahir Ghani
  • Patent number: 10916651
    Abstract: A method for forming the semiconductor device that includes forming a gate opening to a channel region of a fin structure; and forming a dielectric layer on the fin structure, in which an upper portion of the fin structure is exposed. A metal is formed within the gate opening. The portions of the metal directly contacting the upper surface of fin structure provide a body contact. The combination of the metal within the gate opening to the channel region of the fin structure and the dielectric layer provide a functional gate structure to the semiconductor device.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: February 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexander Reznicek, Tak H. Ning, Jeng-Bang Yau, Bahman Hekmatshoartabari
  • Patent number: 10896965
    Abstract: A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Adra Carr, Jingyun Zhang, Choonghyun Lee, Takashi Ando, Pouya Hashemi
  • Patent number: 10749016
    Abstract: The present invention provides a preparation method for a fully-transparent thin film transistor, wherein a transparent conductive gate electrode layer of the fully-transparent thin film transistor is used as a photolithographic mask, a photoresist is exposed through a rear surface of a transparent substrate, the transparent substrate has a transmittance higher than 60% to an exposure light beam, and the transparent conductive gate electrode layer has a transmittance lower than 5% to the exposure light beam. In the preparation method for a fully-transparent thin film transistor provided by the present invention, by using a self-aligned technology, the process complexity and the feature size of the device can both be reduced.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: August 18, 2020
    Assignee: INSTITUTE OF PHYSICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Yonghui Zhang, Zengxia Mei, Huili Liang, Xiaolong Du
  • Patent number: 10665672
    Abstract: A method of fabricating a semiconductor device includes providing a substrate having a layered fin structure thereon. The layered fin structure includes base fin portion, a sacrificial portion provided on the base fin portion and a channel portion provided on the sacrificial portion. A doping source film is provided on the substrate over the layered fin structure, and diffusing doping materials from the doping source film into a portion of the layered fin structure other than the channel portion to form a diffusion doped region in the layered fin structure. An isolation material is provided on the substrate over at least the diffusion doped region of the layered fin structure.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 26, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Anton deVilliers
  • Patent number: 10629730
    Abstract: A method for forming the semiconductor device that includes forming a gate opening to a channel region of a fin structure; and forming a dielectric layer on the fin structure, in which an upper portion of the fin structure is exposed. A metal is formed within the gate opening. The portions of the metal directly contacting the upper surface of fin structure provide a body contact. The combination of the metal within the gate opening to the channel region of the fin structure and the dielectric layer provide a functional gate structure to the semiconductor device.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexander Reznicek, Tak H. Ning, Jeng-Bang Yau, Bahman Hekmatshoartabari
  • Patent number: 10546926
    Abstract: Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Devendra K. Sadana
  • Patent number: 10510848
    Abstract: Techniques are disclosed for reducing off-state leakage of fin-based transistors through the use of a sub-fin passivation layer. In some cases, the techniques include forming sacrificial fins in a bulk silicon substrate and depositing and planarizing shallow trench isolation (STI) material, removing and replacing the sacrificial silicon fins with a replacement material (e.g., SiGe or III-V material), removing at least a portion of the STI material to expose the sub-fin areas of the replacement fins, applying a passivating layer/treatment/agent to the exposed sub-fins, and re-depositing and planarizing additional STI material. Standard transistor forming processes can then be carried out to complete the transistor device. The techniques generally provide the ability to add arbitrary passivation layers for structures that are grown in STI-based trenches. The passivation layer inhibits sub-fin source-to-drain (and drain-to-source) current leakage.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: December 17, 2019
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Ying Pang, Anand S. Murthy, Tahir Ghani, Karthik Jambunathan
  • Patent number: 10490650
    Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Kai Lin, Bo-Yu Lai, Li Chun Te, Kai-Hsuan Lee, Sai-Hooi Yeong, Tien-I Bao, Wei-Ken Lin
  • Patent number: 10374086
    Abstract: A three-dimensional (3D) transistor includes a ferroelectric film between the gate and the channel. The 3D transistor can be characterized as a 3D Negative Capacitance (NC) transistor due to the negative capacitance resulting from the ferroelectric film. Performance of the transistor is optimized by manipulating the structure and/or by the selection of materials. In one example, the capacitance of the ferroelectric film (CFE) is matched to the sum of the gate capacitance (CMOS) and the gate edge capacitance (CEDGE), wherein the gate edge capacitance (CEDGE) is the capacitance at the edge of the gate and between the gate and the source and its extension, and the gate and the drain and its extension.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: August 6, 2019
    Assignee: The Regents of the University of California
    Inventor: Chenming Hu
  • Patent number: 10177143
    Abstract: A semiconductor device includes a semiconductor substrate, at least one first isolation structure, at least one second isolation structure, a source structure, a drain structure and a plurality of semiconductor fins. The first isolation structure and the second isolation structure are located on the semiconductor substrate. The source structure is located on the semiconductor substrate and the first isolation structure, in which at least one first gap is located between the source structure and the first isolation structure. The drain structure is located on the semiconductor substrate and the second isolation structure, in which at least one second gap is located between the drain structure and the second isolation structure. The semiconductor fins protrude from the semiconductor substrate, in which the semiconductor fins are spaced apart from each other, and connect the source structure and the drain structure.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chii-Horng Li, Chien-I Kuo, Lilly Su, Chien-Chang Su, Ying-Wei Li
  • Patent number: 10170485
    Abstract: A structure comprises a first channel region forming an n-channel device; a second channel region forming a p-channel device, the p-channel device being stacked with the n-channel device in a vertical orientation; a gate positioned around the stacked n-channel device and p-channel device; and at least one source region and at least one drain region extending from each of the n-channel device and the p-channel device. Each of the at least one source region and the at least one drain region within the stacked n-channel device and p-channel device are independently contacted.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Guillorn, Robert R. Robison, Reinaldo Vega, Rajasekhar Venigalla
  • Patent number: 10164062
    Abstract: The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Ru Lin, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 10128334
    Abstract: A method is disclosed wherein a gate, having a gate cap and a sacrificial gate sidewall spacer, is formed adjacent to channel region(s) of a transistor and metal plugs, having plug caps, are formed on source/drain regions. The sacrificial gate sidewall spacer is selectively etched, creating a cavity that exposes sidewalls of the gate and gate cap. Optionally, the sidewalls of the gate cap are etched back to widen the upper portion of the cavity. A dielectric spacer layer is deposited to form an air-gap gate sidewall spacer within the cavity. Since different materials are used for the plug caps, gate cap and dielectric spacer layer, a subsequently formed gate contact opening will be self-aligned to the gate. Thus, a gate contact can be formed over an active region (or close thereto) without risk of gate contact-to-metal plug shorting. A structure formed according to the method is also disclosed.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: November 13, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Emilie Bourjot, Ruilong Xie
  • Patent number: 10103243
    Abstract: A semiconductor device includes semiconductor fins formed on a substrate, gate structures formed transversely over the fins, unipolar spacers formed over the gate structures only, and source and drain regions formed between the gate structures on the fins. The fins are free from the unipolar spacers, and the unipolar spacers have a substantially uniform thickness vertically along the gate structures and include a spacer material with an etch selectivity greater than SiN for oxide removal.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: October 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu, Jie Yang
  • Patent number: 10090157
    Abstract: A semiconductor device includes one nanowire structure disposed on semiconductor substrate and extending in first direction on semiconductor substrate. Each nanowire structure includes plurality of nanowires extending along first direction and arranged in second direction, the second direction being substantially perpendicular to first direction. Each nanowire is spaced-apart from immediately adjacent nanowire. A gate structure extends in third direction over first region of nanowire structure, the third direction being substantially perpendicular to both first direction and second direction. The gate structure includes a gate electrode. Source/drain regions are disposed over second region of nanowire structure, the second region being located on opposing sides of gate structure. The gate electrode wraps around each nanowire.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: October 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Ka-Hing Fung
  • Patent number: 10062763
    Abstract: A sacrificial cap is grown on an upper surface of a conductor. A dielectric spacer is against a side of the conductor. An upper dielectric side spacer is formed on a sidewall of the sacrificial cap. The sacrificial cap is selectively etched, leaving a cap recess, and the upper dielectric side spacer facing the cap recess. Silicon nitride is filled in the cap recess, to form a center cap and a protective cap having center cap and the upper dielectric spacer.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: August 28, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Junjing Bao, Haining Yang, Yanxiang Liu, Jeffrey Junhao Xu
  • Patent number: 10038054
    Abstract: Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: July 31, 2018
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Van H. Le, Ravi Pillarisetty, Jack T. Kavalieros, Robert S. Chau, Seung Hoon Sung
  • Patent number: 9899490
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a nanowire structure formed over the substrate. In addition, the nanowire structure includes a first portion, a second portion, and a third portion. The semiconductor structure further includes a gate structure formed around the third portion of the nanowire structure and a source region formed in the first portion of the nanowire structure. In addition, a depletion region in the nanowire structure has a length longer than a length of the gate structure and is not in contact with the source region.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jean-Pierre Colinge
  • Patent number: 9893173
    Abstract: A method for fabricating a metal oxide thin film transistor comprises the steps of: selecting a substrate and fabricating a gate electrode on the substrate; growing a layer of dielectric or a high permittivity dielectric on the substrate, and allowing the layer of dielectric or high permittivity dielectric to cover the gate electrode to serve as a gate dielectric layer; growing a metal layer on the gate dielectric layer; fabricating a channel in the middle position of the metal layer; anodizing the metal of the channel at atmospheric pressure and room-temperature; fabricating an active region comprising a source, a drain, and the channel; depositing a silicon nitride layer on the active region and forming two contact holes of the electrodes on the silicon nitride layer; and depositing a layer of aluminum film and fabricating two metal contact electrodes of the thin film transistor.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: February 13, 2018
    Assignee: SHENZHEN GRADUATE SCHOOL, PEKING UNIVERSITY
    Inventors: Shengdong Zhang, Yang Shao, Xiang Xiao, Xin He
  • Patent number: 9812553
    Abstract: A method for forming a spacer for a semiconductor device includes patterning gate material in a transverse orientation relative to semiconductor fins formed on a substrate and conformally depositing a dummy spacer layer over surfaces of gate structures and the fins. A dielectric fill formed over the gate structures and the fins is planarized to remove a portion of the dummy spacer layer formed on tops of the gate structures and expose the dummy spacer layer at tops of the sidewalls of the gate structures. Channels are formed by removing the dummy spacer layer along the sidewalls of the gate structures. The fins are protected by the dielectric fill. A spacer is formed by filling the channels with a spacer material. The dielectric fill and the dummy spacer layer are removed to expose the fins. Source and drain regions are formed between the gate structures on the fins.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: November 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu, Jie Yang
  • Patent number: 9799583
    Abstract: In one embodiment, a semiconductor device includes a first contact pad disposed at a top side of a workpiece, a second contact pad disposed at the top side of the workpiece. An isolation region is disposed between the first contact pad and the second contact pad. A metal strip is disposed at least partially within the isolation region. The metal strip is not coupled to an external potential node.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: October 24, 2017
    Assignee: Infineon Technologies AG
    Inventors: Thomas Krotscheck Ostermann, Andrew Christopher Graeme Wood, Peter Maier Brandl
  • Patent number: 9691851
    Abstract: A semiconductor device includes one nanowire structure disposed on semiconductor substrate and extending in first direction on semiconductor substrate. Each nanowire structure includes plurality of nanowires extending along first direction and arranged in second direction, the second direction being substantially perpendicular to first direction. Each nanowire is spaced-apart from immediately adjacent nanowire. A gate structure extends in third direction over first region of nanowire structure, the third direction being substantially perpendicular to both first direction and second direction. The gate structure includes a gate electrode. Source/drain regions are disposed over second region of nanowire structure, the second region being located on opposing sides of gate structure. The gate electrode wraps around each nanowire.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: June 27, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Ka-Hing Fung
  • Patent number: 9577074
    Abstract: A method of manufacturing a FinFET device is provided, comprising: a. providing a substrate (100); b. forming a fin (200) on the substrate; c. forming an shallow trench isolation structure (300) on the substrate; d. forming an sacrificial gate stack on the isolation structure, wherein the sacrificial gate stack intersects the fin; e. forming source/drain doping regions by ion implantation into the fin; f. depositing an interlayer dielectric layer (400) on the substrate; g. removing the sacrificial gate stack to form a sacrificial gate vacancy; h. forming an doped region (201) under the sacrificial gate vacancy; i. etching the shallow trench isolation structure (300) under the sacrificial gate vacancy until the top surface of the shallow trench isolation structure (300) levels with the bottom surface of the source/drain doping regions; j. forming a new gate stack in the sacrificial gate vacancy.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: February 21, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Yunfei Liu, Haizhou Yin, Keke Zhang
  • Patent number: 9543407
    Abstract: A method for semiconductor fabrication includes providing mask layers on opposite sides of a substrate, the substrate having one or more mandrels. Dummy spacers are formed along a periphery of the mask layers. A dummy gate structure is formed between the dummy spacers. The dummy spacers are removed to provide a recess. Low-k spacers are formed in the recess.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: January 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Chiahsun Tseng, Tenko Yamashita, Chun-Chen Yeh, Yunpeng Yin
  • Patent number: 9515169
    Abstract: There is provided a FinFET fabricating method, comprising: a. providing a substrate ; b. forming a fin on the substrate; c. forming a channel protective layer on the fin; d. forming a shallow trench isolation on both sides of the fin; e. forming a sacrificial gate stack and a spacer on the top surface and sidewalls of the channel region which is in the middle of the fin; f. forming source/drain regions in both ends of the fin; g. depositing an interlayer dielectric layer on the sacrificial gate stack and the source/drain regions, planarizing later to expose the sacrificial gate stack; h. removing the sacrificial gate stack stack to form a sacrificial gate vacancy and expose the channel region and the channel protective layer; i. covering a portion of the semiconductor structure in one end of the fin with a photoresist layer; j. removing a portion of the spacer not covered; k. removing the photoresist layer and filling a gate stack in the sacrificial gate vacancy; l.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: December 6, 2016
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Haizhou Yin, Yunfei Liu
  • Patent number: 9502539
    Abstract: The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: November 22, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: You-Ru Lin, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 9461149
    Abstract: Methods to fabricate a stacked nanowire field effect transistor (FET) with reduced gate resistance are provided. The nanowire stack in the stacked nanowire FET can be provided by first forming a material stack of alternating sacrificial material layers and nanowire material layer. The sacrificial material layers and selected nanowire material layers in the material stack are subsequently removed to increase a vertical distance between two active nanowire material layers.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: October 4, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hongmei Li, Junjun Li, Xiaoping Liang, Kai Zhao
  • Patent number: 9455140
    Abstract: One illustrative method disclosed herein includes, among other things, performing first and second in situ doping, epitaxial deposition processes to form first and second layers of in situ doped epi semiconductor material, respectively, above a semiconductor substrate, wherein one of the first and second layers has a high level of germanium and a low level of P-type dopant material and the other of the first and second layers has a low level of germanium and a high level of P-type dopant material, and performing a mixing thermal anneal process on the first and second layers so as to form the final silicon germanium material having a high level of germanium and a high level of P-type dopant material.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: September 27, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Jody A. Fronheiser, Murat Kerem Akarvardar
  • Patent number: 9443738
    Abstract: Semiconductor devices and methods for forming the devices with middle of line capacitance reduction in self-aligned contact process flow are provided. One method includes, for instance: obtaining a wafer with at least one source, at least one drain, and at least one sacrificial gate; forming a first contact region over the at least one source and a second contact region over the at least one drain; removing the at least one sacrificial gate; forming at least one gate; and forming at least one small contact over the first contact region and the second contact region. An intermediate semiconductor device is also disclosed.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: September 13, 2016
    Assignees: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hui Zang, Balasubramanian Pranatharthiharan
  • Patent number: 9431521
    Abstract: A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: August 30, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Chun-Chen Yeh
  • Patent number: 9401415
    Abstract: Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The FinFET device structure includes a fin structure extending above a substrate and a gate dielectric layer formed over the fin structure. The FinFET device structure also includes a gate electrode formed on the gate dielectric layer. The FinFET device structure further includes a number of gate spacers formed on sidewalls of the gate electrode. The gate spacers are in direct contact with the fin structure.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: July 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung-Jung Chang
  • Patent number: 9397191
    Abstract: An isolation region is formed in a semiconductor substrate to laterally define and electrically isolate a device region and first and second laterally adjacent well regions are formed in the device region. A gate structure is formed above the device region such that the first well region extends below an entirety of the gate structure and a well region interface formed between the first and second well regions is laterally offset from a drain-side edge of the gate structure. Source and drain regions are formed in the device region such that the source region extends laterally from a source-side edge of the gate structure and across a first portion of the first well region to a first inner edge of the isolation region and the drain region extends laterally from the drain-side edge and across a second portion of the first well region.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: July 19, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jerome Ciavatti, Yanxiang Liu
  • Patent number: 9390932
    Abstract: Embodiments of the present invention provide methods for forming layers that comprise electropositive metals through ALD (atomic layer deposition) and or CVD (chemical vapor deposition) processes, layers comprising one or more electropositive metals, and semiconductor devices comprising layers comprising one or more electropositive metals. In embodiments of the invention, the layers are thin or ultrathin (films that are less than 100 ? thick) and or conformal films. Additionally provided are transistor devices, metal interconnects, and computing devices comprising metal layers comprising one or more electropositive metals.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Patricio E. Romero, Scott B. Clendenning
  • Patent number: 9263594
    Abstract: An embodiment of the present invention provides a TFT array substrate including: a base substrate (1) and thin film transistors. The thin film transistor includes a gate electrode (2), a semiconductor layer (5), a semiconductor protective layer, a source electrode (8) and a drain electrode (9). The semiconductor protective layer is disposed adjacent to the semiconductor layer (5) and includes a composite lamination structure, which includes a protective layer formed of an insulating material capable of preventing de-oxygen of the semiconductor layer (5) and an insulating layer formed of an insulating material to be etched more easily.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: February 16, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiang Liu, Jianshe Xue
  • Patent number: 9231080
    Abstract: A replacement metal gate process which includes forming a fin on a semiconductor substrate; forming a dummy gate structure on the fin; removing the dummy gate structure to leave an opening that is to be filled with a permanent gate structure; depositing a high dielectric constant (high-k) dielectric material in the opening and over the fin; depositing a work function metal in the opening and over the fin so as to be in contact with the high-k dielectric material, the high k dielectric material and the work function metal only partially filling the opening; filling a remainder of the opening with an organic material; etching the organic material until it is partially removed from the opening; etching the work function metal until it is at a same level as the organic material; removing the organic material; and filling the opening with a metal until the opening is completely filled.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: January 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: David V. Horak, Effendi Leobandung, Stefan Schmitz, Junli Wang
  • Patent number: 9029834
    Abstract: Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the SOI layer in a ladder-like configuration. The BOX is recessed under the nanowires. A patternable dielectric dummy gate(s) is formed over the recessed BOX and surrounding a portion of each of the nanowires. A CMP stop layer is deposited over the dummy gate(s) and the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the dummy gate(s). The dummy gate(s) is at least partially removed so as to release the nanowires in a channel region. The dummy gate(s) is replaced with a gate conductor material.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy Cohen, Michael A. Guillorn
  • Patent number: 8994107
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided herein. In an embodiment, a semiconductor device includes a semiconductor substrate. A source region and a drain region are disposed in the semiconductor substrate. A channel region is defined in the semiconductor substrate between the source region and the drain region. A gate dielectric layer overlies the channel region of the semiconductor substrate, and a gate electrode overlies the gate dielectric layer. The channel region includes a first carbon-containing layer, a doped layer overlying the first carbon-containing layer, a second carbon-containing layer overlying the doped layer, and an intrinsic semiconductor layer overlying the second carbon-containing layer. The doped layer includes a dopant that is different than carbon.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: March 31, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: El Mehdi Bazizi, Francis Benistant
  • Patent number: 8952452
    Abstract: Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film pattern. A spacer structure is formed on at least one side of the gate electrode and the gate insulating film pattern. The spacer structure includes a first insulating film spacer contacting the gate insulating film pattern, and a second insulating film spacer on an outer side of the first insulating film spacer. The semiconductor device has an air gap between the first insulating film spacer and the second insulating film spacer.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Seong Kang, Yoon-Hae Kim, Jong-Shik Yoon
  • Patent number: 8823095
    Abstract: It is the purpose of the invention to provide a MOS transistor (20) which guarantees a voltage as high as possible, has a required area as small as possible and which enables the integration into integrated smart power circuits. It results there from as an object of the invention to form the edge structure of the transistors such that it certainly fulfils the requirements on high breakthrough voltages, a good isolation to the surrounding region and requires a minimum of surface on the silicon disc anyway. This is achieved with an elongated MOS power transistor having drain (30) and source (28) for high rated voltages above 100V, wherein the transistor comprises an isolating trench (22) in the edge area for preventing an early electrical breakthrough below the rated voltage. The trench is lined with an isolating material (70, 72), wherein the isolating trench terminates the circuit component.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: September 2, 2014
    Assignee: X-Fab Semiconductor Foundries AG
    Inventor: Ralf Lerner
  • Patent number: 8816328
    Abstract: A method to fabricate a carbon nanotube (CNT)-based transistor includes providing a substrate having a CNT disposed over a surface; forming a protective electrically insulating layer over the CNT and forming a first multi-layer resist stack (MLRS) over the protective electrically insulating layer. The first MLRS includes a bottom layer, an intermediate layer and a top layer of resist. The method further includes patterning and selectively removing a portion of the first MLRS to define an opening for a gate stack while leaving the bottom layer; selectively removing a portion of the protective electrically insulating layer within the opening to expose a first portion of the CNT; forming the gate stack within the opening and upon the exposed first portion of the carbon nanotube, followed by formation of source and drain contacts also in accordance with the inventive method so as to expose second and third portions of the CNT.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B Chang, Martin Glodde, Michael A. Guillorn
  • Patent number: 8802514
    Abstract: Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Wilfried Ernst-August Haensch, Zihong Liu
  • Patent number: 8803129
    Abstract: A structure includes a substrate having a carbon nanotube (CNT) disposed over a surface. The CNT is partially disposed within a protective electrically insulating layer. The structure further includes a gate stack disposed over the substrate. A first portion of a length of the CNT not covered by the protective electrically insulating layer passes through the gate stack. Source and drain contacts are disposed adjacent to the gate stack, where second and third portions of the length of CNT not covered by the protective electrically insulating layer are conductively electrically coupled to the source and drain contacts. The gate stack and the source and drain contacts are contained within the protective electrically insulating layer and within an electrically insulating organic planarization layer that is disposed over the protective electrically insulating layer. A method to fabricate a CNT-based transistor is also described.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B Chang, Martin Glodde, Michael A. Guillorn
  • Patent number: 8796758
    Abstract: A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu
  • Patent number: 8772168
    Abstract: Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: July 8, 2014
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Ruilong Xie, Balasubramanian Pranatharthi Haran, David V. Horak, Su Chen Fan
  • Patent number: 8766360
    Abstract: An apparatus comprises: a semiconductor device on a base substrate, the semiconductor device having a core metal positioned proximate a source and a drain in the base substrate; a work function metal on a portion of the core metal; a dielectric liner on a portion of the work function metal; a metal gate in electrical communication with one of the source and the drain; and an insulator film implanted into the core metal, the insulator film forming an insulative barrier across the metal gate and between the core metal and the source or the drain.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Junli Wang, Keith Kwong Hon Wong, Chih-Chao Yang
  • Patent number: 8722500
    Abstract: Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes processing the IC in a replacement gate technology including forming dummy gates, sidewall spacers on the dummy gates, and metal silicide contacts to active areas. A fill layer is deposited and planarized to expose the dummy gates and the dummy gates are removed. A mask is formed having an opening overlying a portion of the channel region from which the dummy gate was removed and a portion of an adjacent metal silicide contact. The fill layer and a portion of the sidewall spacers exposed through the mask opening are etched to expose a portion of the adjacent metal silicide contact. A gate electrode material is deposited overlying the channel region and exposed metal silicide contact and is planarized to form a gate electrode and a gate-to-metal silicide contact interconnect.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: May 13, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Thilo Scheiper, Stefan Flachowsky, Andy Wei
  • Patent number: 8703611
    Abstract: A method for manufacturing a semiconductor structure is disclosed. The method comprises following steps. A substrate is provided. A sacrificial layer is formed on the substrate. The sacrificial layer is patterned to develop a first opening and a second opening. The first opening corresponds to an exposed portion of the substrate and the second opening corresponds to an unexposed portion of the substrate. A heat procedure is performed. A target material is formed on the exposed portion of the substrate and a rest part of the sacrificial layer. The rest part of the sacrificial layer and parts of the target material on the rest part of the sacrificial layer are removed. A predetermined patterned target material is obtained.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: April 22, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Ming-Kuan Chen
  • Publication number: 20140103434
    Abstract: Structure and methods for a semiconductor transistor design. The transistor structure comprises a field effect transistor having a multi-finger gate and three or more diffusion regions. Each diffusion region is identified as either a source region or a drain region, and each diffusion region is further identified as either an inner diffusion region or an outer diffusion region. Electrical contacts are established in the inner diffusion regions and the outer diffusion regions. There are approximately twice as many contacts in an inner source region as in the outer source region. There are approximately twice as many contacts in an inner drain region as in the outer drain region. The number and locations of contacts in each diffusion region are adjusted to reduce the difference among source node voltages of all fingers and the difference among drain node voltages of all fingers.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Ning Lu
  • Patent number: 8698243
    Abstract: Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: April 15, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Thilo Scheiper