Abstract: A semiconductor memory device including a first memory having a first floating gate formed over a semiconductor substrate, a first control gate formed over and insulated from the first floating gate, a first impurity region and a second impurity region formed within the semiconductor substrate, wherein the first impurity region is deeper than the second impurity region, and a second memory having a second floating gate formed over the semiconductor substrate, a second control gate formed over and insulated from the second floating gate, the first impurity region, and a third impurity region formed within said semiconductor substrate, wherein the first impurity region is deeper than said third impurity region, and a pair of wirings formed on and in electrical contact with the second and third impurity regions, respectively. In one embodiment, the pair of wirings may function as a bit line.

Abstract: Low threshold voltage transistors are fabricated by removing oxide spacers from the poly gate sidewalls of the transistors that are to be low threshold voltage. This causes the effective channel length of the low Vt transistors to be shorter than that of the core transistors, which causes lower threshold voltage.

Abstract: An insulated gate bipolar transistor is disclosed, which comprises a first conductivity type base layer, a second conductivity type base layer and an emitter layer which are selectively formed in an upper surface of the first conductivity type base layer, a buffer layer and a collector layer which are formed on a back surface of the first conductivity type base layer. A requirement of d2/d1>1.5 is satisfied, where d1 is a depth in the buffer layer, as measured from an interface of the buffer layer and the collector layer, at which a first conductivity type impurity concentration in the buffer layer shows a peak value, and d2 is a shallowest depth in the buffer layer, as measured from the interface of the buffer layer and the collector layer, at which an activation ratio of the first conductivity type impurity in the buffer layer is a predetermined value.

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same, more particularly to a new dual gate P+ salicide forming technology having an elevated channel and a source/drain using the selective SiGe epi-silicon growth technology.

Abstract: A semiconductor device comprising a gate having an approximately 0.05 &mgr;m channel length, an oxide layer below the gate, a self-aligned compensation implant below the oxide layer, a halo implant surrounding the self-aligned compensation implant below the oxide layer; and gate and drain regions on opposite sides of the halo implant and below the oxide layer.

Abstract: An integrated circuit device is presented. The integrated circuit device of the present invention comprises a semiconductor substrate having a combination of transistor gates formed using a conventional dielectric-capped gate stack for self-aligned diffusion contacts (SAC) as well as a transistor gate structure formed by removing the dielectric-cap gate stack from selected regions of the semiconductor substrate and replacing the dielectric-cap gate stack with a second gate conductor which is patterned using a damascene process.

Abstract: An integrated circuit drain extension transistor. A transistor gate (72) is formed over a CMOS n-well region (10). A transistor source extension region (50), and drain extension region (52) are formed in the CMOS well region (10). A transistor region (90) is formed in the source extension region 50 and a transistor drain region 92 is formed between two drain alignment structures (74), (76) in the drain extension region (52).

Abstract: A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor.

Abstract: An electrostatic discharge (ESD) protection transistor for discharging current from an ESD event present on an input/output pad. The ESD protection transistor is capable of improved discharging of excessive current without damage to the semiconductor device and to the ESD protection transistor itself. The ESD protection transistor includes a first conductive line connecting an input/output pad to the source and drain of the transistor at multiple points preventing the convergence of an excessive current at a certain point and ESD damage to the transistor. The transistor also includes a second conductive line formed on an insulating layer such that it does not overlap with the first conductive line.

Abstract: A DMOS field effect transistor fabricated from a SiGe heterostructure and a method of fabricating same. The heterostructure includes a strained Si layer on a relaxed, low dislocation density SiGe template. In an exemplary embodiment, the DMOS FET includes a SiGe/Si heterostructure on top of a bulk Si substrate. The heterostructure includes a SiGe graded layer, a SiGe cap of uniform composition layer, and a strained Si channel layer. In accordance with another embodiment, the invention provides a heterostructure for a DMOS transistor, and method of fabricating same, including a monocrystalline Si substrate, a relaxed uniform composition SiGe layer on the substrate; a first strained-Si channel layer on the uniform composition SiGe layer, a SiGe cap layer on the strained-Si channel layer, and a second strained-Si layer on the cap layer.

Abstract: Many integrated circuits include a type of transistor known as a metal-oxide-semiconductor, field-effect transistor, or “mosfet,” which has an insulated gate member that controls its operation. Early mosfets had aluminum gates. But because the aluminum made the mosfets unreliable and difficult to manufacture, aluminum was abandoned in favor of polysilicon. Unfortunately, polysilicon has ten-times more electrical resistance than aluminum, which not only wastes power but also slows operation of the integrated circuits. Several efforts have been made to use materials less-resistive than polysilicon, but these have failed to yield a practical solution, since some of the materials have high electrical resistance and prevent low-voltage operation.

Abstract: A sidewall insulating film is formed on the side faces of a gate electrode on a substrate. A trench isolation film is also formed to be self-aligned with the gate electrode. The upper surface of the trench isolation film reaches a level higher than that of the gate electrode. And source/drain contacts, which make electrical contact with source/drain regions, are formed between the sidewall insulating film and the isolation film. Since the source/drain contacts and the isolation film are both self-aligned with the gate electrode, no mask overlay margin is needed. Thus, the size of the entire active region or the source/drain contacts (or source/drain regions) can be reduced in the gate length direction.

Abstract: A sidewall insulating film is formed on the side faces of a buried gate electrode on a substrate. A trench isolation film, self-aligned with the gate electrode, is also formed so that the upper surface of the isolation film is higher than that of the gate electrode. And source/drain contacts, which make electrical contact with source/drain regions, are formed between the sidewall insulating film and isolation film. Since the source/drain contacts and isolation film are both self-aligned with the gate electrode, no mask overlay margin is needed. Thus, the size of the entire active region and that of the source/drain contacts or source/drain regions can be reduced in the gate length direction.

Abstract: A semiconductor memory device and a fabricating method thereof are provided. In the course of forming a buried contact hole after forming a bit line pattern, the buried contact hole is formed by a self aligned contact process using capping layers included in the bit line pattern, thereby securing an overlap margin. Formation of a deep inner cylinder type capacitor unit prevents a bridge defect between lower electrodes of the capacitor and suppresses the occurrence of particles while simplifying the fabrication process. Furthermore, a mechanism for forming a second metal contact hole can simplifies the problems related to etching and filling of the second metal contact hole.

Abstract: Disclosed is a type “BC” body contacted SOI transistor and process for making these transistors in a manufacturing environment by providing a structure and process which removes overlay tolerance from the effective transistor width. The width is determined by RX on the top side, but by PC on the other with source and drain connected together. In the preferred embodiment such a structure is used as the top part of the SOI transistor with the bottom part a mirror image of the top part such that the effect of the PC to RX overlay is reversed, and the top part and bottom part are connected by a common body part. For the bottom part an “UP misalignment will make the device with large, while a “DOWN” misalignment will make the device width smaller. Thus, if PC is misalleged with respect to RX, any width errors introduced in the top part of the transistor will be exactly canceled by the bottom part of the transistor.

Abstract: A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) on the germanium layer, and forming a gate electrode (e.g., titanium nitride 60) on the gate dielectric. The method may comprise forming source and drain regions 64 in the substrate on either side of the gate dielectric. The germanium layer, which is preferably epitaxially grown, generally prevents formation of a low dielectric constant layer between the gate dielectric and the semiconductor substrate. The disclosed structure comprises a germanium layer 52 disposed on a semiconductor substrate (e.g. silicon 20), a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) disposed on the germanium layer, and a gate electrode (e.g., titanium nitride 60) disposed on the gate dielectric.

Abstract: A MOS transistor of the present invention includes a semiconductor substrate of a first conductivity type impurity, a gate insulating layer formed on the semiconductor substrate, gate electrodes formed on the gate insulating layer, and an oxide layer formed by surface oxidation of the gate electrodes. A first spacer is formed on the side wall of the gate electrodes, and a second spacer is formed on the inclined side wall. A first impurity layer of low concentration is formed at a first depth by a second conductivity type impurity implanted in the vicinity of surface of the semiconductor substrate to be self-aligned at the edge of the gate electrode. A second impurity layer of middle concentration is formed at a deeper second depth than the first depth by the second conductivity type impurity implanted in the vicinity of surface of the semiconductor substrate.

Abstract: A method of producing an asymmetrical semiconductor device with ion implantation techniques and semiconductor devices constructed according to this method in which a barrier of ion absorbing material of height h is positioned beside a structure on a semiconductor surface. The barrier is located at a maximum distance d from one side of the structure, and an angled ion implant is directed at the side of the structure. The maximum distance d of the barrier from the side of the structure is equal to the height of the barrier h divided by the tangent of the angle of the ion implant so that the side of the structure is shadowed from the ion implant. A second ion implant is directed to the opposite side of the structure on the semiconductor surface, thereby forming a desired implant and producing the asymmetrical semiconductor device.

Abstract: An ESD protection circuit with buried diffusion and internal overlap coupling capacitance is used to lower trigger voltage and create a compact protection circuit area. This protection circuit can be applied to memory and logic products and can be employed in power bus, input, and output pins to protect against ESD. The manufacturing process of this high-performance protection circuit is compatible with non-volatile memory process without an additional mask layer step.

Abstract: A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by first forming several chemically distinct layers. Anisotropic etching then forms openings in a top one of the layers. A blanket dielectric layer is formed in the openings and on the layers. Anisotropic etching removes portions of the blanket dielectric layer from planar surfaces of the substrate but not from sidewalls of the openings to form dielectric spacers separated by gaps within the openings. Gate oxides are formed by oxidation of exposed areas of the substrate. Ion implantation forms channels beneath the gate oxides. Polysilicon deposition followed by chemical-mechanical polishing defines gates in the gaps. The chemically distinct layers are then stripped without removing the dielectric spacers.

Abstract: A method of processing wafers containing a gate oxide assembly (10) is disclosed that reduces gate oxide damage during wafer production due to damage caused by charging. The method comprises creating an oxide gate assembly (10) on a silicon layer (11) in a production line chamber followed by the deposition of a polysilicon layer (22). Following the creation of the gate oxide assembly (10) a pressure of at least 1.2 Torr is maintained while lowering the power within the production line chamber. The invention can be used with a gate oxide layer (16) of less than 1000 angstroms.

Abstract: A gate electrode is formed on a first conductive type semiconductor. Next, a second conductive type first impurity is selectively introduced in a drain formation planned region at a surface of the semiconductor substrate to form a first diffusion layer. Then, a second conductive type second impurity having a diffusion coefficient smaller than that of the first impurity is selectively introduced in a source formation planned region at the surface of the semiconductor substrate to form a second diffusion layer. Thereafter, a side wall is formed on a side surface of the gate electrode. Then, a second conductive type third impurity is introduced at the surface of the semiconductor substrate at a density higher than the first and second impurities, using the gate electrode and the side wall as a mask.

Abstract: In a case where an impurity for suppressing the short channel effect of MISFETs is introduced into a semiconductor substrate obliquely to the principal surface thereof, gate electrodes adjacent to each other are arranged so that the impurity to be introduced in directions crossing the gate electrodes may not be introduced into the part of the semiconductor substrate lying between the gate electrodes, and the source region of the MISFETs is arranged in the part between the gate electrodes.

Abstract: A high voltage metal oxide semiconductor device. The high voltage device comprises a high voltage NMOS, a high voltage PMOS, or a high voltage CMOS. A field oxide layer is used to isolate the gate from the source region, while a diffusion region is formed under the field oxide layer. A channel region around the source drain extends across a first doped well and a second doped well having different dopant concentration. The channel region further comprises two grading regions with different dopant concentrations around the drain region.

Abstract: A counter-doped epitaxial silicon (doped opposite to the substrate type) is used to form the buried layer in a CMOS transistor, while maintaining an abrupt channel profile. Shallow source/drain junctions with abrupt source/drain profiles may be formed using raised (or elevated) source/drain design. The invention encompasses a transistor structure including a doped silicon substrate, and an oppositely-doped epitaxial silicon layer formed on the substrate. A gate is formed on the epitaxial layer, the gate defining a channel region in the epitaxial layer underneath the gate. A layer is formed on the epitaxial silicon layer on opposing sides of, and is electrically isolated from, the gate.

Abstract: A MOSFET includes a gate oxide formed on a substrate. A thin dielectric layer is formed on the side walls of the gate. A gate is formed on the gate oxide. A first metal silicide layer is formed on top of the gate to increase the conductivity of the gate. Spacers are formed on the substrate and are separated with the gate by a space. Air gaps are formed between the gate and the spacers. First doped ion regions are formed aligned to the air gaps in the substrate, under a portion of the dielectric layer. Second doped ion regions are formed under the spacers in the substrate, next to the first doped ion regions. Third doped ion regions are formed in the substrate next to the second doped ion regions. The third doped ion regions have relatively highly doped ions to the first doped ion regions. The second doped ion regions are formed with immediately highly doped ions between the first and the third doped ion regions.

Abstract: A method of manufacture of self-aligned floating gate, flash memory device on a semiconductor substrate includes the following steps. Form a blanket silicon oxide layer over the substrate. Form a blanket floating gate conductor layer over the silicon oxide layer. Pattern the blanket silicon oxide layer, the floating gate conductor layer and the substrate in a patterning process with a single floating gate electrode mask forming floating gate electrodes from the floating gate conductor layer and the silicon oxide layer; and simultaneously form trenches in the substrate adjacent to the floating gate electrode and aligned with the floating gate electrodes thereby patterning the active region in the substrate. Form a blanket dielectric layer on the device filling the trenches and planarized with the top surface of the floating gate electrodes. Form an interconductor dielectric layer over the device including the floating gate electrodes. Form a control gate conductor over the interconductor dielectric layer.

Abstract: The present invention provides a semiconductor device and a method for providing such a semiconductor device which allows a field oxide etch while minimizing the damage to the silicon. This method is particularly useful for smaller semiconductor devices, for example, such as a semiconductor device utilizing core source spacing less than 0.4 microns. A method according to the present invention for providing a semiconductor device comprises the steps of depositing a first spacer oxide layer over a core area and a peripheral area of a semiconductor device; etching the first spacer oxide layer at the source side of core cell area; depositing a second spacer oxide layer over the core area and the peripheral area, and etching the first and second spacer oxide layers over the peripheral area only.

Abstract: Ion implantation of fluorine into SiO.sub.2 films results in formation of a dielectric material having a dielectric constant K.ltoreq.3.2. High energies associated with ion implantation permit stable introduction of high concentrations of fluorine within silicon oxide, without giving rise to problems of fluorine outgassing and water absorption associated with conventional FSG deposition techniques. Relatively thick FSG layers conventionally formed by CVD may be sandwiched between implanted FSG liner films formed in accordance with the present invention. Such a combination would reduce the dielectric constant of the dielectric structure as a whole while providing a barrier to fluorine diffusion, without consuming the processing time required to implant an entire dielectric layer.

Abstract: A method and a deep sub-micron FET structure for suppressing short channel effects and reducing gate-to-drain overlay capacitance and for making CMOS devices is achieved. The method for making these improved FETs includes forming a gate oxide and a patterned polysilicon layer for gate electrodes. Silicon nitride (Si.sub.3 N.sub.4) first sidewall spacers are formed on the sidewalls of the gate electrodes. After selectively removing the gate oxide adjacent to the first sidewall spacers, second sidewall spacers are formed from a doped oxide that serve as a solid-phase diffusion source. The source/drain contact areas are implanted adjacent to the second sidewall spacers. The substrate is then annealed to diffuse from the second sidewall spacers the lightly doped source/drains (LDDs). The Si.sub.3 N.sub.4 sidewall spacers serve as a diffusion barrier and the LDDs are formed finder the Si.sub.3 N.sub.

Abstract: A dual voltage chip is fabricated with no intermediate-doped (LDD or MDD) area in the high-voltage transistors by adjusting the gate sidewall spacer thickness and the source/drain implant.

Abstract: A simplified method for forming a self-aligned contact hole is disclosed. The method comprises the steps of (a) providing a semiconductor substrate having a gate electrode and a diffusion region thereon; (b) forming a conformal layer of etch barrier material overlying the substrate surface including the diffusion region and the upper surface and the sidewalls of the gate electrode; (c) forming an insulating layer overlying the barrier layer; (d) etching an opening through the insulating layer self-aligned and borderless to the diffusion region by using the barrier layer as an etch stop; and (e) anisotropically etching the barrier layer underneath the opening, thereby exposing the diffusion region and simultaneously forming a spacer of the etch barrier material on the sidewall of the gate electrode.

Abstract: The present invention includes two transistors every output signal line connected at crosspoints of a plurality of input signal lines and a plurality of output signal lines, with a channel region of one of these transistors being implanted or diffused with an impurity so as to be normally in an active state. By then selectively making electrical connection with one of the plurality of output signal lines, the coded data cannot be easily known because the corresponding relationship of the input signal lines and the output signal lines cannot be confirmed from the wiring layout.

Abstract: A method of forming an integrated circuit device, and in particular a CMOS integrated circuit device, having an improved lightly doped drain region. The methods include the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectric over each P type well and N type well regions. The present LDD fabrication methods then provide a relatively consistent and easy method to fabricate CMOS LDD regions with N type and P type implants at a combination of different dosages and angles using first and second sidewall spacers, with less masking steps and improved device performance.

Abstract: An electrostatic discharge protection device for protecting a mixed voltage integrated circuit against damage is provided which includes at least on pair of NMOS transistors connected in a cascode configuration. Each NMOS transistor pair includes a first transistor, having a drain region coupled to and I/O stage of the mixed voltage integrated circuit, and a gate region coupled to the mixed voltage integrated circuit's low power supply. The second NMOS transistor of the pair is merged into the same active area as the first transistor and has a gate region and a source region coupled to the ground plane of the mixed voltage integrated circuit. The source region of the first transistor and the drain region of the second transistor are constructed of a shared NMOS diffusion region.

Abstract: A 16 Mbit DRAM of the invention is made up of a nexus of four 4 Mbit DRAM chips which are formed adjacent to one another on the wafer and each constitute an individual 4 Mbit DRAM, the connection between the 4 Mbit DRAMs is formed through a short-circuit protecting circuit provided within each 4 Mbit DRAM and an interconnection/controller circuit portion formed in the dicing area between the 4 Mbit DRAMs. When the nexus is cut along the dicing area containing the interconnection/controller circuit portion, 4 Mbit DRAM chips and/or 8 Mbit DRAM chips can be produced as desired.

Abstract: An integrated circuit device in which the gate oxide of the devices in the integrated circuit device is selected to control plasma damage during device processing is disclosed. The integrated circuit device has at least two transistors, each transistor having a source, drain, gate and channel. At least one device has a channel length that is greater than 0.5 .mu.m and at least one device has a channel length that is less than 0.5 .mu.m. The device having a channel length that is greater than 0.5 .mu.m has a gate oxide thickness that is less than the gate oxide thickness of the device having a channel length that is less than 0.5 .mu.m. The relative thickness of the gate oxide for the shorter channel devices and the longer channel devices is selected so that the tunneling leakage current that passes through the gate oxide for the longer channel devices is at least two orders of magnitude greater than the tunneling current through the gate oxide of the shorter channel devices.

Abstract: A semiconductor device comprising a substrate having thereon an active area including a plurality of MOS transistors, an inactive area, and adjacent gate wires having walls and a sidewall on the walls of the gate wires. The adjacent gate wires are arranged on the active area and on the inactive area. A first interval between the adjacent gate wires on the active area is greater than a second interval between the adjacent gate wires on the inactive area. The active area includes one of a source and drain region formed by introducing an impurity in an interval between the adjacent gate wires. This structure circumvents the problem which would otherwise occur when the active area between the adjacent gate wires is covered by the sidewalls to thereby block ion implantation. Also, the overall size of the semiconductor device can be reduced and the wiring density can be increased.

Abstract: A semiconductor device and fabrication method therefor which improve device operation of a CMOS device. The semiconductor device and fabrication method therefor prevent the deterioration of short channel properties of a PMOS device and improve current driving capability of an NMOS device. The semiconductor device has halo impurity regions formed in either the NMOS region or the PMOS region such that a channel length of the PMOS device. Also, the source and drain regions of the PMOS device are prevented from forming deep source and drain regions, thus, preventing deterioration of the short channel properties for the PMOS device.

Abstract: A dual work function CMOS device and method for producing the same is disclosed. The method includes: depositing a first layer of a doped material, either n-type or p-type, over a substrate to be doped; defining the areas that are to be oppositely doped; depositing a second layer of an oppositely doped material over the entire surface; and subjecting the entire CMOS device to a high temperature, drive-in anneal. The drive-in anneal accelerates the diffusion of the dopants into the adjacent areas, thereby doping the gate polysilicon and channels with the desired dopants. A nitride barrier layer may be utilized to prevent the second dopant from diffusing through the first layer and into the substrate beneath.

Abstract: A semiconductor apparatus formed on a semiconductor substrate includes a first active region in the substrate, and a second active region adjacent to the surface of the substrate separated from the first active region by a channel region. A gate oxide region may overlie at least a portion of the first and second active regions. The apparatus further includes a gate positioned over the channel region and having a first end and a second end respectively associated with the first and second active regions. The gate includes a first low conductive region and a second low conduction region at said first and second ends, respectively.A method for making the transistor structure of the present invention is also provided.

Abstract: A semiconductor apparatus formed on a semiconductor substrate includes a first active region in the substrate, and a second active region adjacent to the surface of the substrate separated from the first active region by a channel region. A gate oxide region may overlie at least a portion of the first and second active regions. The apparatus further includes a gate positioned over the channel region and having a first end and a second end respectively associated with the first and second active regions. The gate includes a first low conductive region and a second low conduction region at said first and second ends, respectively.A method for making the transistor structure of the present invention is also provided.

Abstract: A semiconductor device includes a substrate, a gate oxide film formed on the substrate, a gate electrode provided on the gate oxide film, first and second diffusion regions formed in the substrate at both lateral sides of the gate electrode. The gate electrode includes a first region located immediately underneath the gate electrode and a second region adjacent to the first region, wherein the first and second regions contain N atoms with respective concentrations such that the second region contains N with a higher concentration as compared with the first region.

Abstract: A method and structure are provided for an IGFET which has a short conduction channel length. The short channel IGFET functions more rapidly than do longer conduction channel devices. Also the invention includes a dielectric layer with a high dielectric constant value (K) to prolong the longevity of the device. A lightly doped drain region similarly preserves the integrity of the IGFET by protecting the gate from "hot electron injection." The method and structure provide an IGFET with increased performance without compromising the IGFET's reliability or longevity.

Abstract: A laser doping process comprising: irradiating a laser beam operated in a pulsed mode to a single crystal semiconductor substrate of a first conductive type in an atmosphere of an impurity gas which imparts the semiconductor substrate a conductive type opposite to said first conductive type and incorporating the impurity contained in said impurity gas into the surface of said semiconductor substrate, thereby modifying the type and/or the intensity of the conductive type thereof. Provides devices having a channel length of 0.5 .mu.m or less and impurity regions 0.1 .mu.m or less in depth.

Abstract: A semiconductor device having CMOS circuits formed on a glass substrate. The CMOS circuits are composed of TFTs. Lightly doped regions are formed only in the N-channel TFTs. When P-channel TFTs are formed, the conductivity type of the lightly doped regions is converted by a boron ion implant. Each CMOS circuit consists of an N-channel TFT having the lightly doped regions and a P-channel TFT having no lightly doped regions.

Abstract: A gate oxide layer, a polysilicon layer are patterned on a substrate. Then, a thermal oxidation is carried out to form the first silicon dioxide layer on the surface of the polysilicon layer. Then, a first silicon nitride layer is patterned on the first silicon dioxide layer, over the top of the polysilicon layer. Then, a second silicon nitride layer is formed on the first silicon dioxide layer and the first silicon nitride layer. Next, a second silicon dioxide layer is formed on the second silicon nitride layer. Then, an etching technique is used to form the side-wall spacers. The side-wall spacers composed of silicon nitride layer and silicon dioxide layer. A dielectric layer is formed on the cap layer, side-wall spacers and silicon dioxide layer. An etch with high selectivity is used to etch the dielectric layer to create a contact hole.

Abstract: A DRAM unit cell is disclosed which comprises a trench capacitor having a signal electrode, a bit line, a planar active word line overlapping the trench capacitor and a planar FET having a main conducting path coupled between the signal electrode of the trench capacitor and the bit line and a gate electrode formed by the active word line.

Abstract: A method and structure are provided for an IGFET which has a highly scalable short conduction channel length. The short channel IGFET functions more rapidly than do longer conduction channel devices. Lightly doped regions provide a graded extension or buffer region to the conduction channel. Thus, the voltage drop is shared by the source/drain and channel, in contrast to an abrupt n+/p junction where the almost the entire voltage drop occurs across the lightly doped (channel) side of the junction. This method and structure preserves the integrity of the IGFET by protecting the gate from "hot electron injection." The method and structure provide an IGFET with increased performance without compromising the IGFET's reliability or longevity.

Abstract: Fluorine bearing spacers on the sidewalls of gate electrodes of a semiconductor device are provided to suppress hot carrier injection in the semiconductor device. In accordance with one embodiment of the invention, a semiconductor device is formed by forming at least one gate electrode on a surface of a substrate and forming fluorine bearing spacers on the sidewalls of the gate electrode. The fluorine bearing spacers may, for example, be formed of an NF.sub.3 -doped glass material.