Abstract: A power IC for an automobile engine control unit incorporating at least one semiconductor device comprising an N-channel insulated-gate filed-effect transistor formed on an SOI substrate, having an N-type layer having a concentration higher than a concentration of an N-type layer in contact with a p-body layer contacting a gate oxide film of the transistor. The high concentration N-type layer is formed in a region covering at most 95% of the source-drain distance between the p-body layer and a drain electrode of the transistor in the silicon substrate over an interface of a buried oxide film, the silicon substrate being in contact with both the field oxide film and the high concentration N-type layer contacting the drain electrode.

Abstract: A method of fabricating a transistor (10) comprises forming source and drain regions (46) and (47) using a first sidewall (42) and (43) as a mask and forming a deep blanket source and drain regions (54) and (56) using a second sidewall (50) and (51) as a mask, the second sidewall (50) and (51) comprising at least part of the first sidewall (42) and (43).

Abstract: A semiconductor integrated circuit device comprises a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a semiconductor layer insulated from the semiconductor substrate by the insulating layer; source regions of a first conduction type and drain regions of the first conduction type both formed in the semiconductor layer; body regions of a second conduction type formed in the semiconductor layer between the source regions and the drain regions to store data by accumulating or releasing an electric charge; word lines formed on the body regions in electrical isolation from the body regions to extend in a first direction; bit lines connected to the drain regions and extending in a direction different from the first direction; and buried wirings formed in the insulating layer in electrical isolation from the semiconductor substrate and the semiconductor layer, said buried wirings extending in parallel with the bit lines.

Abstract: Thin-film transistor display devices include composite electrodes which provide low resistance contacts and paths for electrical signals and are less susceptible to parasitic metal migration which can limit display quality and lifetime. In particular, a thin-film transistor (TFT) display device is provided having an insulated gate electrode on a face of a substrate (e.g., transparent substrate) and a semiconductor layer on the insulated gate electrode, opposite the face of the substrate. Spaced apart source and drain electrodes are also provided on the semiconductor layer. These source and drain electrodes each preferably comprise a composite of at least two layers containing respective metals therein of different element type. Preferably, one of the layers comprises a metal which is capable of forming a low resistance contact with electrodes such as a pixel electrode (e.g.

Abstract: The dependency of threshold voltage on adjusted bias voltage is varied between N-channel and P-channel MOSFETs. A support substrate, an insulating layer on the support substrate, and island-shaped first and second silicon layers separately formed on the insulating layer; a first MOSFET formed of a fully depleted SOI where a first channel part is formed in a first silicon layer; and a second MOSFET formed of a partially depleted SOI where a second channel part is formed in a second silicon layer, the second MOSFET configures a complementary MOSFET with the first MOSFET, are provided. The threshold voltage of the second MOSFET formed of the partially depleted SOI is hardly varied because of a neutral region in the second channel part, although bias voltage is applied to the support substrate to vary the threshold voltage of the first MOSFET formed of the fully depleted SOI.

Abstract: Method to form a structure to decrease area capacitance within a buried insulator device structure is disclosed. A portion of the substrate layer of a buried insulator structure opposite the insulator layer from the gate is doped with the same doping polarity as the source and drain regions of the device, to provide reduced area capacitance. Such doping may be limited to portions of the substrate which are not below the gate.

Abstract: This semiconductor device is provided with a wiring called a body line (BDL), a body section of a memory cell transistor is connected to this body line (BDL), and a potential of the body section is controlled by a body section controller connected to the body line. As a result, it is possible to propose a novel structure capable of keeping the potential of the body section low and to provide a semiconductor device and a manufacturing method therefor, capable of improving operation performance by contriving circuit operation.

Abstract: A switching device for integrated circuit applications is disclosed. A first switching device includes a first device between a first voltage supply and a common output, a second device between a second voltage supply and common output, and a common input to control said first and second devices. Said first and second devices are constructed as complementary Gated-FET devices, wherein the conductive path of a Gated-FET comprises a resistive channel of the same dopant type as source and drain regions. A second switching device includes a first device between a first voltage supply and a common output, a second device between a second voltage supply and common output, and a common input to control said first and second devices. The conductive paths of said first and second devices are comprised of a single geometry of a semiconductor material.

Abstract: The present invention provides SOI material which includes a top Si-containing layer which has regions of different thickness as well as a method of fabricating such SOI material. The inventive method includes a step of thinning predetermined regions of the top Si-containing layer by masked oxidation of silicon. SOI IC chips including the inventive SOI material having different types of CMOS devices build thereon as also disclosed.

Abstract: To provide a thin film transistor having a low OFF characteristic and to provide P-channel type and N-channel type thin film transistors where a difference in characteristics of the P-channel type and the N-channel type thin film transistors is corrected, a region 145 having a P-type behavior more potential than that of a drain region 146 is arranged between a channel forming region 134 and the drain region 146 in the P-channel type thin film transistor whereby the P-channel type thin film transistor having the low OFF characteristic can be provided and a low concentration impurity region 136 is arranged between a channel forming region 137 and a drain region 127 in the N-channel type thin film transistor whereby the N-channel type thin film transistor having the low OFF characteristic and where deterioration is restrained can be provided.

Abstract: One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an oxide insulation layer. In various embodiments, the well region is a multilayer epitaxy that includes a silicon germanium (Si—Ge) layer. In various embodiments, the well region includes a number of recombination centers between the Si—Ge layer and the insulation layer. A source region, a drain region, a gate oxide layer, and a gate are formed. In various embodiments, the Si—Ge layer includes a number of recombination centers in the source/drain regions. In various embodiments, a metal silicide layer and a lateral metal Schottky layer are formed above the well region to contact the source region and the well region. Other aspects are provided herein.

Abstract: A short-channel NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a channel stop region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate, and both having a depletion region when reverse biased. The shallow regions are surrounded in part by an enhanced p-doping implant pocket. The transistor further has in these regions of enhanced p-doping another region of a p-resistivity higher than the remainder of the semiconductor. These regions extend laterally approximately from the inner border of the respective shallow region to the inner border of the respective recessed region, and vertically from a depth just below the depletion regions of source and drain to approximately the top of the channel stop regions.

Abstract: A semiconductor layer (10) provided on a BOX (buried oxide) layer (2) includes a first P-type region (11), an N+-type region (12), and an N−type region (13) which together form a diode. A plurality of second P-type regions (14) are provided on a bottom part of the semiconductor layer (10). A plurality of insulating oxide films (21) are interposed between the plurality of second P-type regions (14). When the diode is in a reverse-biased state, the second P-type region (14) directly below the N+-type region (12) is approximately the same in potential as the N+-type region (12). The second P-type region (14) will be lower in potential relative to this second P-type region (14) directly below the N+-type region (12), as the second P-type region (14) gets nearer to the first P-type region (11). Electric field concentration can thus be relaxed at an interface between the semiconductor layer (10) and the BOX layer (2), whereby improvement in breakdown voltage of the diode is realized.

Abstract: A semiconductor device has a structure in which an impurity diffusion region with an impurity concentration lower than an impurity concentration of a source and a drain is formed between the source and drain and a channel below the gate, having an asymmetric shape with respect to a center line along which the gate extends.

Abstract: Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate type transistor formed in the semiconductor layer, a highly-doped collector layer of a bipolar transistor embedded in an insulating-layer-free portion of the semiconductor substrate, and a low-doped collector layer disposed on the highly-doped collector layer of the bipolar transistor, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of the insulating layer so as to attain high breakdown voltage and high speed operation of the bipolar transistor.

Abstract: A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided in which an implanted back-gate is formed into a Si-containing layer of an SOI wafer. The implanted back-gate thus formed is capable of controlling the threshold voltage of a polysilicon-containing front-gate which is formed over a portion of the implanted back-gate region. The implanted back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.

Abstract: A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HDTMOS includes an n-type high concentration Si body region, an n− Si region, a SiGe channel region containing n-type low concentration impurities, an n-type low concentration Si cap layer, and a contact which is a conductor member for electrically connecting the gate electrode and the Si body region. The present invention extends the operation range while keeping the threshold voltage small by using, for the channel layer, a material having a smaller potential at the band edge where carriers travel than that of a material constituting the body region.

Abstract: A simiconductor device includes a simiconductor substrate, an insulating layer, a silicon layer, full depletion type transistors, and partial deletion type transistors. The insulating layer is formed on the simiconductor substrate. The silicon layer has a first region and a second region. The silicon layer is formed on the insulating layer. The full depletion type transistors are used for a logical circuit and are formed on the silicon layer at the first region. The partial depletion type transistors are used for a memory cell circuit and are formed on the silicon layer at the second region. The second region of the silicon layer is maintained at a fixed potential.

Abstract: In the case of using an analog buffer circuit, an input voltage is required to be added a voltage equal to a voltage between the gate and source of a polycrystalline silicon TFT; therefore, a power supply voltage is increased, thus a power consumption is increased with heat. In view of the foregoing problem, the invention provides a depletion mode polycrystalline silicon TFT as a polycrystalline silicon TFT used in an analog buffer circuit such as a source follower circuit. The depletion mode polycrystalline silicon TFT has a threshold voltage on its negative voltage side; therefore, an input voltage does not have to be increased as described above. As a result, a power supply voltage requires no increase, thus a low power consumption of a liquid crystal display device in particular can be realized.

Abstract: A semiconductor-on-insulator (SOI) device. The SOI device includes a substrate having a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer. The active layer has an active region defined by isolation regions, the active region having a source and a drain with a body disposed therebetween. The source and the drain have a selectively grown silicon-germanium region disposed under an upper layer of selectively grown silicon. The silicon-geranium regions form heterojunction portions respectively along the source/body junction and the drain/body junction.

Abstract: A semiconductor device in accordance with one example of the present invention pertains to a semiconductor device to be used for a CMOS inverter circuit, comprising a BOX layer 2 formed on a silicon substrate 1, a SOI film 3 including single crystal Si formed on the BOX layer, a gate oxide film 4 formed on the SOI film 3, a gate electrode 5 formed on the gate oxide film, and diffusion layers 7, 8 for source/drain regions formed in source/drain regions of the SOI film 3, wherein, when a power supply voltage of 0.6 V is used, a thickness TSOI of the SOI film 3 is 0.084 &mgr;m or greater and 0.094 &mgr;m or smaller, and an impurity concentration of the SOI film is 7.95×1017/cm3 or greater and 8.05×1017/cm3 or smaller.

Abstract: A method for forming a fin structure on a silicon-on-insulator (SOI) wafer that includes a silicon layer on an insulating layer that is formed over a semiconductor substrate includes etching the silicon layer using a first etch procedure, etching, following the first etch procedure, the silicon layer using a second etch procedure, and etching, following the second etch procedure, the silicon layer using a third etch procedure to form a T-shaped fin structure.

Abstract: A semiconductor device in accordance with the present invention includes: an insulating layer; a semiconductor region formed on the insulating layer; a trench that surrounds side parts of the semiconductor region and reaches the insulating layer; an isolation insulating film formed in the trench; a semiconductor element in which the semiconductor region serves as an active region; a side oxide film formed by oxidizing the side parts of the semiconductor region and located between the rest of the semiconductor region and the isolation insulating film; and a bottom oxide film that is formed by oxidizing a bottom part of the semiconductor region, located over the entire interface between the rest of the semiconductor region and the insulating layer, and having side surfaces that reach the side oxide film.

Abstract: A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.

Abstract: A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.

Abstract: A structure and method of using microfluidic channels to form an array of semiconductor devices is described. The microfluidic channels have been found to be particularly useful when formed in a self aligned process and used to interconnect a series of thin film transistor (TFT) devices.

Abstract: A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing an oxygen ion implantation step to create a stable defect region; a low energy implantation step to create an amorphous layer adjacent to the stable defect region, wherein the low energy implantation steps uses at least one ion other than oxygen; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising a semiconductor substrate having a DIBOX region in patterned or unpatterned forms is also provided herein.

Abstract: An N-channel MOS field-effect transistor on an SOI substrate including a source electrode, drain and gate electrodes both disposed via a field oxide film, a gate oxide film, a high concentration P-type layer, a high concentration N-type layer contacting the source electrode and the gate oxide film, a high concentration N-type layer contacting the drain electrode, a p-body layer contacting the high concentration P-type and N-type layers and the gate oxide film. In this transistor, an N-type layer with a concentration higher than that of a drain region contacting the p-body layer constitutes a region covering at most 95% of the source-drain distance. Further, an N-type region having a concentration from 3×1016/cm3 to 1×1022/cm3 is provided near a buried oxide film under the drain electrode.

Abstract: A semiconductor device comprising: a first insulating film formed on a semiconductor substrate; a semiconductor layer at least a part of which is formed on the first insulating film; a second insulating film comprising a non-doped silicon oxide film and formed on the semiconductor layer; a third insulating film comprising a silicon oxide film containing at least phosphorus formed on the second insulating film; and a fourth insulating film comprising a non-doped silicon oxide film formed on the third insulating film.

Abstract: Systems and methods are provided for static pass transistor logic having transistors with multiple vertical gates. The multiple vertical gates are edge defined such that only a single transistor is required for multiple logic inputs. Thus a minimal surface area is required for each logic input. The novel static pass transistor of the present invention includes a transistor which has a horizontal depletion mode channel region between a single source and drain region. A number of vertical gates are located above different portions of the depletion mode channel region. At least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material. At least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material.

Abstract: A method is provided for advantageously etching dielectric material between highly integrated polysilicon devices with high dielectric-to-polysilicon selectivity to expose polysilicon with minimal polysilicon loss and without photoresist lift. A wet etch solution comprising surfactant and between about 0% and about 10% NH4F is used to wet etch the dielectric material and reduce polysilicon loss thickness, polysilicon resistance ratios, and polysilicon etch rates, while increasing dielectric-to-polysilicon selectivity. Advantageously, the present invention may penetrate into increasingly small geometries of highly integrated devices and may also be used for general wet etches of dielectric material in conjunction with photoresist.

Abstract: A semiconductor device 1000 may include an element isolation region 14, an n-type field effect transistor 100 and an npn-type bipolar transistor 200 formed on a SOI substrate 10. A p-type body region 50a may be electrically connected to an n-type source region 120. The p-type body region 50a may be electrically connected to a p-type base region 220. An n-type drain region 130 may be electrically connected to an n-type collector region 230. An n-type source region 120 may be formed structurally isolated from an n-type emitter region 210.

Abstract: A fully inverted type SOI-MOSFET has a channel region 18 constructed of a portion that belongs to a top silicon layer 13 and is located just under a gate electrode 15 and a source region 16 and a drain region 17, which belong to the top silicon layer 13 and are located adjacent to this channel region 18. The channel region 18 is inverted throughout the entire thickness during operation. The source region 16 has a source resistance RS, which satisfies a relation that (1/gm)>RS with respect to the mutual conductance gm of the channel region 18 itself. According to this fully inverted type SOI-MOSFET, the effective mutual conductance (Gm) can be increased.

Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

Abstract: An LSI device includes a core region to which a first driving voltage is applied and an interface region to which a second driving voltage higher than the above first driving voltage is applied. The LSI device includes an SOI substrate and a device separation region for separating a SOI layer of the SOI substrate into the core region and the interface region. The thickness of the SOI layer of the core region is thinner than the thickness of the SOI layer of the interface region. The LSI device further includes first MOSFETs formed in the core region and in which the SOI layer of the core region is a fully depleted Si channel and second MOSFETs formed in the interface region and in which the SOI layer of the interface region is a fully depleted Si channel.

Abstract: A semiconductor device may be formed with a floating body positioned over an insulator in a semiconductor structure. A gate may be formed over the floating body but spaced therefrom. The semiconductor structure may include doped regions surrounding the floating body The floating body provides a distributed capacitance and resistance along its length to form an integrated RC circuit. The extent of the resistance is a function of the cross-sectional area of the floating body along the source and drain regions and its capacitance is a function of the spacing between the doped regions and the body and between the gate and the body. In some embodiments of the present invention, compensation for input voltage variations may be achieved.

Abstract: A semiconductor device monitor structure is described which can detect localized defects due to floating-body effects, particularly on SOI device wafers. The monitor structure includes a plurality of cells containing PFET or NFET devices, disposed at a perimeter of the structure which is bordered by an insulating region such as shallow trench isolation (STI). Each cell includes polysilicon gate structures having a characteristic spacing given by a first distance, and a portion extending beyond the perimeter a second distance. The cells are constructed in accordance with progressively varying ground rules, so that the first distance and second distance are non-uniform between cells. The cells may be bit fail mapped for single-cell failures, thereby enabling detection of localized defects due to floating-body effects.

Abstract: In a semiconductor device using a crystalline semiconductor film on a substrate 106 having an insulating surface, impurities are locally implanted into an active region 102 to form a pinning region 104. The pinning region 104 suppresses the spread of a depletion layer from the drain side to effectively prevent the short-channel effect. Also, since a channel forming region 105 is intrinsic or substantially intrinsic, a high mobility is realized.

Abstract: A semiconductor device of SOI structure comprises a surface semiconductor layer in a floating state, which is stacked on a buried insulating film so as to construct an SOI substrate, source/drain regions of second conductivity type which are formed in the surface semiconductor layer, a channel region of first conductivity type between the source/drain regions and a gate electrode formed on the channel region through a gate insulating film; wherein the surface semiconductor layer has a potential well of the first conductivity type formed therein at and/or near at least one end of the channel region in a gate width direction thereof.

Abstract: A semiconductor integrated circuit includes: a logic circuit section including transistors formed on an SOI substrate; and a partially-depletion-type transistor, which is formed on the SOI substrate as a switching transistor for controlling ON/OFF states of the logic circuit section and which has a body contact portion. The partially-depletion-type transistor has a threshold voltage, which is substantially equal to that of the transistors in the logic circuit section when no potential is applied to the body contact portion and which is higher than that of the transistors in the logic circuit section when a potential is applied to the body contact portion.

Abstract: A silicon-on-insulation (SOI) body contact is formed within a device region of an SOI substrate so that no space of the SOI substrate is wasted for implementing a body contact. The body contact is formed by epitaxially growing silicon and depositing polysilicon. An electrical device can be formed to overlie the body contact. Thus, no additional circuitry or conductive path is required to electrically connect a body contact and a device region. Also, the body contact provides a predictable electrical characteristics without sacrificing the benefits attained from using the SOI substrate and conservation surface space on the semiconductor die.

Abstract: A silicon-on-insulator (SOI) device structure 100 formed using a self-aligned body tie (SABT) process. The SABT process connects the silicon body of a partially depleted (PD) structure to a bias terminal. In addition, the SABT process creates a self-aligned area of silicon around the edge of the active areas, as defined by the standard transistor active area mask, providing an area efficient device layout. By reducing the overall gate area, the speed and yield of the device may be increased. In addition, the process flow minimizes the sensitivity of critical device parameters due to misalignment and critical dimension control. The SABT process also suppresses the parasitic gate capacitance created with standard body tie techniques.

Abstract: According to the present invention, there is provided an N-type insulated gate field effect transistor using an SOI substrate of which Si layer as a device formation area is N-type. The SOI substrate provided as the device formation area has the N-type semiconductor region, which has an impurity concentration higher than the impurity concentration of the device formation area, formed so that the N-type semiconductor region is contacted to a part of a gate insulating film and a field silicon oxide film formed between a source electrode and a drain electrode, and extends to be contacted to the N-type semiconductor diffusion layer contacted to the drain electrode. According to the above arrangement, the on-state breakdown can be remarkably improved.

Abstract: A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD.

Abstract: A flat panel display device with improved electrical characteristics and a simplified manufacturing process is disclosed. The device includes a semiconductor layer formed on an insulating substrate; source and drain electrodes directly contacting both end portions of the semiconductor layer, respectively; a pixel electrode having an opening portion formed thereon; a first insulating layer formed over the remaining portion of the insulating substrate except for the opening portion; a gate electrode formed on a portion of the first insulating layer over the semiconductor layer; and source and drain regions formed in both end portions of the semiconductor layer.

Abstract: Silicon on insulator technology and strained silicon technology provide semiconductor devices with high performance capabilities. Shallow trench isolation technology provides smaller devices with increased reliability. Bulk silicon technology provides devices requiring deep ion implant capabilities and/or a high degree of thermal management. A semiconductor device including silicon on insulator regions, strained silicon layer, shallow trench isolation structures, and bulk silicon regions is provided on a single semiconductor substrate.

Abstract: Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. Respective ones of the recessed regions are located on respective opposite sides of the gate. Each of the recessed regions define a sidewall and a floor. An elevated source/drain structure on each of the recessed regions is at least as thick adjacent to the gate as remote from the gate. A gate spacer may be included between the gate and the elevated source/drain region. The gate spacer can comprise an insulating film. Preferably, the source/drain structure extends to the sidewall of the recessed region. The elevated source/drain structure is preferably free of a facet adjacent the gate. The present invention also relates to methods for fabricating a field effect transistors (FET) having an elevated source/drain structure.

Abstract: Methods and apparatus are provided for creating field effect transistor (FET) body connections with high-quality matching characteristics and no area penalty for partially depleted silicon-on-insulator (SOI) circuits. The FET body connections are created for partially depleted silicon-on-insulator (SOI) technologies by forming adjacent FET devices inside a shallow trench shape. The adjacent FET devices share a common diffusion area, such as source or drain. Selectively spacing apart adjacent gate lines form an underpath connecting bodies of the adjacent FET devices. The underpath is defined by forming an undepleted region on top of a buried oxide layer. The adjacent polysilicon gate lines are selectively spaced apart to define a depth of depletion in a shared diffusion region for creating the underpath. Also, adjacent FET devices with connecting bodies can be built by adding an ion implant masking step to the fabrication process. This masking step changes the depletion depth under the shared diffusion area.

Abstract: CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1−xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1−xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peal Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1−xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1−xGex layer varies from the peak level where 0.

Abstract: A method and structure for a silicon on insulator (SOI) device with a body contact are provided. The body contact is formed by epitaxial growth from a substrate to the body region of the device. The body contact is self-aligned with the gate of the device and is buried within an isolation region outside of the active area of the device. Thus, the body contact does not increase parasitic capacitance in the device, not does the body contact affect device density. No additional metal wiring or contact holes are required.