Abstract: A display device including a peripheral circuit portion with high operation stability. The display device includes a first substrate and a second substrate. A first insulating layer is on a first plane of the first substrate, and a second insulating layer is on a first plane of the second substrate. An area of the first plane of the first substrate is the same as an area of the first plane of the second substrate. The first plane of the first substrate and the first plane of the second substrate face each other. A bonding layer is between the first insulating layer and the second insulating layer. A protection film is in contact with the first substrate, the first insulating layer, the bonding layer, the second insulating layer, and the second substrate.

Abstract: A pixel is included, the pixel including a photoelectric conversion portion configured to convert incident light to a charge by photoelectric conversion and accumulate the charge, a charge transfer unit configured to transfer the charge generated in the photoelectric conversion portion, a diffusion layer to which the charge is transferred through the charge transfer unit, the diffusion layer having a predetermined storage capacitance, a conversion unit configured to convert the charge transferred to the diffusion layer to a pixel signal, and connection wiring configured to connect the diffusion layer and the conversion unit. The connection wiring is connected to the diffusion layer and the conversion unit through contact wiring extending in a vertical direction with respect to a semiconductor substrate on which the diffusion layer is formed and is formed closer to the semiconductor substrate than other wiring provided in the pixel.

Abstract: An array substrate and a method for producing the same are disclosed. The array substrate includes a metal pattern and an electrically conductive pattern sequentially formed on a base substrate, the electrically conductive pattern being insulated from the metal pattern. The array substrate further includes a static charge releasing pattern formed in a same layer and made of a same material as the electrically conductive pattern, and which is insulated from the electrically conductive pattern. The metal pattern is a signal line running through a display area of the array substrate, and includes an input end, an output end, and a body portion between the input end and the output end. The output end of the signal line includes an island-like structure, and a width of the island-like structure is greater than that of the body portion. The static charge releasing pattern is electrically connected with the island-like structure.

Abstract: A highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics, and a manufacturing method thereof. In the manufacturing method of the semiconductor device which includes a thin film transistor where a semiconductor layer including a channel formation region is an oxide semiconductor layer, heat treatment which reduces impurities such as moisture to improve the purity of the oxide semiconductor layer and oxidize the oxide semiconductor layer (heat treatment for dehydration or dehydrogenation) is performed. Not only impurities such as moisture in the oxide semiconductor layer but also those existing in a gate insulating layer are reduced, and impurities such as moisture existing in interfaces between the oxide semiconductor layer and films provided over and under and in contact with the oxide semiconductor layer are reduced.

Abstract: In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed as an elongated element that is formed into a pattern of a spiral. An embodiment of the pattern of the resistor includes a plurality of revolutions from the starting point to an ending point. The resistor material has one of a separation distance between adjacent revolutions that increases with distance along a periphery of the resistor material or a width of the resistor material that increases with distance along the periphery of the resistor material.

Abstract: A manufacturing method of TFT substrate and a TFT substrate are provided. The method provides a dual-gate structure symmetrically disposed on both sides of active layer, which prevents TFT threshold voltage from changing and improve TFT conduction state switching; by first manufacturing the active layer before the gate insulating layer to make the insulating layer directly grow on active layer, the contact interface between the gate insulating layer and active layer is improved, leading to further improving TFT conduction state switching. The TFT substrate makes the gate located between the source and the pixel electrode in vertical direction, and the dual-gate is symmetrically disposed on both sides of active layer to prevent TFT threshold voltage from changing and improve TFT conduction state switching, as well as improve the contact interface between the gate insulating layer and active layer, leading to further improving TFT conduction state switching.

Abstract: A display device includes a flexible substrate including a first surface and a second surface facing the first surface; a TFT array layer provided on the first surface; a display element layer provided on the TFT array layer; a first heat releasing layer provided on the second surface; a first protective layer provided on the same side as the second surface; a second heat releasing layer provided on the display element layer; and a second protective layer provided on the display element layer. The second heat releasing layer has a light transmittance of 90% or higher.

Abstract: A novel, highly convenient or reliable functional panel is provided. A novel, highly convenient or reliable method for manufacturing a functional panel is provided. The functional panel includes a first base; a second base having a region overlapping with the first base; a bonding layer that bonds the first base to the second base; and an insulating layer in contact with the first base, the second base, and the bonding layer. With this structure, an opening which is formed easily in a region where the bonding layer is in contact with the first base or the second base can be filled with the insulating layer, which can prevent impurities from being diffused into the functional layer located in a region surrounded by the first base, the second base, and the bonding layer that bonds the first base to the second base.

Abstract: A memory structure including a SOI substrate, a first transistor, a second transistor, an isolation structure and a capacitor is provided. The SOI substrate includes a silicon base, a dielectric layer and a silicon layer. The first transistor and the second transistor are disposed on the silicon layer. The isolation structure is disposed in the silicon layer between the first transistor and the second transistor. The capacitor is disposed between the first transistor and the second transistor. The capacitor includes a body portion, a first extension portion, a second extension portion and a third extension portion. The first extension portion extends from the body portion to a source/drain region of the first transistor. The second extension portion extends from the body portion to a source/drain region of the second transistor. The third extension portion extends from the body portion, penetrates through the isolation structure and extends into the dielectric layer.

Abstract: A method, apparatus and system are described providing a high dynamic range pixel. An integration period has multiple sub-integration periods during which charges are accumulated in a photosensor and repeatedly transferred to a storage node, where the charges are accumulated for later transfer to another storage node for output.

Abstract: A manufacturing method of a capacitor structure includes the following steps. A first capacitor is formed on a substrate. The first capacitor includes a first electrically conductive pattern and a second electrically conductive pattern of a first electrically conductive layer and a first dielectric layer disposed therebetween in a horizontal direction. A second capacitor is formed on the substrate before forming the first capacitor. The second capacitor includes a third electrically conductive pattern and a fourth electrically conductive pattern of a second electrically conductive layer and a second dielectric layer disposed therebetween in the horizontal direction. A thickness of the second electrically conductive layer is monitored. A target value of a thickness of the first electrically conductive layer is controlled in accordance with a value of a monitored thickness of the second electrically conductive layer.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method is performed by forming a gate structure over a substrate, and selectively implanting the substrate according to the gate structure to form first and second source/drain regions on opposing sides of the gate structure. A first MEOL structure is formed on the first source/drain region and a second MEOL structure is formed on the second source/drain region. The first MEOL structure has a bottommost surface that extends in a first direction from directly over the first source/drain region to laterally past an outermost edge of the first source/drain region. A conductive structure is formed to contact the first MEOL structure and the second MEOL structure. The conductive structure laterally extends from directly over the first MEOL structure to directly over the second MEOL structure along a second direction perpendicular to the first direction.

Abstract: A display substrate, a method of manufacturing the same and a display device are provided. The display substrate includes: a base substrate including an emission area and a transmission area; an electroluminescent device on the base substrate, the electroluminescent device including a first electrode in the emission area; a thin film transistor for controlling the electroluminescent device, the thin film transistor including an active layer; and a conductive member on the base substrate. The conductive member electrically connects the first electrode of the electroluminescent device with the active layer, the conductive member includes a contact portion in contact with the active layer, and the contact portion is located in the transmission area.

Abstract: A chip includes a first gate extended along a second lateral direction, a first source electrically coupled to a power rail, and a first metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction, wherein the first metal interconnect lies above the first gate and the first source, and the first metal interconnect is configured to electrically couple the first gate to the first source. The chip also includes a second gate extended along the second lateral direction, a second source electrically coupled to the power rail, and a second metal interconnect extended along the first lateral direction, wherein the second metal interconnect lies above the second gate and second source, the second metal interconnect is configured to electrically couple the second gate to the second source, and the first metal interconnect is aligned with the second metal interconnect in the second lateral direction.

Abstract: An image display device includes a plurality of micro light-emission elements that constitute a pixel and that are provided on a driving circuit substrate. The micro light-emission element displays an image by emitting light to a side opposite to the driving circuit substrate. A light convergence portion that converges light is disposed in the pixel.

Abstract: Integrated circuits include a first conductive structure at a first level of the integrated circuit, a second conductive structure at a second level of the integrated circuit, a first conductor at a third level of the integrated circuit between the first level and the second level, a second conductor at the third level and parallel to the first conductor, and a third conductor at the third level and parallel to the first conductor and to the second conductor. The first conductive structure is in physical and electrical contact with the first conductor and the second conductor. The second conductive structure is in physical and electrical contact with the second conductor and the third conductor.

Abstract: The present disclosure relates to an active illuminating display panel and a manufacturing method thereof. The light-emitting layer is configured to emit the red light or the green light instead of the blue light. The energy of the red light photons and the green light photons is lower than the energy of the blue light photons. As such, the high molecular organic material in the light-emitting layer may not decay easily and the lifecycle of the active illuminating display panel may be extended.

Abstract: The present disclosure provides a poly-silicon thin film and a preparation method of a thin film transistor, the method including: providing a substrate, and forming an amorphous silicon thin film on the substrate; placing the amorphous silicon thin film in air for oxidization so as to form an oxide film on the amorphous silicon thin film; etching the oxide film with hydrofluoric acid, and reserving part of the oxide film after etching; and carrying out excimer laser treatment on the amorphous silicon thin film to form a poly-silicon thin film.

Abstract: Disclosed herein is a circuit comprising a first thin film transistor (TFT) and storage capacitor having a first electrode and a second electrode configured to face to each other. A second TFT is coupled to the capacitor, wherein a first gate electrode of the first TFT, a first electrode of the storage capacitor and a second gate electrode of the second TFT are integrally formed.

Abstract: A display panel and a method for fabricating the same are provided. The display panel includes: a TFT array substrate; an OLED array disposed on the TFT array substrate, a package layer which covers the OLED array, an upper protection layer covering the package layer, and a lower protection layer. In a first direction, a first projection of the OLED array on the TFT array substrate is located within a second projection of the package layer on the TFT array substrate, and there is a first distance between a boundary of the first projection and a boundary of the second projection. Also in the first direction, the second projection is located within a third projection of the upper protection layer on the TFT array substrate, and there is a second distance between the boundary of the second projection and a boundary of the third projection.

Abstract: An electronics package includes an insulating substrate and electrical components coupled to a first surface of the insulating substrate. A multi-thickness conductor layer is formed on a second surface of the insulating substrate opposite the first surface. The multi-thickness conductor layer extends through vias in the insulating substrate to connect with contact pads of the electrical components. The multi-thickness conductor layer has a first thickness in a region proximate the first electrical component and a second thickness in a region proximate the second electrical component, the first thickness greater than the second thickness. The electronics package also includes a first redistribution layer having a conductor layer formed atop a portion of the multi-thickness conductor layer having the second thickness. A top surface of the conductor layer is co-planar with or substantially co-planar with a top surface of a portion of the multi-thickness conductor layer having the first thickness.

Abstract: A display device includes a flexible substrate including a first surface and a second surface facing the first surface; a TFT array layer provided on the first surface; a display element layer provided on the TFT array layer; a first heat releasing layer provided on the second surface; a first protective layer provided on the same side as the second surface; a second heat releasing layer provided on the display element layer; and a second protective layer provided on the display element layer. The second heat releasing layer has a light transmittance of 90% or higher.

Abstract: A light-emitting device can be folded in such a manner that a flexible light-emitting panel is supported by a plurality of housings which are provided spaced from each other and the light-emitting panel is bent so that surfaces of adjacent housings are in contact with each other. Furthermore, in the light-emitting device, in which part or the whole of the housings have magnetism, the two adjacent housings can be fixed to each other by a magnetic force when the light-emitting device is used in a folded state.

Abstract: An organic light-emitting diode (OLED) display and a method of manufacturing an OLED display are disclosed. In one aspect, the method includes forming a data electrode layer and patterning the data electrode layer so as to form a source electrode, a drain electrode, and a pad electrode. The method can also include forming a first organic insulating layer over the source, drain and pad electrodes and forming a via hole corresponding to the source electrode or the drain electrode in the first organic insulating layer via a one tone mask. The method can further include forming an OLED including an anode electrically connected to the source electrode or the drain electrode, an organic emission layer, and a cathode, and etching a first portion of the first organic insulating layer formed over the pad electrode and a second portion of the organic emission layer formed over the pad electrode.

Abstract: A multilayer device includes a substrate and a first layer disposed on the substrate. A trench extends through one or both of the substrate and the first layer. The trench has a first sidewall spaced apart from a second sidewall, each sidewall extending from an upper surface of the substrate to a lower surface of the first layer. An optically active region is disposed on the first layer overlying the trench, such that at least a portion of the optically active region is located within a set of lines corresponding to the sidewalls of the trench.

Abstract: The present technique relates to a solid-state imaging element and a driving method and electronic equipment that enable sufficient extension of the dynamic range and obtention of an image with higher quality. In a unit pixel, a first photoelectric converter and a second photoelectric converter are provided. Furthermore, a charge accumulating part is connected to the second photoelectric converter with the intermediary of a second transfer gate part and a charge obtained by photoelectric conversion in the second photoelectric converter is transferred to the charge accumulating part via the second transfer gate part. Moreover, an anti-blooming gate part is connected to the second photoelectric converter and the second photoelectric converter can be reset.

Abstract: A composite electronic component that includes an insulation substrate having a principal surface; a thin-film capacitor on the principal surface of the insulation substrate; a laminated insulation protection layer covering the thin-film capacitor; a first extended wiring in the insulation protection layer and connected to the thin-film capacitor; a first resin layer on the insulation protection layer, first and second thin-film resistors in the first resin layer; a through-hole penetrating the first resin layer in a thickness direction thereof so as to expose the first extended wiring; a first rewiring in the first resin layer and connected to the first extended wiring through the through-hole; and a second resin layer on the first resin layer. The interior of the through-hole is filled with the second resin layer, and the through-hole does not overlap the thin-film capacitor.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: An organic light-emitting display apparatus includes a substrate and an active layer disposed on the substrate. The active layer includes a source region, a drain region, and a channel region disposed between the source region and the drain region. A gate electrode overlaps the channel region. An auxiliary gate electrode is disposed between the gate electrode and the channel region. A first voltage is applied to the auxiliary gate electrode. A first thin-film transistor includes the active layer, the auxiliary gate electrode, and the gate electrode.

Abstract: A display apparatus includes a substrate having a plurality of pixel areas, and a pixel circuit including a storage capacitor and a plurality of thin film transistors (TFTs) which are disposed in each pixel area. At least one of the plurality of TFTs includes a semiconductor layer disposed on the substrate and including a first ion impurity, a source area and a drain area, which are spaced apart from each other, have a first depth from a surface of the semiconductor layer, and include a second ion impurity, a gate electrode disposed on the semiconductor layer between the source area and the drain area, and a bias wiring electrically connected to the semiconductor layer and disposed adjacent to at least one of the source area and the drain area.

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film.

Abstract: A display device includes a substrate divided into an encapsulation area and a non-encapsulation area. The display device includes an interlayer insulating layer disposed over the substrate. The display device includes a first inner contact hole passing through the interlayer insulating layer in the encapsulation area, and connecting an inner conductive layer to an inner lower conductive layer. The display device includes an outer contact hole passing through the interlayer insulating layer in the non-encapsulation area, and connecting an outer conductive layer to an outer lower conductive layer. A slope angle formed by a lateral wall of the outer contact hole with respect to an upper surface of the substrate is less than a slope angle formed by a lateral wall of the first inner contact hole with respect to the upper surface of the substrate.

Abstract: An imaging element which is capable of obtaining a piece of image data by performing light exposure plural times is provided. In addition, an imaging element which is capable of obtaining image data with little noise is provided. Furthermore, an imaging device with reduced power consumption is provided. In an imaging element including a pixel, the pixel includes a photodiode, a transistor including an oxide semiconductor layer, a diode, and a charge retention portion. The polarity of an electrode of the photodiode which is connected to the transistor is the same as that of an electrode of the diode which is connected to the transistor.

Abstract: An array substrate is disclosed. The array substrate includes a substrate, a first film layer on a side surface of the substrate, an insulation layer on the side surface of the substrate, an electrostatic charge dispersion layer on the side surface of the substrate, and a second film layer arranged on the side surface of the substrate. The first film layer, the insulation layer, the electrostatic charge dispersion layer, and the second film layer are sequentially arranged on the substrate. In addition, the insulation layer and the electrostatic charge dispersion layer include via holes, the second film layer is electrically connected with the first film layer through the via holes, and the electrostatic charge dispersion layer is in a same profile as the second film layer.

Abstract: A semiconductor device includes a drift layer of a first conductivity-type, having a super junction structure, including a plurality of columns of a second conductivity-type, a plane pattern of each of the columns extends along a parallel direction to the principal surface of the layer, the columns are arranged at regular intervals; a plurality of well regions of the second conductivity-type provided in a surface-side layer of the layer of the first conductivity-type; a plurality of source regions of the first conductivity-type selectively provided in the plurality of well regions; a gate insulating film provided on the principal surface; an array of gate electrodes disposed on the gate insulating film, each of the gate electrodes is provided so as to bridge the corresponding source regions in a pair of neighboring two well regions; and a temperature detection diode provided at a partial area defined in the array of the gate electrodes.

Abstract: Some embodiments include a resistor that may be used in audio conversion for an ADC. The resistor may be made up of an n-well as well as a p-well polysilicons. The n-well and p-well polysilicons may include a shallow trench isolator. The n-well and p-well components may be in series with other n-well or p-well components respectively. Similarly, multiple n-well components which are in series, may be in parallel with multiple p-well components.

Abstract: A method of fabricating a metal-insulator-metal (MIM) capacitor reduces the number of masks and processing steps compared to conventional techniques. A conductive redistribution layer (RDL) is patterned on a semiconductor chip. A MIM dielectric layer is deposited over the RDL. A first conductive layer of a MIM capacitor is deposited over the MIM dielectric layer. The MIM dielectric layer is patterned using a MIM conductive layer mask. The conductive redistribution layer includes two RDL nodes that extend under the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

Abstract: A solid-state image sensor including a substrate having a photoelectric conversion element disposed therein, the photoelectric conversion element converting an amount of incident light into a charge amount, a memory unit disposed at a side of the photoelectric conversion element, the memory unit receiving the charge amount from the photoelectric conversion element, a first light-shielding section formed at a first side of the memory unit and disposed between the charge accumulation region and the photoelectric conversion element, and a second light-shielding section formed at a second side of the memory unit such that the second side is opposite the first side.

Abstract: In an organic electroluminescent device, deterioration of an organic material layer of an OLED due to moisture and the like from a surrounding material is effectively prevented. An OLED is provided with an organic material layer including a light emitting layer and is provided on a lower substrate. A first diamond-like carbon layer is provided between the lower substrate and the organic material layer and is at least arranged in a light emitting area in a surface along the lower substrate. A second diamond-like carbon layer is provided above the organic material layer and is at least arranged in the light emitting area.

Abstract: In the present invention, At least one row of lens arrays, in which a plurality of lenses are arranged in a direction intersecting with the conveying direction of a substrate to correspond to the plurality of TFT forming areas set in a matrix on the substrate, is shifted in the direction intersecting with the conveying direction of the substrate, to thereby align the lenses in the lens array with the TFT forming areas on the substrate based on the alignment reference position. The laser beams are irradiated onto the lens array when the substrate moves and the TFT forming areas reach the underneath of the corresponding lenses of the lens array, and the laser beams are focused by the plurality of lenses to anneal the amorphous silicon film in each TFT forming area.

Abstract: Disclosed is a process of making field-effect transistor gate stacks containing different deposited thin film silicon material layers having different hydrogen content, and devices comprising these gate stacks. The threshold voltage (Vt) can be tuned by tailoring the hydrogen content of the thin film silicon material layer positioned below a core dielectric and directly on a semiconductor material substrate.

Abstract: Disclosed is a process of making field-effect transistor gate stacks containing different deposited thin film silicon material layers having different hydrogen content, and devices comprising these gate stacks. The threshold voltage (Vt) can be tuned by tailoring the hydrogen content of the thin film silicon material layer positioned below a core dielectric and directly on a semiconductor material substrate.

Abstract: The present disclosure relates to a photo sensor module. The thickness and size of an IC chip may be reduced by manufacturing a photo sensor based on a semiconductor substrate and improving the structure to place a UV sensor on the upper section of an active device or a passive device. The photo sensor module includes a semiconductor substrate, a field oxide layer, formed on the semiconductor substrate, and a photo sensor comprising a photo diode formed on the field oxide layer.

Abstract: A semiconductor device includes: a substrate; a power rail on the substrate; an active layer on the substrate and at same layer as the power rail; and a contact electrically connecting the power rail to the active layer. The active layer includes source/drain terminals.

Abstract: To provide a semiconductor device which can be miniaturized or highly integrated. To obtain a semiconductor device including an oxide semiconductor, which has favorable electrical characteristics. To provide a highly reliable semiconductor device including an oxide semiconductor, by suppression of a change in its electrical characteristics. The semiconductor device includes an island-like oxide semiconductor layer over an insulating surface; an insulating layer surrounding a side surface of the oxide semiconductor layer; a source electrode layer and a drain electrode layer in contact with top surfaces of the oxide semiconductor layer and the insulating layer; a gate electrode layer overlapping with the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode layer. The source electrode layer and the drain electrode layer are provided above the top surface of the oxide semiconductor layer. The top surface of the insulating layer is planarized.

Abstract: An integrated circuit containing a PMOS transistor may be formed by implanting boron in the p-channel source drain (PSD) implant step at a dose consistent with effective channel length control, annealing the PSD implant, and subsequently concurrently implanting boron into a polysilicon resistor with a zero temperature coefficient of resistance using an implant mask which also exposes the PMOS transistor, followed by a millisecond anneal.

Abstract: A semiconductor device (300a) comprising: a substrate (302) having a first surface (303); an n-type well (304) extending from the first surface (303) into the substrate (302) and configured to form a depletion region (306) in the substrate (302) around the n-type well (304); an insulating layer (340) extending over the first surface (303) of the substrate (302) from the n-type well (304), the insulating layer (340) configured to form an inversion layer (342) in the substrate (302) extending from the n-type well (304) adjacent to the first surface (303); wherein a p-type floating channel stopper (370a) is provided, configured to extend through the inversion layer (342) to reduce electrical coupling between the n-type well (304) and at least part of the inversion layer (342), and is electrically disconnected from a remainder of the substrate (320) outside of the depletion region (306).

Abstract: A solid-state image sensor including a substrate having a photoelectric conversion element disposed therein, the photoelectric conversion element converting an amount of incident light into a charge amount, a memory unit disposed at a side of the photoelectric conversion element, the memory unit receiving the charge amount from the photoelectric conversion element, a first light-shielding section formed at a first side of the memory unit and disposed between the charge accumulation region and the photoelectric conversion element, and a second light-shielding section formed at a second side of the memory unit such that the second side is opposite the first side.

Abstract: To provide a semiconductor device which can be miniaturized or highly integrated. To obtain a semiconductor device including an oxide semiconductor, which has favorable electrical characteristics. To provide a highly reliable semiconductor device including an oxide semiconductor, by suppression of a change in its electrical characteristics. The semiconductor device includes an island-like oxide semiconductor layer over an insulating surface; an insulating layer surrounding a side surface of the oxide semiconductor layer; a source electrode layer and a drain electrode layer in contact with top surfaces of the oxide semiconductor layer and the insulating layer; a gate electrode layer overlapping with the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode layer. The source electrode layer and the drain electrode layer are provided above the top surface of the oxide semiconductor layer. The top surface of the insulating layer is planarized.

Abstract: The present invention relates to a driver and a display device including the same, wherein the driver includes: a first driving circuit generating a first output signal; a second driving circuit generating a second output signal; and at least one buffer circuit generating a third output signal of a voltage level corresponding to a gate-on voltage level of the first output signal or the second output signal when the first output signal or the second output signal is transmitted as a gate-on voltage level, and the buffer circuit includes a first transistor transmitting the voltage of the first level as the third output signal, and a second transistor transmitting the voltage of a second level turning off the first transistor and connected to the gate electrode of the first transistor.