Including Resistor Element Patents (Class 257/358)
  • Patent number: 11373997
    Abstract: An HVIC is a gate driver IC that drives a three-phase inverter and includes high-potential-side regions for three phases on a single semiconductor substrate. The high-potential-side region includes an n-type region and has a potential that is fixed at a power source voltage potential through a VB contact region in the n-type region. The high-potential-side region has a high-side driving circuit that drives an upper arm element of the inverter. An interphase region between adjacent high-potential-side regions has no GND contact region and no GND contact electrode arranged therein, and has only a p-type region at a ground potential constituting a low-potential-side region. The high-potential-side region of one phase has a p?-type opening between the high-side driving circuit of thereof and the high-side driving circuit or the GND contact region of an adjacent high-potential-side region that is of another phase and sandwiches the interphase region therebetween.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: June 28, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu Yamaji
  • Patent number: 11133232
    Abstract: A semiconductor device is provided. The semiconductor device includes a functional circuit; a plurality of electrostatic discharge (ESD) protection circuits formed independently of the functional circuit, wherein each of the plurality of ESD protection circuits includes a plurality of junctions having different sizes and capacities, each of the plurality of ESD protection circuits is configured to perform an ESD test in different processes of fabrication of the semiconductor device; and a plurality of test pads connected to the plurality of ESD protection circuits and the functional circuit, respectively, wherein each of the plurality of test pads is configured to receive a test signal for the ESD test.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ae-Nee Jang, Seung-Duk Baek
  • Patent number: 10930638
    Abstract: The disclosure provides a semiconductor device that can reduce the area of the circuit elements formed thereon. The semiconductor device includes a first conductivity type region formed on a substrate and formed with a resistance element surrounded by an insulating film; a second conductivity type region laminated in contact with an upper surface of the resistance element; a capacitor formed on the resistance element via an interlayer insulating layer; a via electrically connecting a terminal of the resistance element and a terminal of the capacitor in series; and a power supply line and a ground line electrically connected to the other terminal of the resistance element and the other terminal of the capacitor respectively.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: February 23, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Chikashi Fuchigami
  • Patent number: 10854596
    Abstract: An RF power limiter and ESD protection circuit has a set of two CMOS FETs each configured to perform a diode function with a defined forward voltage and arranged in an anti-parallel configuration and coupled between the input terminal and the ground terminal. When an RF signal is applied symmetrically to the input terminal and ground terminal it becomes symmetrically attenuated when the signal level exceeds the defined forward voltage of the diode configured CMOS FETs. In the ESD protection mode one of the CMOS FETs acts as a grounded gate NMOS transistor with SCR action to provide for mitigation of voltage and current over-stress of transistors utilized in RF transceiver circuits. Generally, the circuit architectures allow input power levels to be limited to an extent that reliable operation can be maintained.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: December 1, 2020
    Assignee: BeRex, Inc.
    Inventors: Oleksandr Gorbachov, Lisette L. Zhang, Stephen Milkovits
  • Patent number: 10833082
    Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Tse-Hua Lu
  • Patent number: 10784193
    Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: September 22, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Qi-Zhong Hong, Honglin Guo, Benjamin James Timmer, Gregory Boyd Shinn
  • Patent number: 10593661
    Abstract: An electronic circuit includes an electronic device, an input/output terminal, and a protection device. The electronic device includes a signal terminal to receive an input signal. The input/output terminal is configured to receive the input signal from a source external to the electronic circuit. The protection device is coupled to the electronic device and to the input/output terminal. The protection device is configured to protect the electronic device from voltage of the input signal exceeding a threshold. The protection device includes a first semiconductor region, a first contact, and a second contact. The first contact connects the first semiconductor region to the input/output terminal. The second contact connects the first semiconductor region to the signal terminal of the electronic device.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: March 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Robert Callaghan Taft, Tobias Hoehn, Karim Thomas Taghizadeh Kaschani
  • Patent number: 10587266
    Abstract: The present disclosure provides a level-shift circuit and a display device. The level-shift circuit includes a logic setting unit, a control unit, a first field effect transistor, a second field effect transistor, and an over-current protection module. An input terminal of the logic setting unit is input with an initial signal. An output terminal of the logic setting unit is connected with an input terminal of the control unit. The over-current protection module is configured to reduce a resistance of the level-shift circuit when the level-shift circuit is in an initial stage, and increase the resistance of the level-shift circuit when the level-shift circuit is in a working stage.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: March 10, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Xianming Zhang, Yu-Hua Chang
  • Patent number: 10504896
    Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Tse-Hua Lu
  • Patent number: 10411006
    Abstract: A semiconductor device includes an active device of a transistor disposed in a semiconductor substrate. An isolation layer is disposed at the semiconductor substrate, and a polysilicon substrate layer is disposed over the isolation layer and the semiconductor substrate. The polysilicon substrate layer includes a semiconductor device region of an interface protection circuit of the transistor.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: September 10, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Gernot Langguth, Adrien Ille
  • Patent number: 10340289
    Abstract: An amplifier includes a cascode structure comprising a first transistor having first characteristics coupled to a second transistor having second characteristics different than the first characteristics, the first transistor formed with the second transistor on a single diffusion.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: July 2, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Ranadeep Dutta, Antonino Scuderi, Wing Sy
  • Patent number: 10236286
    Abstract: A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 19, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Katsuyoshi Matsuura, Junichi Ariyoshi
  • Patent number: 10217809
    Abstract: The present application provides planar and stacked resistor structures that are embedded within an interconnect dielectric material in which the resistivity of an electrical conducting resistive material or electrical conducting resistive materials of the resistor structure can be tuned to a desired resistivity during the manufacturing of the resistor structure. Notably, a doped metallic insulator layer is formed atop a substrate. A controlled surface treatment process is then performed to an upper portion of the doped metallic insulator layer to convert the upper portion of the doped metallic insulator layer into an electrical conducting resistive material layer. The remaining doped metallic insulator layer and the electrical conducting resistive material layer are then patterned to provide the resistor structure.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 10121573
    Abstract: An epoxy-based resin system composition includes a latent functionality for polymer adhesion improvement. The composition may be used to produce an overcoat layer and/or protection layer in an anti-sulfur resistor (ASR). In some embodiments, the composition include epoxy-based resin(s), hardener(s) and, optionally, blowing agent(s) and/or filler(s). An epoxide functionality of one or more of the epoxy-based resin(s) and a reactive functionality of one or more of the hardener(s) react with each other at a first temperature. The latent functionality, which does not react at the first temperature, is contained in at least one of the epoxy-based resin(s), hardener(s) and filler(s) and reacts in response to another stimulus (e.g., UV light/initiator and/or a second temperature greater than the first temperature) to enhance chemical bonding. Optionally, voids created via etching and/or the blowing agent(s) may be used to enhance mechanical bonding, alone, or in combination with filler(s) exposed in the voids.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Dylan J. Boday, Joseph Kuczynski, Jason T. Wertz, Jing Zhang
  • Patent number: 9935097
    Abstract: A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: April 3, 2018
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Katsuyoshi Matsuura, Junichi Ariyoshi
  • Patent number: 9748221
    Abstract: An electrostatic discharge (ESD) protection device includes two N-metal oxide semiconductor (NMOS) elements and a doped region. The two NMOS elements are arranged on a P-substrate, and each NMOS element includes a gate, a source, and a drain. The source and the drain are arranged on two opposite sides of the gate. The doped region is implanted into an outer space of the two NMOS surrounding the two NMOS, and a PN junction is formed by the doped region and the P-substrate.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: August 29, 2017
    Assignee: Fitipower Integrated Technology, Inc.
    Inventor: Chih-Nan Cheng
  • Patent number: 9536869
    Abstract: An electrostatic discharge protection apparatus comprises a stack arrangement having a first electrostatic discharge protection element and a second electrostatic discharge protection element. The stack arrangement is arranged to provide a bias potential between the first and second electrostatic discharge protection elements. In one embodiment, the bias potential can be achieved by a clamp arrangement coupled across the stack arrangement.
    Type: Grant
    Filed: July 3, 2006
    Date of Patent: January 3, 2017
    Assignee: NXP USA, Inc.
    Inventors: Patrice Besse, Eric Rolland
  • Patent number: 9385241
    Abstract: An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad is provided. The ESD protection circuit includes a first field oxide device coupled between a first terminal that is capable of providing a first supply voltage and the I/O pad. The first field oxide device includes a drain end having a first type of dopant and a source end having the first type of dopant. The first field oxide device includes a first doped region having a second type of dopant disposed adjacent to the drain end of the first field oxide device and a second doped region having the second type of dopant disposed adjacent to the source end of the first field oxide device.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: July 5, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Chuan Lee, Kuo-Ji Chen, Wade Ma
  • Patent number: 9362420
    Abstract: The present invention discloses a transistor structure for electrostatic discharge protection. The structure includes a substrate, a doped well, a first doped region, a second doped region and a third doped region. The doped well is disposed in the substrate and has a first conductive type. The first doped region is disposed in the substrate, encompassed by the doped well and has the first conductive type. The second doped region is disposed in the substrate, encompassed by the doped well and has a second conductive type. The third doped region is disposed in the substrate, encompassed by the doped well and has the second conductive type. A gap is disposed between the first doped region and the second doped region.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: June 7, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Lu-An Chen, Tien-Hao Tang
  • Patent number: 9362270
    Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: June 7, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rajni J. Aggarwal, Jau-Yuann Yang
  • Patent number: 9343590
    Abstract: An ESD device is provided for protecting a circuit from electrostatic discharge, and includes a planar diode having an anode and a cathode. The anode is electrically coupled to a signal path of the circuit, and the cathode is electrically coupled to a ground of the circuit. The ESD device is configured to be off during normal operation of the circuit and to turn on in response to an electrostatic discharge on the signal path. Two depletion regions in the device are separated by an isolation well. In response to the electrostatic discharge, the depletion regions modulate (e.g., widen and merge), providing a path for the discharge to the ground of the circuit.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: May 17, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chien-Hsin Lee, Mahadeva Iyer Natarajan, Manjunatha Prabhu, Anil Kumar, Ruchil Kumar Jain
  • Patent number: 9343457
    Abstract: In order to provide a semiconductor device having a high ESD tolerance, a source wiring (32a) is formed on a gate (31) and a source (32) in a region of an NMOS transistor (30). The source wiring (32a) electrically connects the gate (31), the source (32), and a ground terminal. A drain wiring (33a) is formed on a drain (33) in the region of the NMOS transistor (30) . The drain wiring (33a) electrically connects the drain (33) and a pad (20) serving as an external connection electrode. Moreover, in the region of the NMOS transistor (30), the drain wiring (33a) has the same wiring width as the source wiring (32a).
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: May 17, 2016
    Assignee: STI Semiconductor Corporation
    Inventor: Tomomitsu Risaki
  • Patent number: 9263429
    Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a first doping region, a first well, a resistor element, and a first, a second, and a third heavily doping regions. The first well and the third heavily doping region are disposed in the first doping region, which is disposed on the substrate. The first heavily doping region and the second heavily doping region, which are separated from each other, are disposed in the first well. The second and the third heavily doping regions are electrically connected via the resistor element. Each of the substrate, the first well, and the second heavily doping region has a first type doping. Each of the first doping region, the first heavily doping region, and the third heavily doping region has a second type doping, complementary to the first type doping.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: February 16, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Ling Hung, Hsin-Liang Chen, Wing-Chor Chan
  • Patent number: 9231121
    Abstract: A high voltage circuit layout structure has a P-type substrate; a first N-type tub, a second N-type tub, a third N-type tub, a first P-type tub with a first width and a second P-type tub with a second width formed on the P-type substrate; wherein the first P-type tub is formed between the first N-type tub and the second N-type tub; and the second P-type tub is formed between the second N-type tub and the third N-type tub.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: January 5, 2016
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Joseph Urienza
  • Patent number: 9202808
    Abstract: An integrated circuit electrical protection device is disclosed that includes a semiconductor substrate and a plurality of transistor fingers partitioned into a plurality of segments. The segments are distinguished from one another by well-ties spaced apart from each other within a source/drain region that is shared by adjacent segments.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: December 1, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Michael A. Stockinger, Wenzhong Zhang, Xu Zhang
  • Patent number: 9159921
    Abstract: Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: October 13, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Matthew N. Rocklein, D. V. Nirmal Ramaswamy
  • Patent number: 9142543
    Abstract: An ESD protection circuit having a smaller area is provided. The ESD protection circuit includes: a P-type diffusion resistor 12 whose one end is connected to an input terminal 11 formed in the N-type well; a diode 14 disposed between the diffusion resistor 12 and the N-type well connected to the power supply terminal; an NMOS transistor 15 whose drain is connected to the other end of the diffusion resistor 12; and a parasitic diode formed between the power supply terminal and the ground terminal.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: September 22, 2015
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Takashi Katakura, Hirofumi Harada, Yoshitsugu Hirose
  • Patent number: 9123991
    Abstract: An ear-microphone for connection to a portable apparatus and use as a Frequency Modulation (FM) radio broadcast receiving antenna is provided. The ear-microphone includes an ear plug, a cable, a microphone, and a filtering unit. The ear plug is for connection to an earjack. The cable has a predefined length, has an earphone line whose one end is electrically connected to the ear plug and whose other end is electrically connected to at least one earphone. The microphone intervenes in an intermediate portion of the cable and is connected to the ear plug via a microphone line inside the cable. The filtering unit intervenes in the cable and is installed to have an Electro Static Discharge (ESD) protection function.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: September 1, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Tae-Jin Kang
  • Patent number: 9035384
    Abstract: A semiconductor device includes a first fin-shaped silicon layer on a substrate and a second fin-shaped silicon layer on the substrate, each corresponding to the dimensions of a sidewall pattern around a dummy pattern. A silicide in upper portions of n-type and p-type diffusion layers in the upper portions of the first and second fin-shaped silicon layers. A metal gate line is connected to first and second metal gate electrodes and extends in a direction perpendicular to the first fin-shaped silicon layer and the second fin-shaped silicon layer. A first contact is in direct contact with the n-type diffusion layer in the upper portion of the first pillar-shaped silicon layer, and a second contact is in direct contact with the p-type diffusion layer in the upper portion of the second pillar-shaped silicon layer.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: May 19, 2015
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9018705
    Abstract: An ESD transistor is provided. The ESD transistor includes a collector region on a substrate, a base contact region on the substrate, an emitter region spaced apart from the base contact region, a sink region disposed vertically below the collector region, and a buried layer disposed horizontally under the sink region.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: April 28, 2015
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Kyong Jin Hwang
  • Patent number: 9006838
    Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: April 14, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Rajni J. Aggarwal, Jau-Yuann Yang
  • Patent number: 8981484
    Abstract: An integrated circuit (IC) including a well region of the IC having a first doping level and a plurality of semiconductor regions implanted in the well region. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. A plurality of polysilicon regions are arranged on the plurality of semiconductor regions. The polysilicon regions are respectively connected to the semiconductor regions. The plurality of semiconductor regions is a drain of a metal-oxide semiconductor field-effect transistor (MOSFET).
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: March 17, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Ravishanker Krishnamoorthy, Siew Yong Chui
  • Patent number: 8963277
    Abstract: A semiconductor structure with a high voltage area and a low voltage area includes a substrate of a first conductivity type accommodating the high voltage area and the low voltage area. A resistor is on the substrate, connecting the high voltage area and the low voltage area, and the resistor resides substantially in the high voltage area. The structure further includes a first doped region of the first conductivity type in the substrate between the high voltage area and the low voltage area, and a second doped region of a second conductivity type between the substrate and the first doped region. Moreover, an insulating layer is formed between the resistor and the first doped region.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: February 24, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chen-Yuan Lin, Ching-Lin Chan, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 8963253
    Abstract: A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: February 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsin-Liang Chen, Shuo-Lun Tu
  • Patent number: 8916934
    Abstract: A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: December 23, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Steinhoff, Jonathan Brodsky, Thomas A. Vrotsos
  • Publication number: 20140361372
    Abstract: An input signal having a high level or a low level is input to a pad. A first protection element includes a first transistor configured as an N-channel MOSFET designed so as to withstand ESD. A second protection element includes a second transistor configured as a P-channel MOSFET designed so as to withstand ESD. A capacitance element is connected to a second line, and forms an RC filter together with a filter resistor. The capacitance element includes at least one from among a third transistor having the same device structure as that of the first transistor and a fourth transistor having the same device structure as that of the second transistor.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 11, 2014
    Applicant: ROHM CO., LTD.
    Inventor: Kenji ARAI
  • Publication number: 20140339608
    Abstract: An electrostatic discharge (ESD) protection circuit is disclosed. The circuit includes a first region having a first conductivity type (410) is formed at a face of a substrate. A gate having a second conductivity type (406) is formed in the substrate beside the first region. A channel having the first conductivity type is formed below the first region adjacent the gate. A second region having the first conductivity type (404) is formed at the face of the substrate beside the gate. A third region having the first conductivity type (430) is formed below the channel and has a greater impurity concentration than the channel.
    Type: Application
    Filed: August 1, 2014
    Publication date: November 20, 2014
    Inventor: Robert Newton Rountree
  • Patent number: 8890248
    Abstract: An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: November 18, 2014
    Assignee: Texas Instruments Incorporation
    Inventors: Timothy Patrick Pauletti, Sameer Pendharkar, Wayne Tien-Feng Chen, Jonathan Brodsky, Robert Steinhoff
  • Patent number: 8860139
    Abstract: In an aspect of the present invention, an ESD (Electrostatic Discharge) protection element includes a bipolar transistor comprising a collector diffusion layer connected with a first terminal and an emitter diffusion layer; and current control resistances provided for a plurality of current paths from a second terminal to the collector diffusion layer through the emitter diffusion layer, respectively. The bipolar transistor further includes a base diffusion region connected with the second terminal through a first resistance which is different from the current control resistances.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: October 14, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Kouichi Sawahata
  • Patent number: 8847290
    Abstract: A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 30, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeru Kusunoki, Shinichi Ishizawa
  • Patent number: 8847320
    Abstract: A device comprises a semiconductor substrate having first and second implant regions of a first dopant type. A gate insulating layer and a gate electrode are provided above a resistor region between the first and second implant regions. A first dielectric layer is on the first implant region. A contact structure is provided, including a first contact portion conductively contacting the gate electrode, at least part of the first contact portion directly on the gate electrode. A second contact portion directly contacts the first contact portion and is formed directly on the first dielectric layer. A third contact portion is formed on the second implant region.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Hui Chen
  • Patent number: 8816436
    Abstract: A fin resistor and method of fabrication are disclosed. The fin resistor comprises a plurality of fins arranged in a linear pattern with an alternating pattern of epitaxial regions. An anneal diffuses dopants from the epitaxial regions into the fins. Contacts are connected to endpoint epitaxial regions to allow the resistor to be connected to more complex integrated circuits.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Thomas N. Adam, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8797775
    Abstract: The embodiments of the present circuit and method disclose a bridge rectifier and a driving circuit. The bridge rectifier having a first input, a second input, a first output, and a second output may comprise two high side diodes and two low side switches. The driving circuit may be coupled to the first input of the bridge rectifier and the second input of the bridge rectifier, and the driving circuit may be configured to provide a first driving signal and a second driving signal. The first driving signal may be coupled to a first low side switch and the second driving signal may be coupled to a second low side switch. The first driving signal may be limited to less than a first predetermined driving voltage and the second driving signal may be limited to less than a second predetermined driving voltage.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: August 5, 2014
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventors: Yike Li, Changjiang Chen, Rui Wang
  • Patent number: 8796772
    Abstract: Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: August 5, 2014
    Assignee: Intel Corporation
    Inventors: Jeng-Ya D. Yeh, Peter J. Vandervoorn, Walid M. Hafez, Chia-Hong Jan, Curtis Tsai, Joodong Park
  • Patent number: 8753941
    Abstract: An integrated circuit with a LV transistor and a high performance asymmetric transistor. A power amplifier integrated circuit with a core transistor and a high performance asymmetric transistor. A method of forming an integrated circuit with a core transistor and a high performance asymmetric transistor. A method of forming a power amplifier integrated circuit with an nmos core transistor and an nmos high performance asymmetric transistor, a resistor, and an inductor.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: June 17, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kamel Benaissa, Vijay K. Reddy, Samuel Martin, T Krishnaswamy
  • Patent number: 8716802
    Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: May 6, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor Chiang Liang, You-Ren Liu, Chih-Chen Hsueh
  • Patent number: 8710593
    Abstract: A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor, a transitional structure, and a dielectric layer covering the transistor and the transitional structure formed thereon, forming a recess in between two opposite polysilicon end portions in the transitional structure, forming a U-shaped resistance modulating layer and an insulating layer filling the recess, removing a dummy gate of the transistor and the polysilicon end portions of the transitional structure to form a gate trench and two terminal trenches respectively in the transistor and the transitional structure, and forming a metal gate in the gate trench and conductive terminals in the terminal trenches simultaneously.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: April 29, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Sheng Tseng, Yao-Chang Wang, Jie-Ning Yang
  • Patent number: 8710589
    Abstract: An allowable current amount of a ballast resistance is increased without increasing the width of the ballast resistance. At least one of resistances included in a ballast resistance has a first resistance and a second resistance. The first resistance extends in a first direction (X direction in FIG. 1) in which current flows in a protection element. The second resistance element is coupled in parallel to the first resistance element and extends in the first direction. The second resistance element and the first resistance element are located on the same straight line.
    Type: Grant
    Filed: November 3, 2012
    Date of Patent: April 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Ko Noguchi
  • Patent number: 8704308
    Abstract: The invention provides a semiconductor device including an ESD protection circuit with a high ESD protection characteristic. An RC timer included discharge portion including an RC timer formed by a resistor element and a capacitor element and a PLDMOS transistor is formed so as to turn on only when a surge voltage due to static electricity is applied. Furthermore, a noise prevention portion including first and second NMOS off transistors of which the source electrode and the drain electrode are connected is formed. The source electrode of the PLDMOS transistor of the RC timer included discharge portion is connected to a power supply line. The drain electrode of the PLDMOS transistor and the drain electrode of the first NMOS off transistor are connected. The source electrode of the second NMOS off transistor is connected to a ground line.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: April 22, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Kazumasa Akai
  • Patent number: 8692329
    Abstract: An electric resistance element comprising: a base body, which is formed with a semiconductor material; a first contact element, which is electrically conductively connected to the base body; and a second contact element, which is electrically conductively connected to the base body. The base body has a first main surface into which a cutout is introduced. The first contact element is electrically conductively connected to the base body at least in places in the cutout. The base body has a second main surface, which is arranged in a manner lying opposite the first main surface. The second contact element is electrically conductively connected to the base body at least in places at the second main surface.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: April 8, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Krister Bergenek