Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.

Abstract: Embodiments of the disclosure provide an electrostatic discharge (ESD) device, including: an input pad; an underlapped field effect transistor (UL-FET) with a trigger voltage Vt, including: an underlapped drain region coupled to the input pad; a source region coupled to ground; and a gate structure coupled to the input pad; and a blocking layer separating the underlapped drain region from the gate structure of the UL-FET by an underlap distance.

Abstract: A device includes first and second standard cells in a layout of an integrated circuit, and first and second active regions. The first standard cell includes an electrostatic discharge (ESD) protection unit, and the second standard cell includes first and second transistors that connect to the ESD protection unit. The first active region includes first, second, and third source/drain regions. The first standard cell includes a first gate arranged across the first active region; and a second gate that is separated from the first gate and is arranged across the first active region and the second active region. The first gate, the first source/drain region and the second source/drain region together correspond to a third transistor of the ESD protection unit. The second gate, the second source/drain region and the third source/drain region together correspond to the first transistor.

Abstract: An ESD circuit is connected between an I/O pad and a first node. The ESD circuit includes a bi-directional buck circuit, a triggering circuit and a discharging circuit. The bi-directional buck circuit includes a forward path and a reverse path. The forward path and the reverse path are connected between the I/O pad and a second node. The triggering circuit is connected between the second node and the first node. The discharging circuit is connected between the second node and the first node, and connected with the triggering circuit. When the I/O pad receives negative ESD zap, the ESD current flows from the first node to the I/O pad through the discharging circuit and the reverse path. When the I/O pad receives positive ESD zap, the ESD current flows from the I/O pad to the first node through the forward path and the discharging circuit.

Abstract: Disclosed is a liquid crystal display device which can be used in a variety of situations and applications. The liquid crystal display device comprises: a first substrate comprising a first display region, a second display region, and a third display region wherein the first display region, the second display region, and the third display region are continuously formed; a second substrate having a form which fits the first substrate; and a liquid crystal interposed between the first substrate and the second substrate. The second display region is interposed between the first display region and the second display region. The second display region is curved, and the first display region and the second display region are substantially flat.

Abstract: An integrated circuit, such as a flip chip, may be configured to increase the I/O cells by stacking the I/O cells in two or more rows with external high voltage circuits on opposite sides of a respective cell to reduce the distance between the rows. In addition, the integrated circuit may include a guard ring around the I/O cells to reduce signal noise interference generated by the external high voltage circuits in the I/O cells.

Abstract: A static electricity prevention circuit of a display device including: a driving circuit configured to drive a display unit that displays an image, at least one clock signal wire configured to transmit a clock signal to the driving circuit, at least one transistor electrically coupled to the clock signal wire, and at least one capacitor including a first electrode coupled to a source electrode and to a drain electrode of the transistor, and a second electrode configured to be maintained at a voltage.

Abstract: A structure for a semiconductor device includes a dielectric layer and a metal layer. The structure also includes a plurality of unit cells. Each unit cell is formed of interconnected segments. The plurality of unit cells forms a lattice. The lattice is between the dielectric layer and the metal layer.

Abstract: A system includes: 1) a buffer circuit; 2) circuitry coupled to an input of the buffer circuit; 3) a load coupled to an output of the buffer circuit; and 4) a clamp circuit coupled between an input of the buffer circuit and the output of the buffer circuit. The clamp circuit includes: 1) a bipolar junction transistor (BJT); 2) a first resistor with a first end coupled to a base terminal of the BJT and with a second end coupled to a collector terminal of the BJT; and 3) a second resistor with a first end coupled to the collector terminal of the BJT and with a second end coupled to the input of the buffer circuit. The second resistor is between an output of the circuitry and the input of the buffer circuit.

Abstract: An input/output (I/O) circuit includes at least one I/O cell having a first size, and a high current circuit coupled to the at least one I/O cell. The high current circuit has a second size that is smaller than the first size. A connection bus is coupled to the high current circuit. The connection bus has the second size and is positioned in substantially a same location within the I/O circuit as the high current circuit. A bump or a bond pad is coupled to the connection bus.

Abstract: An electronics package includes an insulating substrate, a first electrical component coupled to a bottom surface of the insulating substrate, and a first conductor layer formed adjacent the bottom surface of the insulating substrate. The electronics package also includes a second conductor layer formed on a top surface of the insulating substrate and extending through a plurality of vias in the insulating substrate to electrically couple with the first electrical component and the first conductor layer. A second electrical component is electrically coupled to the first conductor layer and the first electrical component and the second electrical component are positioned in a stacked arrangement.

Abstract: When forming semiconductor devices, plasma-induced damage may be prevented or restricted by providing a conductive path between critical areas and the substrate of the semiconductor device. According to the present disclosure, a negative effect of any such protective structures on the performance of the semiconductor device may be significantly reduced by permanently interrupting the corresponding electrical connection at any appropriate point in time of the manufacturing sequence. Furthermore, respective fuse structures acting as current-sensitive areas may also be implemented in test structures in order to evaluate plasma-induced currents, thereby providing a possibility for a more efficient design of respective protective structures and/or for contributing to superior process control of critical plasma treatments.

Abstract: A method for manufacturing an array substrate, an array substrate, and a fingerprint recognition device. The method includes: forming a plurality of polysilicon patterns on a substrate, the plurality of polysilicon patterns including a first polysilicon pattern for forming the PIN-type diode and a second polysilicon pattern for forming the transistor, each polysilicon pattern including a first sub-region, a second sub-region, and a third sub-region between the first sub-region and the second sub-region; using a first doping process to dope the first sub-region of the first polysilicon pattern and the first sub-region and the second sub-region of the second polysilicon pattern with one of P-type ions and N-type ions respectively; and using a second doping process to dope the second sub-region of the first polysilicon pattern with the other of P-type ions and N-type ions.

Abstract: A panel device includes a substrate, a common electrode, and an electrostatic protection component. The substrate includes an active area and a peripheral area, the peripheral area is outside of the active area, and a plurality of signal lines is disposed on the substrate. The common electrode is disposed on the substrate, and at least part of the common electrode is disposed in the peripheral area. The electrostatic protection component is disposed in the peripheral area of the substrate and electrically connected to one of the plurality of signal lines and the common electrode, and the electrostatic protection component includes a first double-gate transistor. The first double-gate transistor includes a first gate, a second gate, a first electrode and a second electrode. The first gate is electrically connected to the first electrode, and the second gate is electrically connected to the second electrode.

Abstract: A semiconductor structure for electrostatic discharge (ESD) protection is provided. The semiconductor structure includes a substrate, a first doped well, a source doped region, a drain doped region, and a gate structure. The first doped well is disposed in the substrate and has a first conductive type. The source doped region is disposed in the substrate and has a second conductive type opposite to the first conductive type. The drain doped region is disposed in the substrate and has the second conductive type. The gate structure is disposed on the substrate and between the source doped region and the drain doped region. The gate structure is separated from the source doped region.

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, and first to third semiconductor regions. The third electrode is separated from the second electrode in a first direction. The first semiconductor region includes a first partial region separated from the first electrode, a second partial region separated from the second electrode, and a third partial region separated from the third electrode. The second semiconductor region includes a fourth partial region positioned between the first electrode and the first partial region, a fifth partial region positioned between the second electrode and the second partial region, and a sixth partial region positioned between the third electrode and the third partial region. The third semiconductor region includes a seventh partial region positioned between the second electrode and the fifth partial region and an eighth partial region positioned between the third electrode and the sixth partial region.

Abstract: A liquid crystal display includes scanning lines and signal lines arranged in a matrix pattern on a TFT substrate, a pixel being formed at a crossing portion of each scanning line and each signal line, and including a TFT that is connected to each scanning line and each signal line, first nonlinear resistance elements formed respectively in the scanning lines, each of which being connected to one scanning line at one end thereof and to a short ring power-supply line for a scanning line at another end thereof, and second nonlinear resistance elements formed respectively in the signal lines, each of which being connected to one signal line at one end thereof and to a short ring power-supply line for a signal line at another end thereof. A voltage is applied to the first and second nonlinear resistance elements independently of each scanning line and each signal line.

Abstract: A semiconductor device includes an insulated gate bipolar transistor (IGBT) arrangement having a first configuration region of emitter-side insulated gate bipolar transistor structures, a second configuration region of emitter-side insulated gate bipolar transistor structures, a collector layer and a drift layer. The drift layer is arranged between the collector layer and the emitter-side insulated gate bipolar transistor structures of the first configuration region and the second configuration region. The collector layer includes at least a first doping region laterally adjacent to a second doping region, the doping regions having different charge carrier life times, different conductivity types or different doping concentrations. The first configuration region is located with at least a partial lateral overlap to the first doping region, and the second configuration region is located with at least a partial lateral overlap to the second doping region.

Abstract: A power semiconductor device includes a substrate, a main body and an electrode unit. The main body includes an active portion, an edge termination portion surrounding the active portion, and an insulating layer disposed on the edge termination portion. The edge termination portion includes a first-type semiconductor region, and a plurality of spaced-apart second-type semiconductor segments distributed in the first-type semiconductor region and arranged at intervals along a Y-direction directing from the insulating layer toward the substrate, and an X-direction directing from the active portion toward the edge termination portion. The electrode unit includes a first electrode and a second electrode.

Abstract: An organic light emitting display device includes a substrate including a pixel region and a peripheral region, a first wiring, a second wiring, a third wiring, and an electrostatic protection structure including electrostatic protection diodes coupled to the first, second, and third wirings. The electrostatic protection diodes each include an active pattern, a gate electrode pattern, and a connection pattern. The active pattern is at the peripheral region of the substrate, and has a first region, a second region spaced apart from the first region, and a third region between the first and second regions. The gate electrode pattern is at the third region on the active pattern. The connection pattern is coupled to the gate electrode pattern and the active pattern and is on the gate electrode pattern, and overlaps a portion of the first region of the active pattern and a portion of the third region.

Abstract: A protection circuit includes a control circuit that controls current between a first wiring and a second wiring and an application circuit that applies a voltage to the control circuit. The control circuit includes a first thin film transistor that controls the current. The application circuit includes second and third thin film transistors that are connected in series. Each of the second and third thin film transistors includes first and second gates. The first gate of the second thin film transistor is connected to the first wiring. The first gate of the third thin film transistor is connected to a connection point between the second and third thin film transistors. The second gates of the second thin film transistor and the third thin film transistor are connected to the second wiring. The application circuit applies a voltage of the connection point to a gate of the first thin film transistor.

Abstract: A gate-less electrostatic discharge (ESD) protection device is provided that can be formed in various complementary metal-oxide-semiconductor (CMOS) systems. The gate-less ESD event protection device includes a substrate, a first doped region formed in the substrate, a second doped region extending into the first doped region, a third doped region extending into the first doped region, a first node formed over a portion of the second doped region and coupled to a source terminal and a second node formed over the third doped region and coupled to a drain terminal. The gate-less ESD protection devices can be formed such that no gate electrode is formed and the gate-less ESD protection device does not include a gate terminal. Thus, an operating voltage range of the gate-less ESD protection device is not limited by gate oxide degradation.

Abstract: A semiconductor device includes a semiconductor body having opposite first and second surfaces. The semiconductor device further includes a transistor structure in the semiconductor body and a source contact structure overlapping the transistor structure. The source contact structure is electrically connected to source regions of the transistor structure. A gate contact structure is further provided, which has a part separated from the source contact structure by a longitudinal gap within a lateral plane. Gate interconnecting structures bridge the longitudinal gap and are electrically coupled between the gate contact structure and a gate electrode of the transistor structure. Electrostatic discharge protection structures bridge the longitudinal gap and are electrically coupled between the gate contact structure and the source contact structure.

Abstract: An IC structure is provided. The IC structure includes a P-type substrate, a deep N-well region in the substrate, a first N-well region on the deep N-well region, a first N-type doped region in the first N-well region, a second N-well region in the substrate, a first P-well region in the substrate, and a discharge circuit. The second N-well region and the first P-well region are separated from the deep N-well region. The discharge circuit includes a first P-type doped region in the first P-well region, a first PMOS transistor formed in the second N-well region, a first electrical path coupled between a source of the first PMOS transistor and the first N-type doped region, and a second electrical path coupled between a drain of the first PMOS transistor and the first P-type doped region.

Abstract: An electronic device includes a package, a plurality of external leads extending outside the package, a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads, and a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads. A capacitive coupling may be positioned between the first and second die to allow electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event.

Abstract: An electrostatic discharge (ESD) protection circuit is disclosed. In this regard, an ESD protection circuit is provided to protect an integrated circuit (IC) from an ESD event. In one aspect, an ESD voltage detection circuitry activates an ESD clamping circuitry when an ESD voltage associated with faster voltage rise time is detected between a supply rail and a ground rail. In another aspect, an operation voltage detection circuitry deactivates the ESD clamping circuitry when an operation voltage associated with slower voltage rise time is detected between the supply rail and the ground rail. By differentiating the ESD voltage from the operation voltage based on respective voltage rise times, it is possible to prevent the ESD clamping circuitry from missing the ESD voltage associated with the faster voltage rise time or being falsely activated by the operation voltage associated with the slower voltage rise time.

Abstract: An electronics package includes an insulating substrate and electrical components coupled to a first surface of the insulating substrate. A multi-thickness conductor layer is formed on a second surface of the insulating substrate opposite the first surface. The multi-thickness conductor layer extends through vias in the insulating substrate to connect with contact pads of the electrical components. The multi-thickness conductor layer has a first thickness in a region proximate the first electrical component and a second thickness in a region proximate the second electrical component, the first thickness greater than the second thickness. The electronics package also includes a first redistribution layer having a conductor layer formed atop a portion of the multi-thickness conductor layer having the second thickness. A top surface of the conductor layer is co-planar with or substantially co-planar with a top surface of a portion of the multi-thickness conductor layer having the first thickness.

Abstract: Some demonstrative embodiments include devices and/or systems of a Silicon Controlled Rectifier (SCR). For example, a silicon controlled rectifier (SCR) may include a metal-oxide-semiconductor field-effect transistor (MOSFET), the MOSFET may include a gate; an N-type source region; a non-Lightly Doped Drain (LDD) N-type drain region; and a P-Well region extending between the N-type source region and the non-LDD N-type drain region, and extending between the non-LDD N-type drain region and a drain region of the gate.

Abstract: A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer.

Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; a first doped region of type one, doped in the well of type two; and a second doped region of type two, provided in the well of type one and the well of type two, not touching the first doped region of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

Abstract: Wafer to wafer alignment which includes a first semiconductor wafer and a second semiconductor wafer. The first and second semiconductor wafers have selectively-activated alignment arrays for aligning the first semiconductor wafer with the second semiconductor wafer. Each of the alignment arrays include an alignment structure which includes an antenna connected to a semiconductor device. The antenna in each of the alignment arrays is selectively activated to act as a charge source or as a charge sensing receptor. The alignment arrays are located in the kerf areas of the semiconductor wafers. The semiconductor wafers are aligned when the charge sources on one semiconductor wafer match with the charge sensing receptors on the other semiconductor wafer.

Abstract: The present disclosure provides an array substrate, a liquid crystal panel, and a manufacturing method of the array substrate. In the present disclosure, the first discharging elements and the second discharging elements are arranged on the array substrate, the first discharging elements are electrically connected to the common electrode line, and the second discharging elements are respectively electrically connected to the data lines, and the first discharging elements and the second discharging elements are simultaneously formed with the scanning lines and the data lines or are formed after the scanning lines and the data lines are formed, thus, electrostatic protection is provided to the components in the subsequent manufacturing process of the array substrate after the scanning line and the data lines are formed on the array substrate.

Abstract: According to one embodiment, a display device includes a first line extending in a first direction, an insulating layer covering the first line, a second line disposed on the insulating layer and extending in a second direction, and a drive circuit including an output line extending in the first direction and connected to the first line through a contact portion. The contact portion includes a first portion to which the first line is connected at a first position, and a second portion to which the output line is connected at a second position which is apart from the first position in the second direction, the second portion facing the first portion with the insulating layer interposed therebetween while being electrically connected to the first portion.

Abstract: A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer.

Abstract: A protection device is provided that exhibits a turn on time of order of one nanosecond or less. Such a device provides enhanced protection for integrated circuits against electrostatic discharge events. This in turn reduces the risk of device failure in use. The protection device can include a bipolar transistor structure connected between a node to be protected and a discharge path.

Abstract: A unidirectional transient voltage suppressor (TVS) device includes first and second NPN transistors that are connected in parallel to each other. Each NPN transistor includes a collector region, an emitter. The first and second NPN structures are formed on a common substrate. The first NPN transistor has a floating base and the second NPN transistor has a base shorted to an emitter.

Abstract: Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures. The first device layer is formed on a substrate and includes one or more first inverter structures. The second device layer is formed on the first device layer and includes one or more second inverter structures. The one or more inter-layer connection structures are configured to electrically connect to the first inverter structures and the second inverter structures.

Abstract: An amplifier is disclosed that avoids an increase in circuit scale and an increase in power consumption, and easily avoids the odd-order harmonics. This amplifier includes a MOS transistor including a plurality of gate fingers or a plurality of MOS transistors each including a single gate finger; a dielectric capacitor that is added to each of the gate fingers; and a variable resistor that is connected between an input terminal to which an AC signal is input, and a gate input terminal. In the amplifier, the variable resistor, gate resistors of the respective gate fingers, and the dielectric capacitors form a plurality of low pass filters having desired frequency characteristics, and the gate fingers are different from each other in width or length from the gate input terminal to an oxide diffusion (OD) area boundary.

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate; a second region laterally adjacent to the first region; a third region disposed laterally adjacent to the second region on a side of the second region opposite the first region; a fourth region disposed within a portion of the first region proximate the second region; a fifth region disposed within a portion of the second region proximate the first region, wherein the fourth region and the fifth region are separated by a first isolation area; a sixth region disposed within a portion of the third region proximate the second region; and a seventh region disposed within the second region and below the fifth region.

Abstract: A protection diode includes a semiconductor substrate; a gate side well region of a first conductivity type in the semiconductor substrate; a grounding side well region of the first conductivity type in the semiconductor substrate and joined to the gate side well region; a gate side diffusion region of a second conductivity type in the semiconductor substrate and joined to the gate side well region; a grounding side diffusion region of the second conductivity type in the semiconductor substrate, separated from the gate side diffusion region, and joined to the grounding side well region; a gate side electrode connected between a gate of a transistor and the gate side diffusion region; and a grounding electrode connected to the grounding side diffusion region. Dopant impurity concentration in the grounding side well region is lower than dopant impurity concentration in the gate side well region.

Abstract: A protection diode includes: a semiconductor substrate; a well region of a first conductivity type in the semiconductor substrate; a gate side diffusion region of a second conductivity type in the semiconductor substrate and joined to the well region; a grounding side diffusion region of the second conductivity type in the semiconductor substrate, separated from the gate side diffusion region, and joined to the well region; a gate side electrode connected between a gate of a transistor and the gate side diffusion region; a grounding electrode connected to the grounding side diffusion region; and an insulating film on the well region. The grounding electrode extends to the well region on the insulating film.

Abstract: A semiconductor device according to the present invention includes a base plate, an insulating layer provided on an upper surface of the base plate, a metal pattern provided on an upper surface of the insulating layer, a semiconductor element bonded to the metal pattern, and an insulating substrate disposed to be in contact with an upper surface of the semiconductor element. An end of the insulating substrate is located outside the semiconductor element in plan view. The end of the insulating substrate and the metal pattern are directly or indirectly bonded. The semiconductor element includes an electrode on the upper surface. A portion of the insulating substrate, in which the electrode on the upper surface of the semiconductor element overlaps in plan view, is provided with a through-hole.

Abstract: A semiconductor device (1) includes an n type epitaxial layer (8), body regions (12) formed in the surface layer part of the n type epitaxial layer (8), n type source regions (16) formed in the surface layer parts of the body regions (12), a gate insulating film (19) formed on the n type epitaxial layer (8), and a gate protection diode (30) and gate electrodes (20) formed on the gate insulating film (19). The gate protection diode (30) includes a first p type region (31), an n type region (32), and a second p type region (33). A first diode (30A) is formed of the first p type region (31) and the n type region (32). A second diode (30B) is formed of the n type region (32) and the second p type region (33). The first p type region (31) is connected to the gate electrode (20). The second p type region (33) is connected to a source electrode (27).

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

Abstract: An electro-static-discharge (ESD) protection circuit has a vertical NPN transistor with a floating p-type base created by a deep p-type implant under an N+ source region. The deep p-type implant may be an ESD implant in a standard CMOS process. The p-type implant provides a low initial snap-back trigger voltage, but the holding voltage may be too low, creating latch-up problems. The holding voltage is raised by about one volt by connecting the emitter of the vertical NPN transistor to parallel resistor and diode paths. When the vertical NPN transistor is triggered, its current initially flows through the resistor, creating an increasing voltage drop through the resistor as current rises. Once the voltage across the resistor reaches 0.5 volt, the diode in parallel with the resistor becomes forward biased and shunts a higher current than the resistor, raising the holding voltage. A clamp transistor may replace the diode.

Abstract: A semiconductor device includes a substrate having a first type doping. The semiconductor device further includes a first deep well in the substrate, the first deep well having a second type doping. The semiconductor device further includes a second deep well in the substrate, the second deep well having the second type doping and being separated and above the first deep well. The semiconductor device further includes a first well over the second deep well, the first well having the first type doping and a gate structure over the first well.

Abstract: An integrated circuit (IC) including a well region of the IC having a first doping level and a plurality of semiconductor regions implanted in the well region. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. A plurality of polysilicon regions are arranged on the plurality of semiconductor regions. The polysilicon regions are respectively connected to the semiconductor regions. The plurality of semiconductor regions is a drain of a metal-oxide semiconductor field-effect transistor (MOSFET).

Abstract: An integrated circuit including a first power rail, a second power rail, a power clamp connected between the first and second power rails; and a trigger circuit connected to the power clamp and the first second power rails. The trigger circuit includes an RC element formed on the basis of field effect transistors, first inverter stage connected to the RC element, a second inverter stage, and a third inverter stage. The first, second and third inverter stages are connected in series to a control input of the power clamp. The trigger circuit also included a feed back connection from an output of the second inverter stage to the first inverter stage.

Abstract: An ESD protection structure and a semiconductor device having an ESD protection structure with the ESD protection structure including a patterned conductive ESD protection layer. The ESD protection layer is patterned to have a first portion of a substantially closed ring shape having an outer contour line and an inner contour line parallel with each other. The outer and the inner contour lines are waved lines. The first portion further has a midline between and parallel with the outer and the inner contour lines. The midline is a waved line having a substantially constant curvature at each point of the midline. Therefore the ESD protection layer has a substantially uniform curvature and an increased perimeter which advantageously improve the breakdown voltage and the current handling capacity of the ESD protection structure.