For Protecting Against Gate Insulator Breakdown Patents (Class 257/356)
  • Patent number: 10381474
    Abstract: A power semiconductor device includes a substrate, a main body and an electrode unit. The main body includes an active portion, an edge termination portion surrounding the active portion, and an insulating layer disposed on the edge termination portion. The edge termination portion includes a first-type semiconductor region, and a plurality of spaced-apart second-type semiconductor segments distributed in the first-type semiconductor region and arranged at intervals along a Y-direction directing from the insulating layer toward the substrate, and an X-direction directing from the active portion toward the edge termination portion. The electrode unit includes a first electrode and a second electrode.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: August 13, 2019
    Assignee: MACROBLOCK, INC.
    Inventors: Kung-Yen Lee, Chih-Fang Huang, Sheng-Chung Wang, Chia-Hui Cheng
  • Patent number: 10319711
    Abstract: An organic light emitting display device includes a substrate including a pixel region and a peripheral region, a first wiring, a second wiring, a third wiring, and an electrostatic protection structure including electrostatic protection diodes coupled to the first, second, and third wirings. The electrostatic protection diodes each include an active pattern, a gate electrode pattern, and a connection pattern. The active pattern is at the peripheral region of the substrate, and has a first region, a second region spaced apart from the first region, and a third region between the first and second regions. The gate electrode pattern is at the third region on the active pattern. The connection pattern is coupled to the gate electrode pattern and the active pattern and is on the gate electrode pattern, and overlaps a portion of the first region of the active pattern and a portion of the third region.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: June 11, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung-Hyun Kim, Yeon-Hong Kim, Ki-Wan Ahn
  • Patent number: 10291021
    Abstract: A protection circuit includes a control circuit that controls current between a first wiring and a second wiring and an application circuit that applies a voltage to the control circuit. The control circuit includes a first thin film transistor that controls the current. The application circuit includes second and third thin film transistors that are connected in series. Each of the second and third thin film transistors includes first and second gates. The first gate of the second thin film transistor is connected to the first wiring. The first gate of the third thin film transistor is connected to a connection point between the second and third thin film transistors. The second gates of the second thin film transistor and the third thin film transistor are connected to the second wiring. The application circuit applies a voltage of the connection point to a gate of the first thin film transistor.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: May 14, 2019
    Assignee: NLT Technologies, Ltd.
    Inventors: Hiroyuki Sekine, Yusuke Yamamoto
  • Patent number: 10256225
    Abstract: A gate-less electrostatic discharge (ESD) protection device is provided that can be formed in various complementary metal-oxide-semiconductor (CMOS) systems. The gate-less ESD event protection device includes a substrate, a first doped region formed in the substrate, a second doped region extending into the first doped region, a third doped region extending into the first doped region, a first node formed over a portion of the second doped region and coupled to a source terminal and a second node formed over the third doped region and coupled to a drain terminal. The gate-less ESD protection devices can be formed such that no gate electrode is formed and the gate-less ESD protection device does not include a gate terminal. Thus, an operating voltage range of the gate-less ESD protection device is not limited by gate oxide degradation.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: April 9, 2019
    Assignee: Allegro MicroSystems, LLC
    Inventors: Maxim Klebanov, Washington Lamar
  • Patent number: 10199367
    Abstract: A semiconductor device includes a semiconductor body having opposite first and second surfaces. The semiconductor device further includes a transistor structure in the semiconductor body and a source contact structure overlapping the transistor structure. The source contact structure is electrically connected to source regions of the transistor structure. A gate contact structure is further provided, which has a part separated from the source contact structure by a longitudinal gap within a lateral plane. Gate interconnecting structures bridge the longitudinal gap and are electrically coupled between the gate contact structure and a gate electrode of the transistor structure. Electrostatic discharge protection structures bridge the longitudinal gap and are electrically coupled between the gate contact structure and the source contact structure.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Markus Schmitt, Armin Tilke, Joachim Weyers
  • Patent number: 10157925
    Abstract: An IC structure is provided. The IC structure includes a P-type substrate, a deep N-well region in the substrate, a first N-well region on the deep N-well region, a first N-type doped region in the first N-well region, a second N-well region in the substrate, a first P-well region in the substrate, and a discharge circuit. The second N-well region and the first P-well region are separated from the deep N-well region. The discharge circuit includes a first P-type doped region in the first P-well region, a first PMOS transistor formed in the second N-well region, a first electrical path coupled between a source of the first PMOS transistor and the first N-type doped region, and a second electrical path coupled between a drain of the first PMOS transistor and the first P-type doped region.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Yu Kuo, Yu-Lin Chu
  • Patent number: 10147689
    Abstract: An electronic device includes a package, a plurality of external leads extending outside the package, a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads, and a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads. A capacitive coupling may be positioned between the first and second die to allow electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 4, 2018
    Assignee: Allegro MicroSystems, LLC
    Inventors: Washington Lamar, Maxim Klebanov
  • Patent number: 9972999
    Abstract: An electrostatic discharge (ESD) protection circuit is disclosed. In this regard, an ESD protection circuit is provided to protect an integrated circuit (IC) from an ESD event. In one aspect, an ESD voltage detection circuitry activates an ESD clamping circuitry when an ESD voltage associated with faster voltage rise time is detected between a supply rail and a ground rail. In another aspect, an operation voltage detection circuitry deactivates the ESD clamping circuitry when an operation voltage associated with slower voltage rise time is detected between the supply rail and the ground rail. By differentiating the ESD voltage from the operation voltage based on respective voltage rise times, it is possible to prevent the ESD clamping circuitry from missing the ESD voltage associated with the faster voltage rise time or being falsely activated by the operation voltage associated with the slower voltage rise time.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: May 15, 2018
    Assignee: Qorvo US, Inc.
    Inventor: Nathaniel Peachey
  • Patent number: 9966361
    Abstract: An electronics package includes an insulating substrate and electrical components coupled to a first surface of the insulating substrate. A multi-thickness conductor layer is formed on a second surface of the insulating substrate opposite the first surface. The multi-thickness conductor layer extends through vias in the insulating substrate to connect with contact pads of the electrical components. The multi-thickness conductor layer has a first thickness in a region proximate the first electrical component and a second thickness in a region proximate the second electrical component, the first thickness greater than the second thickness. The electronics package also includes a first redistribution layer having a conductor layer formed atop a portion of the multi-thickness conductor layer having the second thickness. A top surface of the conductor layer is co-planar with or substantially co-planar with a top surface of a portion of the multi-thickness conductor layer having the first thickness.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: May 8, 2018
    Assignee: General Electric Company
    Inventors: Risto Ilkka Tuominen, Arun Virupaksha Gowda
  • Patent number: 9882003
    Abstract: Some demonstrative embodiments include devices and/or systems of a Silicon Controlled Rectifier (SCR). For example, a silicon controlled rectifier (SCR) may include a metal-oxide-semiconductor field-effect transistor (MOSFET), the MOSFET may include a gate; an N-type source region; a non-Lightly Doped Drain (LDD) N-type drain region; and a P-Well region extending between the N-type source region and the non-LDD N-type drain region, and extending between the non-LDD N-type drain region and a drain region of the gate.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: January 30, 2018
    Assignee: TOWER SEMICONDUCTOR LTD.
    Inventor: Efraim Aharoni
  • Patent number: 9871030
    Abstract: A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: King-Yuen Wong, Chun-Wei Hsu, Chen-Ju Yu, Fu-Wei Yao, Jiun-Lei Jerry Yu, Fu-Chih Yang, Po-Chih Chen
  • Patent number: 9806146
    Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; a first doped region of type one, doped in the well of type two; and a second doped region of type two, provided in the well of type one and the well of type two, not touching the first doped region of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: October 31, 2017
    Assignee: MEDIATEK INC.
    Inventors: Bo-Shih Huang, Chien-Hui Chuang, Cheng-Chou Hung
  • Patent number: 9671215
    Abstract: Wafer to wafer alignment which includes a first semiconductor wafer and a second semiconductor wafer. The first and second semiconductor wafers have selectively-activated alignment arrays for aligning the first semiconductor wafer with the second semiconductor wafer. Each of the alignment arrays include an alignment structure which includes an antenna connected to a semiconductor device. The antenna in each of the alignment arrays is selectively activated to act as a charge source or as a charge sensing receptor. The alignment arrays are located in the kerf areas of the semiconductor wafers. The semiconductor wafers are aligned when the charge sources on one semiconductor wafer match with the charge sensing receptors on the other semiconductor wafer.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: June 6, 2017
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Spyridon Skordas
  • Patent number: 9608013
    Abstract: The present disclosure provides an array substrate, a liquid crystal panel, and a manufacturing method of the array substrate. In the present disclosure, the first discharging elements and the second discharging elements are arranged on the array substrate, the first discharging elements are electrically connected to the common electrode line, and the second discharging elements are respectively electrically connected to the data lines, and the first discharging elements and the second discharging elements are simultaneously formed with the scanning lines and the data lines or are formed after the scanning lines and the data lines are formed, thus, electrostatic protection is provided to the components in the subsequent manufacturing process of the array substrate after the scanning line and the data lines are formed on the array substrate.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: March 28, 2017
    Assignee: SHENZHEN CHINA STAR OTPOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhiguang Yi, Zhicheng Liu
  • Patent number: 9547205
    Abstract: According to one embodiment, a display device includes a first line extending in a first direction, an insulating layer covering the first line, a second line disposed on the insulating layer and extending in a second direction, and a drive circuit including an output line extending in the first direction and connected to the first line through a contact portion. The contact portion includes a first portion to which the first line is connected at a first position, and a second portion to which the output line is connected at a second position which is apart from the first position in the second direction, the second portion facing the first portion with the insulating layer interposed therebetween while being electrically connected to the first portion.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: January 17, 2017
    Assignee: Japan Display, Inc.
    Inventor: Akira Yokogawa
  • Patent number: 9502311
    Abstract: A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: November 22, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: King-Yuen Wong, Chun-Wei Hsu, Chen-Ju Yu, Fu-Wei Yao, Jiun-Lei Jerry Yu, Fu-Chih Yang, Po-Chih Chen
  • Patent number: 9484739
    Abstract: A protection device is provided that exhibits a turn on time of order of one nanosecond or less. Such a device provides enhanced protection for integrated circuits against electrostatic discharge events. This in turn reduces the risk of device failure in use. The protection device can include a bipolar transistor structure connected between a node to be protected and a discharge path.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: November 1, 2016
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Edward John Coyne, John Twomey, Seamus P. Whiston, David J. Clarke, Donal P. McAuliffe, William Allan Lane, Stephen Denis Heffernan, Brian A. Moane, Brian Michael Sweeney, Patrick Martin McGuinness
  • Patent number: 9391061
    Abstract: A unidirectional transient voltage suppressor (TVS) device includes first and second NPN transistors that are connected in parallel to each other. Each NPN transistor includes a collector region, an emitter. The first and second NPN structures are formed on a common substrate. The first NPN transistor has a floating base and the second NPN transistor has a base shorted to an emitter.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: July 12, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla
  • Patent number: 9373623
    Abstract: Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures. The first device layer is formed on a substrate and includes one or more first inverter structures. The second device layer is formed on the first device layer and includes one or more second inverter structures. The one or more inter-layer connection structures are configured to electrically connect to the first inverter structures and the second inverter structures.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Fan Lin, Yi-Tang Lin, Cheng-Hung Yeh, Hsien-Hsin Sean Lee, Chou-Kun Lin
  • Patent number: 9369088
    Abstract: An amplifier is disclosed that avoids an increase in circuit scale and an increase in power consumption, and easily avoids the odd-order harmonics. This amplifier includes a MOS transistor including a plurality of gate fingers or a plurality of MOS transistors each including a single gate finger; a dielectric capacitor that is added to each of the gate fingers; and a variable resistor that is connected between an input terminal to which an AC signal is input, and a gate input terminal. In the amplifier, the variable resistor, gate resistors of the respective gate fingers, and the dielectric capacitors form a plurality of low pass filters having desired frequency characteristics, and the gate fingers are different from each other in width or length from the gate input terminal to an oxide diffusion (OD) area boundary.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: June 14, 2016
    Assignee: PANASONIC CORPORATION
    Inventors: Kouji Takahashi, Shigeki Nakamura
  • Patent number: 9263428
    Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: February 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Cornelius Christian Russ, David Alvarez
  • Patent number: 9240401
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate; a second region laterally adjacent to the first region; a third region disposed laterally adjacent to the second region on a side of the second region opposite the first region; a fourth region disposed within a portion of the first region proximate the second region; a fifth region disposed within a portion of the second region proximate the first region, wherein the fourth region and the fifth region are separated by a first isolation area; a sixth region disposed within a portion of the third region proximate the second region; and a seventh region disposed within the second region and below the fifth region.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: January 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Yu Kuo, Chin-Yuan Ko
  • Patent number: 9202907
    Abstract: A protection diode includes: a semiconductor substrate; a well region of a first conductivity type in the semiconductor substrate; a gate side diffusion region of a second conductivity type in the semiconductor substrate and joined to the well region; a grounding side diffusion region of the second conductivity type in the semiconductor substrate, separated from the gate side diffusion region, and joined to the well region; a gate side electrode connected between a gate of a transistor and the gate side diffusion region; a grounding electrode connected to the grounding side diffusion region; and an insulating film on the well region. The grounding electrode extends to the well region on the insulating film.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: December 1, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Koichi Fujita
  • Patent number: 9202908
    Abstract: A protection diode includes a semiconductor substrate; a gate side well region of a first conductivity type in the semiconductor substrate; a grounding side well region of the first conductivity type in the semiconductor substrate and joined to the gate side well region; a gate side diffusion region of a second conductivity type in the semiconductor substrate and joined to the gate side well region; a grounding side diffusion region of the second conductivity type in the semiconductor substrate, separated from the gate side diffusion region, and joined to the grounding side well region; a gate side electrode connected between a gate of a transistor and the gate side diffusion region; and a grounding electrode connected to the grounding side diffusion region. Dopant impurity concentration in the grounding side well region is lower than dopant impurity concentration in the gate side well region.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: December 1, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Koichi Fujita
  • Patent number: 9171773
    Abstract: A semiconductor device according to the present invention includes a base plate, an insulating layer provided on an upper surface of the base plate, a metal pattern provided on an upper surface of the insulating layer, a semiconductor element bonded to the metal pattern, and an insulating substrate disposed to be in contact with an upper surface of the semiconductor element. An end of the insulating substrate is located outside the semiconductor element in plan view. The end of the insulating substrate and the metal pattern are directly or indirectly bonded. The semiconductor element includes an electrode on the upper surface. A portion of the insulating substrate, in which the electrode on the upper surface of the semiconductor element overlaps in plan view, is provided with a through-hole.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: October 27, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kiyoshi Arai, Osamu Usui
  • Patent number: 9142542
    Abstract: A semiconductor device (1) includes an n type epitaxial layer (8), body regions (12) formed in the surface layer part of the n type epitaxial layer (8), n type source regions (16) formed in the surface layer parts of the body regions (12), a gate insulating film (19) formed on the n type epitaxial layer (8), and a gate protection diode (30) and gate electrodes (20) formed on the gate insulating film (19). The gate protection diode (30) includes a first p type region (31), an n type region (32), and a second p type region (33). A first diode (30A) is formed of the first p type region (31) and the n type region (32). A second diode (30B) is formed of the n type region (32) and the second p type region (33). The first p type region (31) is connected to the gate electrode (20). The second p type region (33) is connected to a source electrode (27).
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: September 22, 2015
    Assignee: ROHM CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 9129805
    Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: September 8, 2015
    Assignee: Infineon Technologies AG
    Inventors: Cornelius Christian Russ, David Alvarez
  • Patent number: 9054521
    Abstract: An electro-static-discharge (ESD) protection circuit has a vertical NPN transistor with a floating p-type base created by a deep p-type implant under an N+ source region. The deep p-type implant may be an ESD implant in a standard CMOS process. The p-type implant provides a low initial snap-back trigger voltage, but the holding voltage may be too low, creating latch-up problems. The holding voltage is raised by about one volt by connecting the emitter of the vertical NPN transistor to parallel resistor and diode paths. When the vertical NPN transistor is triggered, its current initially flows through the resistor, creating an increasing voltage drop through the resistor as current rises. Once the voltage across the resistor reaches 0.5 volt, the diode in parallel with the resistor becomes forward biased and shunts a higher current than the resistor, raising the holding voltage. A clamp transistor may replace the diode.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: June 9, 2015
    Assignee: Hong Kong Applied Science & Technology Research Institute Company, Ltd.
    Inventors: Xiao Huo, Beiping Yan, Xiaowu Cai
  • Patent number: 8987825
    Abstract: A semiconductor device includes a substrate having a first type doping. The semiconductor device further includes a first deep well in the substrate, the first deep well having a second type doping. The semiconductor device further includes a second deep well in the substrate, the second deep well having the second type doping and being separated and above the first deep well. The semiconductor device further includes a first well over the second deep well, the first well having the first type doping and a gate structure over the first well.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hua-Chou Tseng, Chien-Chih Ho
  • Patent number: 8981484
    Abstract: An integrated circuit (IC) including a well region of the IC having a first doping level and a plurality of semiconductor regions implanted in the well region. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. A plurality of polysilicon regions are arranged on the plurality of semiconductor regions. The polysilicon regions are respectively connected to the semiconductor regions. The plurality of semiconductor regions is a drain of a metal-oxide semiconductor field-effect transistor (MOSFET).
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: March 17, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Ravishanker Krishnamoorthy, Siew Yong Chui
  • Patent number: 8969914
    Abstract: An integrated circuit including a first power rail, a second power rail, a power clamp connected between the first and second power rails; and a trigger circuit connected to the power clamp and the first second power rails. The trigger circuit includes an RC element formed on the basis of field effect transistors, first inverter stage connected to the RC element, a second inverter stage, and a third inverter stage. The first, second and third inverter stages are connected in series to a control input of the power clamp. The trigger circuit also included a feed back connection from an output of the second inverter stage to the first inverter stage.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: March 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sreenivasa Chalamala, Matthias Baer
  • Patent number: 8969968
    Abstract: An ESD protection structure and a semiconductor device having an ESD protection structure with the ESD protection structure including a patterned conductive ESD protection layer. The ESD protection layer is patterned to have a first portion of a substantially closed ring shape having an outer contour line and an inner contour line parallel with each other. The outer and the inner contour lines are waved lines. The first portion further has a midline between and parallel with the outer and the inner contour lines. The midline is a waved line having a substantially constant curvature at each point of the midline. Therefore the ESD protection layer has a substantially uniform curvature and an increased perimeter which advantageously improve the breakdown voltage and the current handling capacity of the ESD protection structure.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: March 3, 2015
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventors: Rongyao Ma, Tieshing Li
  • Patent number: 8963252
    Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor device may include a semiconductor element disposed on a substrate and including an insulating layer and a gate electrode, a doped region having a first conductivity-type on the substrate, a conductive interconnection electrically connected to the gate electrode, and a first contact plug having a second conductivity-type and electrically connecting the conductive interconnection and the doped region to each other and constituting a Zener diode by junction with the doped region.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moojin Kim, Jeongyun Lee
  • Patent number: 8946824
    Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: February 3, 2015
    Assignee: Panasonic Corporation
    Inventors: Tomoaki Ikegami, Kazuyuki Nakanishi, Masaki Tamaru
  • Patent number: 8946825
    Abstract: During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: David Yen, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
  • Patent number: 8921941
    Abstract: An electrostatic discharge (ESD) protection device includes a substrate; a source region of a first conductivity type in the substrate; a drain region of the first conductivity type in the substrate; a gate electrode overlying the substrate between the source region and the drain region; and a core pocket doping region of the second conductivity type within the drain region. The core pocket doping region does not overlap with an edge of the drain region.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: December 30, 2014
    Assignee: Mediatek Inc.
    Inventors: Ming-Tzong Yang, Ming-Cheng Lee
  • Patent number: 8916934
    Abstract: A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: December 23, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Steinhoff, Jonathan Brodsky, Thomas A. Vrotsos
  • Patent number: 8907424
    Abstract: A protection diode includes: a semiconductor substrate; a well region of a first conductivity type in the semiconductor substrate; a gate side diffusion region of a second conductivity type in the semiconductor substrate and joined to the well region; a grounding side diffusion region of the second conductivity type in the semiconductor substrate, separated from the gate side diffusion region, and joined to the well region; a gate side electrode connected between a gate of a transistor and the gate side diffusion region; and a grounding electrode connected to the grounding side diffusion region. Dopant impurity concentration in the grounding side diffusion region is lower than dopant impurity concentration in the gate side diffusion region.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: December 9, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Koichi Fujita
  • Patent number: 8907373
    Abstract: A protection device includes a triac and triggering units. Each triggering unit is formed by a MOS transistor configured to operate at least temporarily in a hybrid operating mode and a field-effect diode. The field-effect diode has a controlled gate that is connected to the gate of the MOS transistor.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Jean Jimenez, Johan Bourgeat, Boris Heitz
  • Patent number: 8872269
    Abstract: An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Hang Yang, Chun-Fu Chen, Pin-Dai Sue, Hui-Zhong Zhuang
  • Patent number: 8847319
    Abstract: Dummy structures between a high voltage (HV) region and a low voltage (LV) region of a substrate are disclosed, along with methods of forming the dummy structures. An embodiment is a structure comprising a HV gate dielectric over a HV region of a substrate, a LV gate dielectric over a LV region of the substrate, and a dummy structure over a top surface of the HV gate dielectric. A thickness of the LV gate dielectric is less than a thickness of the HV gate dielectric. The dummy structure is on a sidewall of the HV gate dielectric.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huei-Ru Liu, Chien-Chih Chou, Kong-Beng Thei, Gwo-Yuh Shiau
  • Patent number: 8847275
    Abstract: The component incorporates, in topological terms, a scalable number of triac structures in a concentric annular arrangement. The component can be used with an electronic device to protect against electrostatic discharges. For example, the components can be used to protect the input/output pad, the first power supply terminal, and the second power supply terminal of an integrated circuit against electrostatic discharges.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: September 30, 2014
    Assignee: STMicroelectronics S.A.
    Inventors: Jean Jimenez, Philippe Galy, Boris Heitz
  • Patent number: 8823106
    Abstract: The present invention mainly provides an ESD protective element which can be built in high voltage semiconductor integrated circuit devices without increasing the chip area. An ESD protective element according to one embodiment has a construction comprising a semiconductor layer, a first region of a first conduction type formed in the semiconductor layer, a first region of a second conduction type formed in the semiconductor layer away from the first region of the first conduction type, a second region of the second conduction type formed in the first region of the second conduction type and has a higher impurity concentration than it, and a second region of the first conduction type formed in the second region of the second conduction type and has a high impurity concentration. The first and second regions of the second conduction type are in an electrically floating state.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: September 2, 2014
    Assignee: Panasonic Corporation
    Inventors: Teruhisa Ikuta, Yoshinobu Satou
  • Patent number: 8816438
    Abstract: A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 26, 2014
    Assignee: Spansion LLC
    Inventors: Chun Chen, Sameer Haddad, Kuo Tung Chang, Mark Ramsbey, Unsoon Kim, Shenqing Fang
  • Patent number: 8810004
    Abstract: A resistor-equipped transistor includes a package that provides an external collector connection node (114, 134), an external emitter connection node (120, 140) and an external base connection node (106, 126). The package contains a substrate upon which a transistor (102, 122), first and second resistors, and first and second diodes are formed. The transistor has an internal collector (118, 138), an internal emitter (120, 140) and an internal base (116, 136) with the first resistor (104, 124) being electrically connected between the internal base and the external base connection node and the second resistor (108, 128) being electrically connected between the internal base and the internal emitter.
    Type: Grant
    Filed: November 26, 2009
    Date of Patent: August 19, 2014
    Assignee: NXP, B.V.
    Inventors: Stefan Bengt Berglund, Steffen Holland, Uwe Podschus
  • Patent number: 8779516
    Abstract: A second conduction-type MIS transistor in which a source is coupled to a second power source over the surface of a first conduction-type well and a drain is coupled to the open-drain signal terminal is provided. A second conduction-type first region is provided at both sides of the MIS transistor in parallel with a direction where the electric current of the MIS transistor flows and coupled to the open-drain signal terminal. The whole these components are surrounded by a first conduction-type guard ring coupled to the second power source and the outside surrounded by the first conduction-type guard ring is further surrounded by a second conduction-type guard ring coupled to a first power source. Thereby, the semiconductor device is capable of achieving ESD protection of an open-drain signal terminal having a small area and not providing a protection element between power source terminals.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: July 15, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Toshikatsu Kawachi
  • Patent number: 8772861
    Abstract: One embodiment of the invention relates to a field effect trench transistor with a multiplicity of transistor cells that are arranged like an array and whose gate electrodes are arranged in active trenches formed in a semiconductor body. Inactive trenches are arranged in the array of the transistor cells, there being no gate electrodes situated in said inactive trenches, and a series of polysilicon diodes are integrated in one or more of the inactive trenches which diodes, for protection against damage to the gate oxide through ESD pulses, are contact-connected to a source metallization at one of their ends and to a gate metallization at their other end, and/or alternatively or additionally one or more polysilicon zener diodes connected in series is or are integrated in the inactive trench or trenches and contact-connected to the gate metallization by one of its or their ends and to drain potential by its or their other end.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: July 8, 2014
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Norbert Krischke, Thorsten Meyer
  • Publication number: 20140183639
    Abstract: An ESD protection structure and a semiconductor device having an ESD protection structure with the ESD protection structure including a patterned conductive ESD protection layer. The ESD protection layer is patterned to have a first portion of a substantially closed ring shape having an outer contour line and an inner contour line parallel with each other. The outer and the inner contour lines are waved lines. The first portion further has a midline between and parallel with the outer and the inner contour lines. The midline is a waved line having a substantially constant curvature at each point of the midline. Therefore the ESD protection layer has a substantially uniform curvature and an increased perimeter which advantageously improve the breakdown voltage and the current handling capacity of the ESD protection structure.
    Type: Application
    Filed: December 26, 2013
    Publication date: July 3, 2014
    Applicant: Chengdu Monolithic Power Systems, Co., Ltd.
    Inventors: Rongyao Ma, Tieshing Li
  • Patent number: 8748987
    Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: June 10, 2014
    Assignee: Panasonic Corporation
    Inventors: Tomoaki Ikegami, Kazuyuki Nakanishi, Masaki Tamaru
  • Patent number: 8742475
    Abstract: In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer disposed on the dielectric layer, and a second metal layer disposed on the first metal layer, a second FET including a second portion of the first metal layer disposed on the dielectric layer, and a boundary region separating the first FET from the second FET.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin, Yanfeng Wang