Dielectric Isolation Means (e.g., Dielectric Layer In Vertical Grooves) Patents (Class 257/374)
  • Patent number: 10461085
    Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a first transistor on the substrate, wherein the first transistor includes a first source/drain electrode. The semiconductor device further includes a second transistor on the substrate, wherein the second transistor includes a second source/drain electrode. The semiconductor device further includes an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode and the second source/drain electrode.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: October 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Shan Wang, Shun-Yi Lee
  • Patent number: 10461189
    Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: October 29, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sug-Hyun Sung, Jung-gun You, Gi-gwan Park, Ki-il Kim
  • Patent number: 10461188
    Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The method includes: providing a substrate structure, where the substrate structure includes: a substrate having a first device region and a second device region, a first dummy gate structure at the first device region, a second dummy gate structure at the second device region, and an LDD region below the first dummy gate structure. The first dummy gate structure includes a first dummy gate dielectric layer at the first device region, a first dummy gate on the first dummy gate dielectric layer, and a first spacer layer at a side wall of the first dummy gate. The second dummy gate structure includes a second dummy gate dielectric layer at the second device region, a second dummy gate on the second dummy gate dielectric layer, and a second spacer layer at a side wall of the second dummy gate.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: October 29, 2019
    Assignees: Semiconductor Manufacturing Int. (Beijing) Corp., Semiconductor Manufacturing Int. (Shanghai) Corp.
    Inventor: Fei Zhou
  • Patent number: 10418440
    Abstract: A memory structure including a substrate, stacked structures, at least one isolation structure, a second conductive layer, and a second dielectric layer is provided. The stacked structures are disposed on the substrate. Each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structures, and the first opening extends into the substrate. The isolation structure is disposed in the first opening and covers a sidewall of the first dielectric layer. The isolation structure has a recess, such that a top profile of the isolation structure is shaped as a funnel. The second conductive layer is disposed on the stacked structures and fills the first opening. The second dielectric layer is disposed between the second conductive layer and the first conductive layer.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: September 17, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Chung-Hsien Liu, Chun-Hsu Chen, Lu-Ping Chiang
  • Patent number: 10361201
    Abstract: Semiconductor structures, devices, and methods of forming the structures and device are disclosed. Exemplary structures include multi-gate or FinFET structures that can include both n-channel MOS (NMOS) and p-channel MOS (PMOS) devices to form CMOS structures and devices on a substrate. The devices can be formed using selective epitaxy and shallow trench isolation techniques.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: July 23, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Qi Xie, Vladimir Machkaoutsan, Jan Willem Maes
  • Patent number: 10290550
    Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Feng Yuan, Hung-Li Chiang, Wei-Jen Lai
  • Patent number: 10263109
    Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: April 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungkwan Kang, Keum Seok Park, Byeongchan Lee, Sangbom Kang, Nam-Kyu Kim
  • Patent number: 10243047
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to active and passive radio frequency (RF) components with deep trench isolation structures and methods of manufacture. The structure includes a bulk high resistivity wafer with a deep trench isolation structure having a depth deeper than a maximum depletion depth at worst case voltage bias difference between devices which are formed on the bulk high resistivity wafer.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: March 26, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven M. Shank, Anthony K. Stamper, John J. Ellis-Monaghan
  • Patent number: 10229945
    Abstract: Provided is a solid state image pickup element including a MOS type transistor which amplifies a signal which is based on electric charges generated in a photoelectric conversion unit of a pixel. A channel region of the transistor is divided into a source-side region and a drain-side region. When a conductivity type of the transistor is defined as a first conductivity type and a conductivity type which is opposite to the first conductivity type is defined as a second conductivity type, a concentration of a first conductivity type impurity in the source-side region is higher than a concentration of the first conductivity type impurity in the drain-side region or a concentration of a second conductivity type impurity in the drain-side region is higher than a concentration of the second conductivity type impurity in the source-side region.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 12, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takehiko Soda, Akira Okita
  • Patent number: 10109714
    Abstract: Structures including a vertical field-effect transistor and fabrication methods for a structure including a vertical field-effect transistor. A vertical field-effect transistor includes a source/drain region located in a section of a semiconductor layer, a first semiconductor fin projecting from the source/drain region, a second semiconductor fin projecting from the source/drain region, and a gate electrode on the section of the semiconductor layer and coupled with the first semiconductor fin and with the second semiconductor fin. The structure further includes a contact located in a trench defined in the section of the semiconductor layer between the first semiconductor fin and the second semiconductor fin. The contact is coupled with the source/drain region of the vertical field-effect transistor.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Tek Po Rinus Lee
  • Patent number: 10109645
    Abstract: A semiconductor device includes a first device isolation layer defining active regions spaced apart from each other along a first direction on a substrate, second device isolation layers defining a plurality of active patterns protruding from the substrate, the second device isolation layers extending in the first direction to be spaced apart from each other in a second direction and connected to the first device isolation layer, a gate structure extending in the second direction on the first device isolation layer between the active regions, a top surface of the second device isolation layer being lower than a top surface of the active pattern, a top surface of the first device isolation layer being higher than the top surface of the active pattern, and at least part of a bottom surface of the gate structure being higher than the top surface of the active pattern.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: October 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changseop Yoon, Junggun You, YoungJoon Park, Jeonghyo Lee
  • Patent number: 10103244
    Abstract: A method of making a semiconductor device is provided. The method includes forming a deep well (DWELL) and a well (WELL) in a first region of a substrate, the WELL adjacent a surface of the substrate so that an interface between the WELL and DWELL is exposed on the surface of the substrate. A channel for a DEMOS transistor is formed in the first region over the interface and includes a first channel formed in the WELL and a second channel formed in the DWELL. A gate layer is deposited and patterned to concurrently form in the first region a first gate for the DEMOS transistor and in a second region a second gate for an ESD device. Dopants are implanted in the first and second regions to concurrently form a drain extension of the DEMOS transistor, and an ESD diffusion region of the ESD device.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: October 16, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Venkatraman Prabhakar, Igor Kouznetsov
  • Patent number: 10079279
    Abstract: A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a gate structure; and forming offset sidewall spacers around the gate structure. The method also includes forming trenches in the semiconductor substrate at outside of the gate structure; and forming isolation layers on side surfaces of the trenches to prevent diffusions between subsequently formed doping regions. Further, the method includes removing at least portions of the offset sidewall spacers to expose portions of the surface of the semiconductor substrate between the gate structure and the trenches; and forming filling layers with a top surface higher than the surface of the semiconductor substrate by filling the trenches and covering portions of the surface of the semiconductor substrate between the trenches and the gate structure. Further, the method also includes forming doping regions configured as raised source/drain regions in the filling layers.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: September 18, 2018
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Hualong Song
  • Patent number: 10074572
    Abstract: An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalls of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalls of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: September 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yup Chung, Yoon-seok Lee, Hyun-jo Kim, Hwa-sung Rhee, Hee-don Jeong, Se-wan Park, Bo-cheol Jeong
  • Patent number: 10074563
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a spacer element over a sidewall of the gate stack. The spacer element is substantially free of oxygen. The semiconductor device structure also includes a dielectric layer over the semiconductor substrate, and the dielectric layer surrounds the gate stack and the spacer element. The semiconductor device structure further includes a conductive contact penetrating through the dielectric layer and electrically connected to a conductive feature over the semiconductor substrate. An angle between a sidewall of the conductive contact and a top surface of the spacer element is in a range from about 90 degrees to about 120 degrees, and the conductive contact covers a portion of the spacer element.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: September 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hua-Li Hung, Chih-Lun Lu, Hsu-Yu Huang, Tsung-Fan Yin, Ying-Ting Hsia, Yi-Wei Chiu, Li-Te Hsu
  • Patent number: 10038065
    Abstract: One illustrative method disclosed includes, among other things, forming an initial conductive source/drain structure that is conductively coupled to a source/drain region of a transistor device, performing a recess etching process on the initial conductive source/drain structure to thereby define a stepped conductive source/drain structure with a cavity defined therein, forming a non-conductive structure in the cavity, forming a layer of insulating material above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, forming a gate contact opening in the layer of insulating material and forming a conductive gate contact in the gate contact opening that is conductively coupled to the gate structure.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: July 31, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Chanro Park, Min Gyu Sung, Hoon Kim
  • Patent number: 9972627
    Abstract: A semiconductor device that has a passing gate with a single gate electrode and a main gate with lower and upper gate electrodes mitigates gate induced drain leakage (GIDL). Additional elements that help mitigate GIDL include the upper gate electrode having a lower work function than the lower gate electrode, and the lower gate electrode being disposed below a storage node junction region while the upper gate electrode is disposed at a same level as the storage node junction region.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: May 15, 2018
    Assignee: SK HYNIX INC.
    Inventors: Tae Su Jang, Jeong Seob Kye
  • Patent number: 9960245
    Abstract: A transistor device including a semiconductor material layer, a gate layer, and an insulation layer between the gate layer and the semiconductor material layer is provided. The semiconductor material layer includes a first conductive portion, a second conductive portion, a channel portion between the first conductive portion and the second conductive portion, and a first protruding portion formed integrally. The channel portion has a first boundary adjacent to the first conductive portion, a second boundary adjacent to the second conductive portion, a third boundary, and a fourth boundary. The third boundary and the fourth boundary connect the terminals of the first boundary and the second boundary. The first protruding portion is protruded outwardly from the third boundary of the channel portion. The first gate boundary and the second gate boundary are overlapped with the first boundary and the second boundary of the channel portion.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: May 1, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Tai-Jui Wang, Tsu-Chiang Chang, Chieh-Wei Feng, Shao-An Yan, Wei-Han Chen
  • Patent number: 9953967
    Abstract: An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: April 24, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Youn Sung Choi, Greg Charles Baldwin
  • Patent number: 9947762
    Abstract: A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: April 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chu-Fu Chen, Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang
  • Patent number: 9922973
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to switches with deep trench depletion and isolation structures and methods of manufacture. The structure includes a bulk substrate with a fully depleted region below source and drain regions of at least one gate stack and confined by deep trench isolation structures lined with doped material.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: March 20, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven M. Shank, Anthony K. Stamper, John J. Ellis-Monaghan, Thai Doan
  • Patent number: 9847418
    Abstract: A method includes forming a fin on a substrate. A first liner is formed on the fin. A first dielectric layer is formed above the first liner. A patterned hard mask is formed above the first dielectric layer and has a fin cut opening defined therein. Portions of the first dielectric layer and the first liner disposed below the fin cut opening are removed to expose a portion of the fin. The patterned hard mask layer is removed. The exposed portion of the fin is oxidized to define a diffusion break in the fin.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: December 19, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kwan-Yong Lim, Min Gyu Sung, Chanro Park
  • Patent number: 9847278
    Abstract: A semiconductor device includes first and second bit line structures on a substrate and spaced apart from each other, a via plug partially filling between the first and second bit line structures, a via pad in contact with an upper surface of the via plug and an upper sidewall of the first bit line structure, the via pad being spaced apart from an upper portion of the second bit line structure, a first cavity filled with air being between the via plug and the first bit line structure and a second cavity filled with air between the via plug and the second bit line structure, A gap capping spacer having a first portion on the upper sidewall of the first bit line structure and a second portion covers the first air spacer. A horizontal width of the first portion is smaller than that of the second portion.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: December 19, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Eun Kim, Yongkwan Kim, Semyeong Jang, Jaehyoung Choi, Yoosang Hwang, Bong-Soo Kim
  • Patent number: 9825157
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor with a stress component and methods of manufacture. The heterojunction bipolar transistor includes a collector region, an emitter region and a base region. Stress material is formed within a trench of a substrate and surrounding at least the collector region and the base region.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: November 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vibhor Jain, Renata A. Camillo-Castillo, Anthony K. Stamper
  • Patent number: 9799676
    Abstract: The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: October 24, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Xinyun Xie, Ming Zhou
  • Patent number: 9793347
    Abstract: A semiconductor device includes a substrate, a conductive pattern, a side spacer, and an air gap. The substrate includes an interlayer insulating layer and a trench penetrating the interlayer insulating layer. The conductive pattern is disposed within the trench of the substrate. The side spacer is disposed within the trench. The side spacer covers an upper side surface of the conductive pattern. The air gap is disposed within the trench. The air gap is bounded by a sidewall of the trench, the side spacer, and a lower side surface of the conductive pattern. A level of a bottom surface of the conductive pattern is lower than a level of bottom surfaces of the side spacer.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: October 17, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woo-Jin Lee, Sang-Hoon Ahn, Gil-Heyun Choi, Jong-Won Hong
  • Patent number: 9786756
    Abstract: A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Bahman Hekmatshoartabari, Jeehwan Kim, Siegfried L. Maurer, Devendra K. Sadana
  • Patent number: 9755048
    Abstract: A patterned structure of a semiconductor device includes a substrate, a first feature and a second feature. The first feature and the second feature are disposed on the substrate, and either of which includes a vertical segment and a horizontal segment. There is a distance between the vertical segment of the first feature and the vertical segment of the second feature, and the distance is less than the minimum exposure limits of an exposure apparatus.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: September 5, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Rai-Min Huang, I-Ming Tseng, Tong-Jyun Huang, Kuan-Hsien Li
  • Patent number: 9748259
    Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a semiconductor device structure including a hybrid substrate comprising an SOI region and a bulk region, the SOI region comprising an active semiconductor layer, a substrate material, and a buried insulating material interposed between the active semiconductor layer and the substrate material, and the bulk region being provided by the substrate material, an insulating structure formed in the hybrid substrate, the insulating structure separating the bulk region and the SOI region, and a gate electrode formed in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: August 29, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Juergen Faul, Frank Jakubowski
  • Patent number: 9679890
    Abstract: In one general aspect, an apparatus can include a semiconductor substrate, and a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis. The apparatus includes a dielectric disposed within the trench, and an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric. The semiconductor substrate can have a portion aligned vertically and adjacent the trench, and the portion of the semiconductor substrate can have a conductivity type that is continuous along an entirety of the depth of the trench. The apparatus is biased to a normally-on state.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: June 13, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Tirthajyoti Sarkar, Adrian Mikolajczak, Ihsiu Ho, Ashok Challa
  • Patent number: 9673330
    Abstract: An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalk of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalk of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: June 6, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yup Chung, Yoon-seok Lee, Hyun-jo Kim, Hwa-sung Rhee, Hee-don Jeong, Se-wan Park, Bo-cheol Jeong
  • Patent number: 9673290
    Abstract: A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 6, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Bahman Hekmatshoartabari, Jeehwan Kim, Siegfried L. Maurer, Devendra K. Sadana
  • Patent number: 9640663
    Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The high-voltage FinFET device includes: at least one fin structure, a working gate, a shallow trench isolation structure, and a first dummy gate. The fin structure includes a first-type well region and a second-type well region adjacent to the first-type well region, and further includes a first part and a second part. A trench is disposed between the first part and the second part and disposed in the first-type well region. A drain doped layer is disposed on the first part which is disposed in the first-type well region, and a source doped layer is disposed on the second part which is disposed in the second-type well region. The working gate is disposed on the fin structure which is disposed in the first-type well region and in the second-type well region.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: May 2, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Tai-Ju Chen, Yi-Han Ye, Te-Chih Chen
  • Patent number: 9613852
    Abstract: The present disclosure provides a method for forming a semiconductor structure. In accordance with some embodiments, the method includes providing a substrate and a conductive feature formed over the substrate; forming a first etch stop layer over the conductive feature; forming a low-k dielectric layer over the first etch stop layer; etching the low-k dielectric layer to form a contact trench aligned with the conductive feature; performing a sputtering process to the first etch stop layer exposed in the contact trench; and forming a sealing oxide layer on the low-k dielectric layer. In some embodiments, the sealing oxide layer is self-aligned and conformed to surfaces of the low-k dielectric layer exposed in the contact trench.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiang-Wei Lin
  • Patent number: 9613953
    Abstract: A layout of a semiconductor device is stored on a non-transitory computer-readable medium. The layout includes an active area region extending in a first direction, a gate electrode extending in a second direction and crossing the active area region, and a dummy gate extending in the second direction. The dummy gate is adjacent the gate electrode. The dummy gate is a dielectric dummy gate.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: April 4, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9589954
    Abstract: Electric-field concentration in the vicinity of a recess is suppressed. A gate insulating film is provided on a substrate that has a drain region and a first recess therein. The first recess is located between the gate insulating film and the drain region, and is filled with an insulating film. The insulating film has a second recess on its side close to the gate insulating film. An angle defined by an inner side face of the first recess and the surface of the substrate is rounded on a side of the drain region close to the gate insulating film.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: March 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Akira Mitsuiki, Tomoo Nakayama, Shigeaki Shimizu, Hiroyuki Okuaki
  • Patent number: 9564424
    Abstract: In one embodiment, an ESD device is configured to include a trigger device that assists in forming a trigger of the ESD device. The trigger device is configured to enable a transistor or a transistor of an SCR responsively to an input voltage having a value that is no less than the trigger value of the ESD device.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: February 7, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: David D. Marreiro, Yupeng Chen, Ralph Wall, Umesh Sharma, Harry Yue Gee
  • Patent number: 9564353
    Abstract: An integrated circuit structure includes a semiconductor substrate, a semiconductor strip over a portion of the semiconductor substrate, and a Shallow Trench Isolation (STI) region on a side of the semiconductor strip. The STI region includes a dielectric layer, which includes a sidewall portion on a sidewall of the semiconductor strip and a bottom portion. The dielectric layer has a first etching rate when etched using a diluted HF solution. The STI region further includes a dielectric region over the bottom portion of the dielectric layer. The dielectric region has an edge contacting an edge of the sidewall portion of the dielectric layer. The dielectric region has a second etching rate when etched using the diluted HF solution, wherein the second etching rate is smaller than the first etching rate.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Kun-Yen Lu
  • Patent number: 9548357
    Abstract: Embodiments of the present invention provide an improved shallow trench isolation structure and method of fabrication. The shallow trench isolation cavity includes an upper region having a sigma cavity shape, and a lower region having a substantially rectangular cross-section. The lower region is filled with a first material having good gap fill properties. The sigma cavity is filled with a second material having good stress-inducing properties. In some embodiments, source/drain stressor cavities may be eliminated, with the stress provided by the shallow trench isolation structure. In other embodiments, the stress from the shallow trench isolation structure may be used to complement or counteract stress from a source/drain stressor region of an adjacent transistor. This enables precise tuning of channel stress to achieve a desired carrier mobility for a transistor.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: January 17, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: HaoCheng Tsai, Min-hwa Chi
  • Patent number: 9543437
    Abstract: An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: January 10, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Youn Sung Choi, Greg Charles Baldwin
  • Patent number: 9472610
    Abstract: A substrate having a dielectric film thereon, in which: the dielectric film comprises at least four stacked layers of a dielectric material; the stacked layers comprise compressive layers which are subject to a compressive stress, and tensile layers which are subject to a tensile stress; and there are at least two spaced apart tensile layers which are each adjacent to one or more compressive layers.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: October 18, 2016
    Assignee: SPTS TECHNOLOGIES LIMITED
    Inventors: Katherine Crook, Stephen R Burgess
  • Patent number: 9443957
    Abstract: A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: September 13, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel P. de Souza, Bahman Hekmatshoartabari, Jeehwan Kim, Siegfried L. Maurer, Devendra K. Sadana
  • Patent number: 9437723
    Abstract: A semiconductor device includes an electron transit layer configured to be formed on a substrate; an electron supply layer configured to be formed on the electron transit layer; an upper surface layer configured to be formed on the electron supply layer; a gate electrode configured to be formed on the electron supply layer or the upper surface layer; a source electrode and a drain electrode configured to be formed on the upper surface layer; and first conductivity-type regions configured to be formed in the upper surface layer and the electron supply layer immediately below regions where the source electrode and the drain electrode are formed. The electron supply layer is formed of a nitride semiconductor including In. The upper surface layer is formed of a material including a nitride of one or more elements selected among B, Al, and Ga.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: September 6, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Masato Nishimori, Toshihide Kikkawa
  • Patent number: 9437474
    Abstract: A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: September 6, 2016
    Assignee: Commissariat à l'énergie atomique et aux énergies alternative
    Inventors: Laurent Grenouillet, Yannick Le Tiec, Nicolas Loubet, Maud Vinet, Romain Wacquez
  • Patent number: 9362276
    Abstract: Semiconductor devices and fabrication methods are provided. A semiconductor substrate is provided having dummy gate structures formed thereon. A stress layer is formed in the semiconductor substrate between adjacent dummy gate structures. A first dielectric layer is formed on the semiconductor substrate, the stress layers, and the sidewall spacers of the dummy gate structures, exposing dummy gate electrode layers. Gate structures are formed in the dielectric layer to replace the dummy gate structures. The gate structures include functional gate structures and at least one non-functional gate structure. The at least one non-functional gate structure is removed to form at least one second opening in the first dielectric layer. At least one third opening is formed in the semiconductor substrate at a bottom of the at least one second opening. A second dielectric layer is formed in the at least one second opening and the at least one third opening.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 7, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Zhongshan Hong
  • Patent number: 9337178
    Abstract: In one embodiment, an ESD device is configured to include a trigger device that assists in forming a trigger of the ESD device. The trigger device is configured to enable a transistor or a transistor of an SCR responsively to an input voltage having a value that is no less than the trigger value of the ESD device.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: May 10, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: David D. Marreiro, Yupeng Chen, Ralph Wall, Umesh Sharma, Harry Yue Gee
  • Patent number: 9275957
    Abstract: In one embodiment, a semiconductor die is formed to have sloped sidewalls. A conductor is formed on the sloped sidewalls.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: March 1, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney, Gordon M. Grivna
  • Patent number: 9257327
    Abstract: Methods of forming a Field Effect Transistor (FET) are provided. The methods may include forming a region that provides enhanced oxidation under a fin-shaped FET (FinFET) body.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: February 9, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mark S. Rodder, Kang-ill Seo
  • Patent number: 9240462
    Abstract: A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: January 19, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Juergen Holz, Klaus Schruefer, Helmut Tews
  • Patent number: 9059244
    Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Ming Cai, Dechao Guo, Liyang Song, Chun-chen Yeh