With Pn Junction To Collect Injected Minority Carriers To Prevent Parasitic Bipolar Transistor Action Patents (Class 257/373)
  • Patent number: 10930799
    Abstract: A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: February 23, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Flavio Francesco Villa, Marco Morelli, Marco Marchesi, Simone Dario Mariani, Fabrizio Fausto Renzo Toia
  • Patent number: 10833019
    Abstract: A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: November 10, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Takashi Ando, Hiroaki Niimi, Tenko Yamashita
  • Patent number: 10243065
    Abstract: A SOI lateral heterojunction Si-emitter SiGe-base bipolar transistor is provided that contains an intrinsic base region that includes a small band gap region (i.e., a silicon germanium alloy base of a first conductivity type) and a large band gap region (i.e., a silicon region of the first conductivity type) A silicon emitter of a second conductivity type that is opposite the first conductivity type is formed on the large-band gap side of the intrinsic base region and a silicon collector of the second conductivity type is formed on the small-band gap side of the intrinsic base region.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Patent number: 9997528
    Abstract: Methods of integrating complementary SONOS devices into a CMOS process flow are described. In one embodiment, the method begins with depositing a hardmask (HM) over a substrate including a first-SONOS region and a second-SONOS region. A first tunnel mask (TUNM) is formed over the HM exposing a first portion of the HM in the second-SONOS region. The first portion of the HM is etched, a channel for a first SONOS device implanted through a first pad oxide overlying the second-SONOS region and the first TUNM removed. A second TUNM is formed exposing a second portion of the HM in the first-SONOS region. The second portion of the HM is etched, a channel for a second SONOS device implanted through a second pad oxide overlying the first-SONOS region and the second TUNM removed. The first and second pad oxides are concurrently etched, and the HM removed.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: June 12, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Venkatraman Prabhakar, Krishnaswamy Ramkumar, Igor Kouznetsov
  • Patent number: 9966141
    Abstract: A nonvolatile memory cell includes a first-conductivity-type silicon substrate, a metal layer formed in a surface of the first-conductivity-type silicon substrate, a second-conductivity-type diffusion layer formed in the surface of the first-conductivity-type silicon substrate and spaced apart from the metal layer, an insulating film disposed on the surface of the first-conductivity-type silicon substrate between the metal layer and the second-conductivity-type diffusion layer, a gate electrode disposed on the insulating film between the metal layer and the second-conductivity-type diffusion layer, and a sidewall disposed at a same side of the gate electrode as the metal layer and situated between the gate electrode and the metal layer, the sidewall being made of insulating material.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: May 8, 2018
    Assignee: NSCORE, INC.
    Inventor: Tadahiko Horiuchi
  • Patent number: 9887165
    Abstract: An IC may include a semiconductor substrate having circuitry formed in the substrate, an interconnect layer above the semiconductor substrate and having an antenna coupled to the circuitry, and a seal ring around a periphery of the interconnect layer. The IC may include an electrically insulating trench extending vertically into the semiconductor substrate and extending laterally across the semiconductor substrate from adjacent one side to adjacent another side.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: February 6, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alberto Pagani, Giovanni Girlando, Federico Giovanni Ziglioli, Alessandro Finocchiaro
  • Patent number: 9793196
    Abstract: Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction, each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: October 17, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Akira Matsumoto, Yoshinao Miura, Yasutaka Nakashiba
  • Patent number: 9390928
    Abstract: Capacitive coupling between a gate electrode and underlying portions of the source and drain regions can be enhanced while suppressing capacitive coupling between the gate electrode and laterally spaced elements such as contact via structures for the source and drain regions. A transistor including a gate electrode and source and drain regions is formed employing a disposable gate spacer. The disposable gate spacer is removed to form a spacer cavity, which is filled with an anisotropic dielectric material to form an anisotropic gate spacer. The anisotropic dielectric material is aligned with an electrical field such that lengthwise directions of the molecules of the anisotropic dielectric material are aligned vertically within the spacer cavity. The anisotropic gate spacer provides a higher dielectric constant along the vertical direction and a lower dielectric constant along the horizontal direction.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: July 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Emre Alptekin, Hari V. Mallela, Reinaldo Vega
  • Patent number: 9041119
    Abstract: A method of forming transistors with close proximity stressors to channel regions of the transistors is provided. The method includes forming a first transistor, in a first region of a substrate, having a gate stack on top of the first region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the first region including a source and drain region of the first transistor; forming a second transistor, in a second region of the substrate, having a gate stack on top of the second region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the second region including a source and drain region of the second transistor; covering the first transistor with a photo-resist mask without covering the second transistor; creating recesses in the source and drain regions of the second transistor; and forming stressors in the recesses.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: May 26, 2015
    Assignees: International Business Machines Corporation, GlobalFoundries, Inc.
    Inventors: Desmond J. Donegan, Jr., Abhishek Dube, Steven Jones, Jophy S. Koshy, Viorel Ontalus
  • Patent number: 8981488
    Abstract: A semiconductor structure and an integrated circuit are provided. The semiconductor structure includes a first field-effect transistor (FET), a second FET, an isolation structure, and a body electrode. The first FET includes a first active body having a first type conductivity. The second FET includes a second active body having the first type conductivity. The first active body and the second active body are isolated from each other by the isolation structure. The body electrode has the first type conductivity and formed in the second active body.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: March 17, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Yung-Ju Wen, Tien-Hao Tang, Chang-Tzu Wang
  • Patent number: 8981491
    Abstract: A memory array having improved radiation immunity is described. The memory array comprises a plurality of memory elements, each memory element having an p-type transistor formed in an n-type region; and a plurality of p-wells, each p-well having an n-type transistor coupled to a corresponding p-type transistor to form a memory element of the plurality of memory elements; wherein each p-well provides a p-n junction to dissipate minority charge in a portion of the n-type region occupied by a corresponding p-type transistor and associated with at least two adjacent memory elements. A method of implementing a memory array is also described.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: March 17, 2015
    Assignee: Xilinx, Inc.
    Inventors: Michael J. Hart, James Karp
  • Patent number: 8884372
    Abstract: At least one analog signal compatible complementary metal oxide semiconductor (CMOS) switch circuit is incorporated with digital logic circuits in an integrated circuit. The integrated circuit may further comprise a digital processor and memory, e.g., microcontroller, microprocessor, digital signal processor (DSP), programmable logic array (PLA), application specific integrated circuit (ASIC), etc., for controlling operation of the at least one analog signal compatible CMOS switch for switching analog signals, e.g., audio, video, serial communications, etc. The at least one analog signal compatible CMOS switch may have first and second states, e.g., single throw “on” or “off”, or double throw common to a or b, controlled by a single digital control signal of either a logic “0” or a logic “1”.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: November 11, 2014
    Assignee: Microchip Technology Incorporated
    Inventor: James K. Russell
  • Patent number: 8872276
    Abstract: An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: October 28, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, Gordon M. Grivna
  • Patent number: 8872222
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: October 28, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Ching-Lin Chan, Chen-Yuan Lin, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 8648427
    Abstract: An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: February 11, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, Gordon M. Grivna
  • Patent number: 8569865
    Abstract: An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: October 29, 2013
    Assignee: Infineon Technologies AG
    Inventor: Matthias Stecher
  • Patent number: 8518778
    Abstract: A method of forming a semiconductor structure is provided. A second area is between first and third areas. An epitaxial layer is formed on a substrate. A first gate is formed in the epitaxial layer and partially in first and second areas. A second gate is formed in the epitaxial layer and partially in second and third areas. A body layer is formed in the epitaxial layer in first and second areas. A doped region is formed in the body layer in the first area. All of the doped region, the epitaxial layer and the second gate are partially removed to form a first opening in the doped region and in the body layer in the first area, and form a second opening in the epitaxial layer in the third area and in a portion of the second gate. A first metal layer is filled in first and second openings.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: August 27, 2013
    Assignee: Excelliance MOS Corporation
    Inventor: Chu-Kuang Liu
  • Patent number: 8502336
    Abstract: A diode (200) is disclosed having improved efficiency, smaller form factor, and reduced reverse biased leakage current. Schottky diodes (212) are formed on the sidewalls (210) of a mesa region (206). The mesa region (206) is a cathode of the Schottky diode (212). The current path through the mesa region (206) has a lateral and a vertical current path. The diode (200) further comprises a MOS structure (214), p-type regions (220), MOS structures (230), and p-type regions (232). MOS structure (214) with the p-type regions (220) pinch-off the lateral current path under reverse bias conditions. P-type regions (220), MOS structures (230), and p-type regions (232) each pinch-off the vertical current path under reverse bias conditions. MOS structure (214) and MOS structures (230) reduce resistance of the lateral and vertical current path under forward bias conditions. The mesa region (206) can have a uniform or non-uniform doping concentration.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: August 6, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, Jefferson W. Hall, Mohammed Tanvir Quddus
  • Patent number: 8497195
    Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: July 30, 2013
    Assignee: Silicon Space Technology Corporation
    Inventor: Wesley H. Morris
  • Patent number: 8492849
    Abstract: A high side semiconductor structure is provided. The high side semiconductor structure includes a substrate, a first deep well, a second deep well, a first active element, a second active element and a doped well. The first deep well and the second deep well are formed in the substrate, wherein the first deep well and the second deep well have identical type of ion doping. The first active element and the second active element are respectively formed in the first deep well and the second deep well. The doped well is formed in the substrate and is disposed between the first deep well and the second deep well. The doped well, the first deep well and the second deep well are interspaced, and the type of ion doping of the first deep well and the second deep well is complementary with that of the doped well.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: July 23, 2013
    Assignee: System General Corp.
    Inventors: Han-Chung Tai, Hsin-Chih Chiang
  • Patent number: 8390074
    Abstract: A structure for preventing latchup. The structure includes a latchup sensitive structure and a through wafer via structure bounding the latch-up sensitive structure to prevent parasitic carriers from being injected into the latch-up sensitive structure.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: March 5, 2013
    Assignee: International Business Machines Corporation
    Inventor: Steven H. Voldman
  • Patent number: 8159033
    Abstract: A junction forming region is formed between a drain region of a MOS structure and a device isolation region which surrounds the MOS structure and is in contact with the drain region, to form a PN junction together with the drain region. As a consequence, it is possible to adjust a breakdown voltage of an ESD protection device which is fabricated in the same process as that for an internal device without varying basic performance of the internal device even at a final stage of an LSI manufacturing process.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: April 17, 2012
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Hirokazu Hayashi
  • Patent number: 8093145
    Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: January 10, 2012
    Assignee: Silicon Space Technology Corp.
    Inventor: Wesley H. Morris
  • Patent number: 8084844
    Abstract: A semiconductor device in which potential is uniformly controlled and in which the influence of noise is reduced. A p-type well region is formed beneath a surface of a p-type Si substrate. n-type MOS transistors are formed on the p-type well region. An n-type well region is formed in the p-type Si substrate so that it surrounds the p-type well region. A plurality of conductive regions which pierce through the n-type well region are formed at regular intervals. By doing so, parasitic resistance from the p-type Si substrate, through the plurality of conductive regions, to the n-type MOS transistors becomes low. Accordingly, when back bias is applied to a contact region, the back bias potential of the n-type MOS transistors can be controlled uniformly. As a result, the influence of noise from the p-type Si substrate or the p-type well region can be reduced.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: December 27, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takuji Tanaka
  • Patent number: 8072033
    Abstract: An electrostatic protection element is disposed commonly to a plurality of output circuits along a long side of an output circuit region. More preferably, the electrostatic protection element should be disposed between a Pch region and an Nch region of an output circuit.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: December 6, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Nobuyuki Kobayashi
  • Patent number: 7936023
    Abstract: A diode, includes a semiconductor substrate, a first region doped with a first dopant type in the substrate, a second region doped with a second dopant type in the substrate, a first well of the first dopant type in the substrate and surrounding the first region and the second region, and a second well of the second dopant type in the substrate connecting the first region and the second region. The first dopant type is opposite the second dopant type.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: May 3, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jaejune Jang, Bill Phan, Helmut Puchner
  • Patent number: 7911003
    Abstract: A semiconductor integrated circuit device including a semiconductor substrate and a MOS transistor having a source diffusion region and a drain diffusion region formed in the semiconductor substrate. A well is formed in the semiconductor substrate. A back gate diffusion region is defined in the vicinity of the source diffusion region or the drain diffusion region. The back gate diffusion region is of a conductivity type that is the same as that of the source diffusion region or the drain diffusion region. A potential control layer, arranged in the semiconductor substrate or under the well, controls the potential at the semiconductor substrate or the well.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: March 22, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kazutaka Takeuchi
  • Patent number: 7863689
    Abstract: Deep submicron wells of MOS transistors, implemented over an ungrounded well, exhibit two modes of operation: a current sink mode and a current source mode. While operation as a current sink is well understood and successfully controlled, it is also necessary to control the current provided in the current source mode of the well. A Schottky diode is connected between the well and the gate, the Schottky diode having a smaller barrier height than that of the PN junction of the well-to-source. For an NMOS transistor, current flows through the PN junction when the gate is high. When the gate is low, current flows through the Schottky diode. This difference of current flow results in a difference in transistor threshold, thereby achieving a dynamic threshold voltage using the current from the well when operating at the current source mode.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: January 4, 2011
    Assignee: Semi Solutions, LLC.
    Inventor: Robert Strain
  • Patent number: 7847616
    Abstract: A balanced input inverter circuit includes a first P-type MOS transistor including a gate terminal connected to an input, a source terminal connected to a first power source potential, and a drain terminal connected to an output, a first N-type MOS transistor including a gate terminal connected to the input, a drain terminal connected to the output, and a source terminal connected to a second power source potential, a first inverter circuit including an input terminal connected to an inverted input, and an output terminal connected to a back gate terminal of the first N-type MOS transistor, a first diode connected between the first power source potential and a first power source terminal of the first inverter circuit, a second inverter circuit including an input terminal connected to the inverted input, and an output terminal connected to a back gate terminal of the first P-type MOS transistor, and a second diode connected between the second power source potential and a second power source terminal of the sec
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: December 7, 2010
    Assignee: Fujitsu Limited
    Inventor: Yasuhiro Hashimoto
  • Patent number: 7804138
    Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: September 28, 2010
    Assignee: Silicon Space Technology Corp.
    Inventor: Wesley H. Morris
  • Patent number: 7723799
    Abstract: A semiconductor device includes a P-substrate, an N-well disposed in the P-substrate, an NMOS transistor disposed in the P-substrate and having one of a source and a drain connected to a ground voltage, a P-tap disposed in the P-substrate and connected to a low voltage so as to provide the P-substrate with the low voltage to be lower than the ground voltage, a PMOS transistor disposed in the N-well and having a source connected to a power supply voltage, an N-tap disposed in the N-well and connected to the power supply voltage so as to provide the N-well with the power supply voltage, and a depression-type PMOS transistor having a drain connected to the low voltage and a source connected to the ground voltage so as to prevent a parasitic transistor, which may exist among the PMOS transistor, the N-well, the NMOS transistor, and the P-substrate, from causing a latchup between the power supply voltage and the ground voltage due to the low voltage rising higher than the ground voltage, and for becoming in a cond
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: May 25, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Motoaki Nishimura
  • Patent number: 7675120
    Abstract: A composite integrated circuit incorporating two LDMOSFETs of unlike designs, with the consequent creation of a parasitic transistor. A multipurpose resistor is integrally built into the composite integrated circuit in order to prevent the parasitic transistor from accidentally turning on. In an intended application of the composite integrated circuit to a startup circuit of a switching-mode power supply, the multipurpose resistor serves as startup resistor for limiting the flow of rush current during the startup period of the switching-mode power supply.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: March 9, 2010
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Keiichi Sekiguchi, Kazuya Aizawa
  • Patent number: 7667288
    Abstract: Systems and methods for voltage distribution via epitaxial layers. In accordance with a first embodiment of the present invention, an integrated circuit comprises an epitaxial layer of a connectivity type disposed upon a wafer substrate of an opposite connectivity type.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: February 23, 2010
    Inventor: Robert P. Masleid
  • Publication number: 20100025761
    Abstract: Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic.
    Type: Application
    Filed: July 31, 2008
    Publication date: February 4, 2010
    Inventor: Steven H. Voldman
  • Patent number: 7629654
    Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: December 8, 2009
    Assignee: Silicon Space Technology Corp.
    Inventor: Wesley H. Morris
  • Patent number: 7595534
    Abstract: The invention relates to layers in substrate wafers. The aim of the invention is to provide layers in substrate wafers with which the drawbacks of conventional assemblies are overcome in order to achieve, on the one hand, an adequate resistance to latch-up in highly scaled, digital CMOS circuits with comparatively low costs and, on the other hand, to ensure low substrate losses/couplings for analog high-frequency circuits and, in addition, to influence the component behavior in a non-destructive manner.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: September 29, 2009
    Assignee: IHP GmbH-Innovations for High Performance Microelectronics/Institut fur Innovative Mikroelektronik
    Inventors: Bernd Heinemann, Karl-Ernst Ehwald, Dieter Knoll, Bernd Tillack, Dirk Wolansky, Peter Schley
  • Patent number: 7541652
    Abstract: An integrated circuit includes a substrate, a noise sensitive circuit, and a first low impedance guard ring. The substrate includes a well-doped blocking ring that at least partially surrounds the noise sensitive circuit. The noise sensitive circuit is fabricated on the substrate. The first low impedance guard ring is fabricated on the substrate to at least partially surround the well-doped blocking ring, wherein the first low impedance guard ring is operably coupled to a first circuit ground, wherein impedance of the first low impedance guard ring is substantially less than impedance of the well-doped blocking ring.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: June 2, 2009
    Assignee: XILINX, Inc.
    Inventor: Firas N. Abughazaleh
  • Patent number: 7482642
    Abstract: A bipolar transistor which has a base formed of a combination of shallow and deep acceptors species. Specifically, elements such as Indium, Tellurium, and Gallium are deep acceptors in silicon, and are appropriate for such an application, in combination with boron as the shallow acceptor. The use of a deep acceptor for doping the base of the transistor has the benefit of providing a doping species, which increases in ionization as the temperature rises. At elevated temperatures, the fraction of, for example, indium which is ionized increases and it results in an increased Gummel number, driving down the current gain. In other words, the enhancement of the Gummel number between room temperature and an elevated temperature compensates for the increase in the ratio of collector and base currents due to band gap narrowing effects. Thus, a zero temperature coefficient bipolar transistor is provided.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: January 27, 2009
    Assignee: LSI Corporation
    Inventor: Ashok K. Kapoor
  • Patent number: 7474011
    Abstract: A process and system for estimating the occurrence of single event latch-up in an integrated circuit. The process involves determining the resistance between each junction and the closest appropriate tap in a regular shaped well. Each junction occurring in an irregular-shaped well is also identified. Finally, the method may make suggestions for lowering the probability that single event latch-up may occur in the integrated circuit.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: January 6, 2009
    Assignee: Integrated Device Technologies, inc.
    Inventors: Chuen-Der Lien, Ta-Ke Tien, Pao-Lu Louis Huang
  • Patent number: 7436041
    Abstract: An ESD protection circuit using a double-triggered silicon controller rectifier (SCR). The double-triggered silicon controller rectifier (SCR) includes N+ diffusion areas, P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region formed in a P-substrate. The N+ diffusion areas and the P+ diffusion areas are isolated by shallow trench isolation (STI) structures. Two of the N+ diffusion areas are N-type trigger terminals. Two of the P+ diffusion areas are the P-type trigger terminal.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: October 14, 2008
    Assignee: National Chiao Tung University
    Inventors: Ming-Dou Ker, Kuo-Chun Hsu
  • Publication number: 20080158885
    Abstract: An LED module includes a housing component, a frame holding an LED thereon and covered by the housing component, a fastener located in and secured to the housing component, a heat spreader located in the fastener and secured to the fastener and a heat transfer member having a heat-dissipating unit remote from the LED and a heat pipe thermally connecting with the heat spreader, the LED and the heat-dissipating unit. The housing component tightly presses the frame on the fastener to make a close contact between the heat pipe and the frame. The heat pipe transfers heat from the LED to the heat spreader and the heat-dissipating unit. The heat spreader and the heat-dissipating unit each have a large heat-dissipating surface, whereby the heat generated by the LED can be quickly dissipated by the heat spreader and the heat-dissipating unit.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Applicant: FOXCONN TECHNOLOGY CO., LTD.
    Inventors: CHENG-TIEN LAI, ZHI-YONG ZHOU, QIAO-LI DING
  • Patent number: 7394156
    Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: July 1, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinya Tokunaga, Shigeki Furuya, Yuuji Hinatsu
  • Patent number: 7394136
    Abstract: A high performance semiconductor device and the method for making same is disclosed with an improved drive current. The semiconductor device has source and drain regions built on an active region, a length of the device being different than a width thereof. One or more isolation regions are fabricated surrounding the active region, the isolation regions are then filled with an predetermined isolation material whose volume shrinkage exceeds 0.5% after an anneal process. A gate electrode is formed over the active region, and one or more dielectric spacers are made next to the gate electrode. Then, a contact etch stopper layer is put over the device, wherein the isolation regions, spacers and contact etch layer contribute to modulating a net strain imposed on the active region so as to improve the drive current.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: July 1, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Hu Ke, Wen-Chin Lee, Yee-Chia Yeo, Chih-Hsin Ko, Chenming Hu
  • Patent number: 7355250
    Abstract: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: April 8, 2008
    Assignee: System General Corp.
    Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu G. Lin, Tuo-Hsin Chien
  • Patent number: 7326977
    Abstract: An FET (field effect transistor) having source, drain and channel regions of a conductivity type in a semiconductor body of opposite conductivity type. The channel region is located at the lower extremity of the source and drain regions so as to be spaced from the surface of the semiconductor body by a distance d.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: February 5, 2008
    Assignee: Northrop Grumman Corporation
    Inventors: Nathan Bluzer, Donald R. Lampe
  • Publication number: 20080017906
    Abstract: A silicon on insulator (SOI) device and methods for fabricating such a device are provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.
    Type: Application
    Filed: July 21, 2006
    Publication date: January 24, 2008
    Inventors: Mario M. Pelella, Donggang D. Wu, James F. Buller
  • Patent number: 7304354
    Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: December 4, 2007
    Assignee: Silicon Space Technology Corp.
    Inventor: Wesley H. Morris
  • Patent number: 7276772
    Abstract: A semiconductor device, including: a semiconductor substrate of a first conduction type; an active region used as a function-element-forming region on the semiconductor substrate; a low-resistance region of a second conduction type formed on an outermost periphery of the active region to surround the active region and having contact with the semiconductor substrate, the second conduction type being different from the first conduction type; and an electrode connected to the function element and the low-resistance region. A diode is formed by the semiconductor substrate and the low-resistance region. The function element and the diode are electrically connected in parallel between the semiconductor substrate and the electrode, and, between the semiconductor substrate and the electrode, resistance of the low-resistance region is lower than resistance of an electrical conduction path via the function element.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: October 2, 2007
    Assignee: Rohm Co., Ltd.
    Inventor: Kenichi Yoshimochi
  • Patent number: 7274073
    Abstract: An integrated circuit having devices fabricated in both SOI regions and bulk regions, wherein the regions are connected by a trench filled with epitaxially deposited material. The filled trench provides a continuous semiconductor surface joining the SOI and bulk regions. The SOI and bulk regions may have the same or different crystal orientations. The present integrated circuit is made by forming a substrate with SOI and bulk regions separated by an embedded sidewall spacer (made of dielectric). The sidewall spacer is etched, forming a trench that is subsequently filled with epitaxial material. After planarizing, the substrate has SOI and bulk regions with a continuous semiconductor surface. A butted P-N junction and silicide layer can provide electrical connection between the SOI and bulk regions.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: September 25, 2007
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: RE41477
    Abstract: An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of the P type buried layer dopant is greater than the N type buried layer dopant so that connections can be made to the P type buried layer by P wells which have a lower dopant concentration than the N buried layer.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: August 10, 2010
    Inventor: James D. Beasom