With Means To Reduce Substrate Spreading Resistance (e.g., Heavily Doped Substrate) Patents (Class 257/375)
  • Patent number: 11004978
    Abstract: Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Glenn Glass, Karthik Jambunathan, Anand Murthy, Chandra Mohapatra, Seiyon Kim
  • Patent number: 10833066
    Abstract: A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal, and a high-side drive circuit having a level shifter with a level shifter transistor. The low-side transistor and the level shifter transistor are integrated in a common semiconductor body.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: November 10, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler, Peter Irsigler
  • Patent number: 9461104
    Abstract: A semiconductor device includes: a semiconductor substrate; a high-voltage first resistive structure which extends along a spiral path above the substrate and is separated from the substrate by a first dielectric layer; and a conductive shielding structure, including a plurality of first shielding strips, which are arranged in sequence along respective portions of the first resistive structure and are separated from the first resistive structure by a second dielectric layer.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: October 4, 2016
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Vincenzo Palumbo, Mirko Venturato
  • Patent number: 8951879
    Abstract: A method for producing a protective structure may include: providing a semiconductor base substrate with a doping of a first conductivity type; producing a first epitaxial layer on the substrate; implanting a dopant of a second conductivity type in a delimited implantation region of the first epitaxial layer; applying a second epitaxial layer with a doping of the second conductivity type on the first epitaxial layer; forming an insulation zone in the second epitaxial layer, such that the second epitaxial layer is subdivided into first and second regions; producing a first dopant zone with a doping of the first conductivity type in the first region above the implantation region; producing a second dopant zone with a doping of the second conductivity type in the second region; outdiffusing the dopant from the implantation region to form a buried layer at the junction between the first epitaxial layer and the first region.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: February 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Andre Schmenn, Damian Sojka, Carsten Ahrens
  • Patent number: 8609502
    Abstract: In a method of manufacturing a semiconductor device, a semiconductor substrate of a first conductivity type having first and second surfaces is prepared. Second conductivity type impurities for forming a collector layer are implanted to the second surface using a mask that has an opening at a portion where the collector layer will be formed. An oxide layer is formed by enhanced-oxidizing the collector layer. First conductivity type impurities for forming a first conductivity type layer are implanted to the second surface using the oxide layer as a mask. A support base is attached to the second surface and a thickness of the semiconductor substrate is reduced from the first surface. An element part including a base region, an emitter region, a plurality of trenches, a gate insulating layer, a gate electrode, and a first electrode is formed on the first surface of the semiconductor substrate.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: December 17, 2013
    Assignee: DENSO CORPORATION
    Inventors: Masaki Koyama, Yutaka Fukuda
  • Patent number: 8507352
    Abstract: In a method of manufacturing a semiconductor device, a semiconductor substrate of a first conductivity type having first and second surfaces is prepared. Second conductivity type impurities for forming a collector layer are implanted to the second surface using a mask that has an opening at a portion where the collector layer will be formed. An oxide layer is formed by enhanced-oxidizing the collector layer. First conductivity type impurities for forming a first conductivity type layer are implanted to the second surface using the oxide layer as a mask. A support base is attached to the second surface and a thickness of the semiconductor substrate is reduced from the first surface. An element part including a base region, an emitter region, a plurality of trenches, a gate insulating layer, a gate electrode, and a first electrode is formed on the first surface of the semiconductor substrate.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: August 13, 2013
    Assignee: DENSO CORPORATION
    Inventors: Masaki Koyama, Yutaka Fukuda
  • Patent number: 8497195
    Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: July 30, 2013
    Assignee: Silicon Space Technology Corporation
    Inventor: Wesley H. Morris
  • Patent number: 8354292
    Abstract: In a method of manufacturing a CMOS image sensor, a P type epitaxial layer is formed on an N type substrate. A deep P+ type well layer is formed in the P type epitaxial layer. An N type deep guardring well is formed in a photodiode guardring region. The N type deep guardring region makes contact with the N type substrate and also be connected with an operational voltage terminal. A triple well is formed in a photodiode region and a peripheral circuit region. The triple well is used for forming a PMOS and an NMOS having different operational voltages. An isolation region is formed in the photodiode region. The isolation region in the photodiode region has a depth different from a depth of an isolation region in the peripheral circuit region.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: January 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Je Park, Young-Hoon Park, Ui-Sik Kim, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Kang
  • Patent number: 8168999
    Abstract: A semiconductor device includes: a substrate; an active element cell area including IGBT cell region and a diode cell region; a first semiconductor region on a first side of the substrate in the active element cell area; a second semiconductor region on a second side of the substrate in the IGBT cell region; a third semiconductor region on the second side in the diode cell region; a fourth semiconductor region on the first side surrounding the active element cell area; a fifth semiconductor region on the first side surrounding the fourth semiconductor region; and a sixth semiconductor region on the second side below the fourth semiconductor region. The second semiconductor region, the third semiconductor region and the sixth semiconductor region are electrically coupled with each other.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: May 1, 2012
    Assignee: DENSO CORPORATION
    Inventors: Yukio Tsuzuki, Kenji Kouno
  • Patent number: 8138530
    Abstract: In a method of manufacturing a CMOS image sensor, a P type epitaxial layer is formed on an N type substrate. A deep P+ type well layer is formed in the P type epitaxial layer. An N type deep guardring well is formed in a photodiode guardring region. The N type deep guardring region makes contact with the N type substrate and also be connected with an operational voltage terminal. A triple well is formed in a photodiode region and a peripheral circuit region. The triple well is used for forming a PMOS and an NMOS having different operational voltages. An isolation region is formed in the photodiode region. The isolation region in the photodiode region has a depth different from a depth of an isolation region in the peripheral circuit region.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: March 20, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Je Park, Young-Hoon Park, Ui-Sik Kim, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Keang
  • Patent number: 8093145
    Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: January 10, 2012
    Assignee: Silicon Space Technology Corp.
    Inventor: Wesley H. Morris
  • Patent number: 8080853
    Abstract: A semiconductor device includes a vertical IGBT and a vertical free-wheeling diode in a semiconductor substrate. A plurality of base regions is disposed at a first-surface side portion of the semiconductor substrate, and a plurality of collector regions and a plurality of cathode regions are alternately disposed in a second-surface side portion of the semiconductor substrate. The base regions include a plurality of regions where channels are provided when the vertical IGBT is in an operating state. The first-side portion of the semiconductor substrate include a plurality of IGBT regions each located between adjacent two of the channels, including one of the base regions electrically coupled with an emitter electrode, and being opposed to one of the cathode regions. The IGBT regions include a plurality of narrow regions and a plurality of wide regions.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: December 20, 2011
    Assignee: DENSO CORPORATION
    Inventors: Yukio Tsuzuki, Hiromitsu Tanabe, Kenji Kouno
  • Patent number: 7989329
    Abstract: A method and apparatus for removing excess dopant from a doped substrate is provided. In one embodiment, a substrate is doped by surfaced deposition of dopant followed by formation of a capping layer and thermal diffusion drive-in. A reactive etchant mixture is provided to the process chamber, with optional plasma, to etch away the capping layer and form volatile compounds by reacting with excess dopant. In another embodiment, a substrate is doped by energetic implantation of dopant. A reactive gas mixture is provided to the process chamber, with optional plasma, to remove excess dopant adsorbed on the surface and high-concentration dopant near the surface by reacting with the dopant to form volatile compounds. The reactive gas mixture may be provided during thermal treatment, or it may be provided before or after at temperatures different from the thermal treatment temperature. The volatile compounds are removed.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: August 2, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Ramaswamy, Kenneth S. Collins, Biagio Gallo, Hiroji Hanawa, Majeed A. Foad, Martin A. Hilkene, Kartik Santhanam, Matthew D. Scotney-Castle
  • Patent number: 7977753
    Abstract: A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICMOS device includes: a reverse diffusion under field (DUF) region formed by patterning a predetermined region of a semiconductor substrate; a diffusion under field (DUF) region formed in the substrate adjacent to the reverse DUF region; a spacer formed at a sidewall of the reverse DUF region; an epitaxial layer formed on an entire surface of the substrate; and a well region formed in contact with the DUF region.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: July 12, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Kwang Young Ko
  • Patent number: 7944000
    Abstract: A method for manufacturing a semiconductor resistor includes forming a well region in a semiconductor substrate, with the well region serving as a resistive region, forming a pair of contact regions spaced apart from each other in the well region, and forming a diffusion region in an intermediate portion between the pair of contact regions on a surface of the well region. The diffusion region is configured to adjust resistance and temperature dependence of the semiconductor resistor.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: May 17, 2011
    Assignee: Ricoh Company, Ltd.
    Inventors: Masaya Ohtsuka, Hiroaki Abe, Tatsuo Abe, legal representative
  • Patent number: 7911003
    Abstract: A semiconductor integrated circuit device including a semiconductor substrate and a MOS transistor having a source diffusion region and a drain diffusion region formed in the semiconductor substrate. A well is formed in the semiconductor substrate. A back gate diffusion region is defined in the vicinity of the source diffusion region or the drain diffusion region. The back gate diffusion region is of a conductivity type that is the same as that of the source diffusion region or the drain diffusion region. A potential control layer, arranged in the semiconductor substrate or under the well, controls the potential at the semiconductor substrate or the well.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: March 22, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kazutaka Takeuchi
  • Patent number: 7859058
    Abstract: An isolation insulating film is formed so that an active region of a first access transistor and a substrate contact region can be integrated with each other in a plan view. A dummy gate electrode is formed on the semiconductor substrate between the active region of the first access transistor and the substrate contact region. The dummy gate electrode is electrically connected to a P-type impurity region of the substrate contact region.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: December 28, 2010
    Assignee: Panasonic Corporation
    Inventors: Masayuki Nakamura, Satoshi Ishikura, Takayuki Yamada
  • Patent number: 7804138
    Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: September 28, 2010
    Assignee: Silicon Space Technology Corp.
    Inventor: Wesley H. Morris
  • Patent number: 7741680
    Abstract: The present invention relates to a semiconductor device including a substrate layer, a metal-oxide-semiconductor field-effect transistor (MOSFET), a backgate region, an isolation layer and a diode. The MOSFET includes a gate region, a source region and a drain region. The source and drain regions are embedded in the backgate region, which includes a voltage input terminal. The isolation layer is located between the backgate region and the substrate layer and has a doping type opposite that of the backgate region. The diode includes a first terminal connected to the isolation layer and a second terminal coupled to an isolation voltage source.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: June 22, 2010
    Assignee: Analog Devices, Inc.
    Inventors: Haiyang Zhu, David Foley
  • Patent number: 7714394
    Abstract: A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regions, respectively. A first elevated source region and a first elevated drain region are disposed at both sides of the first gate pattern respectively, and a second elevated source region and a second elevated drain region are disposed at both sides of the second gate pattern respectively. The first elevated source/drain regions are provided on the first active region, and the second elevated source/drain regions are provided on the second active region. A first gate spacer is provided between the first gate pattern and the first elevated source/drain regions.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: May 11, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Hwa-Sung Rhee, Tetsuji Ueno, Ho Lee, Seung-Hwan Lee
  • Patent number: 7629654
    Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: December 8, 2009
    Assignee: Silicon Space Technology Corp.
    Inventor: Wesley H. Morris
  • Patent number: 7396715
    Abstract: Patterning is performed in such a manner that an end portion fabricated of a second gate insulating film partially overlaps an end portion fabricated of a first gate insulating film. Then, a surface recovery treatment is performed in the aforementioned state where the first and second gate insulating films partially overlap each other.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: July 8, 2008
    Assignee: Fujitsu Limited
    Inventor: Kazuto Ikeda
  • Patent number: 7394156
    Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: July 1, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinya Tokunaga, Shigeki Furuya, Yuuji Hinatsu
  • Patent number: 7390680
    Abstract: A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristics database which identifies hard and soft bins that are sensitive to different failure mechanisms is maintained, and the bin characteristics database is used to compute particle sensitive yield. It is determined whether the particle sensitive yield of the local region around the current die is less than a pre-set threshold, and the die is downgraded if the particle sensitive yield of the local region around the current die is less than the pre-set threshold. If the particle sensitive yield of the local region around the current die is not less than the pre-set threshold, the die is not downgraded.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: June 24, 2008
    Assignee: LSI Corporation
    Inventors: Ramon Gonzales, Kevin Cota, Manu Rehani, David Abercrombie
  • Patent number: 7355250
    Abstract: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: April 8, 2008
    Assignee: System General Corp.
    Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu G. Lin, Tuo-Hsin Chien
  • Patent number: 7326977
    Abstract: An FET (field effect transistor) having source, drain and channel regions of a conductivity type in a semiconductor body of opposite conductivity type. The channel region is located at the lower extremity of the source and drain regions so as to be spaced from the surface of the semiconductor body by a distance d.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: February 5, 2008
    Assignee: Northrop Grumman Corporation
    Inventors: Nathan Bluzer, Donald R. Lampe
  • Patent number: 7304354
    Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: December 4, 2007
    Assignee: Silicon Space Technology Corp.
    Inventor: Wesley H. Morris
  • Patent number: 7132715
    Abstract: A semiconductor device includes a silicon substrate heavily-doped with phosphorous. A spacer layer is disposed over the substrate and is doped with dopant atoms having a diffusion coefficient in the spacer layer material that is less than the diffusion coefficient of phosphorous in silicon. An epitaxial layer is also disposed over the substrate. A device layer is disposed over the substrate, and over the epitaxial and spacer layers.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: November 7, 2006
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Qi Wang, Amber Crellin-Ngo, Hossein Paravi
  • Patent number: 7019379
    Abstract: A semiconductor device includes a heavily doped layer 25 of p-type formed in the surface of an n-type well 21, an intermediately doped layer 26 of p-type formed to adjoin and surround the heavily p-doped layer 25, and an isolation region 22 formed to surround the heavily p-doped layer 25 and the intermediately p-doped layer 26. The heavily p-doped layer 25 has a higher dopant concentration than the well 21. The intermediately p-doped layer 26 has a higher dopant concentration than the well 21 and a lower dopant concentration than the heavily p-doped layer 25.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: March 28, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hirotsugu Honda
  • Patent number: 6995432
    Abstract: A MIS type semiconductor device and a method for fabricating the same characterized in that impurity regions are selectively formed on a semiconductor substrate or semiconductor thin film and are activated by radiating laser beams or a strong light equivalent thereto from above so that the laser beams or the equivalent strong light are radiated onto the impurity regions and on an boundary between the impurity region and an active region adjoining the impurity region.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: February 7, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 6972466
    Abstract: Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the lightly-doped base region, a low-resistance current path into the base region may be provided. The low-resistance current path may be provided by a base conductor formed from heavily-doped epitaxial crystalline semiconductor. Metal-oxide-semiconductor (MOS) transistors with narrow gates may be formed on the same substrate as bipolar transistors. The MOS gates may be formed using a self-aligned process in which a patterned gate conductor layer serves as both an implantation mask and as a gate conductor. A base masking layer that is separate from the patterned gate conductor layer may be used as an implantation mask for defining the lightly-doped base region.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: December 6, 2005
    Assignee: Altera Corporation
    Inventors: Minchang Liang, Yow-Juang Liu, Fangyun Richter
  • Patent number: 6963113
    Abstract: A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: November 8, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Ting Cheong Ang, Sang Yee Loong, Shyue Fong Quek, Jun Song
  • Patent number: 6946711
    Abstract: In a semiconductor device such as MOSFET, a single crystal semiconductor substrate is provided. An epitaxitial layer is formed on the single crystal semiconductor substrate. A p-well regions are formed on the epitaxitial layer, respectively, and n+ source regions are formed on the p-well regions, respectively. A gate electrode is formed through a gate insulation film on a part of each p-well region and that of each n+ source region. The gate electrode is covered with an insulation film. On the insulation film, a source electrode is formed so that the n-channel MOSFET includes body diodes BD imbedded therein. A drain electrode is formed on the single crystal semiconductor substrate. A cluster-containing layer is implanted in the single crystal semiconductor substrate as a gettering layer so that the cluster-containing layer contains a cluster of nitrogen.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: September 20, 2005
    Assignee: Denso Corporation
    Inventors: Mikimasa Suzuki, Shoji Miura, Akira Kuroyanagi, Noriyuki Iwamori, Takashi Suzuki
  • Patent number: 6943411
    Abstract: A semiconductor device can include a low resistance wiring layer (13) formed in, and extending along a base material. A number of element regions (14) are formed separate from one another, each in contact with wiring layer (13). A circuit element can be formed in each element region (14). A metal is preferably used for wiring layer (13). In the above arrangement, metal-oxide-semiconductor (MOS) type transistors can be provided in a silicon-on-insulator (SOI) substrate that can have different potentials applied to a source/drain region with respect to a channel region.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: September 13, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Toshikazu Kato
  • Patent number: 6853040
    Abstract: A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximate the edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region. P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: February 8, 2005
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Kyung-Oun Jang, Sun-Hak Lee
  • Patent number: 6833591
    Abstract: A method for fabricating a semiconductor device including a step of forming an interconnection having the upper surface covered with an insulation film on a base substrate, a step of sequentially depositing an insulation film and an insulation film on the base substrate with the interconnection formed on, a step of etching the insulation film with the insulation film as a stopper to form openings in a region containing a region where the interconnection is formed, and the step of etching the insulation film in the opening to form sidewall insulation films of the insulation film on the side walls of the interconnection and to form contact holes to be connected to the base substrate in alignment with the interconnection.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: December 21, 2004
    Assignee: Fujitsu Limited
    Inventor: Shunji Nakamura
  • Patent number: 6831330
    Abstract: A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A recessed plug of a conductive material is then formed within a lower portion of the opening and a dielectric spacer is formed along the sidewalls of an upper portion of the opening. The spacer is cylindrical and has a central hole. A contact plug is subsequently formed within the central hole, the contact plug electrically coupled to the recessed plug. The contact plug can include a memory element or an additional memory element can be applied over the contact plug.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: December 14, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Steven T. Harshfield
  • Publication number: 20040212021
    Abstract: An HNMOS transistor (4) has its drain electrode connected to the gate electrode of an NMOS transistor (21), and a logic circuit voltage (VCC) is applied to the drain electrode of the NMOS transistor (21) through a resistor (32). A ground potential is applied to the source electrode of the NMOS transistor (21). A drain potential (V2) at the NMOS transistor (21) is monitored by an interface circuit (1), for indirectly monitoring a potential (VS). Thus provided is a high voltage integrated circuit for preventing damage to a semiconductor device used for performing bridge rectification of a power line.
    Type: Application
    Filed: February 19, 2004
    Publication date: October 28, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Kazuhiro Shimizu
  • Publication number: 20040183140
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.
    Type: Application
    Filed: March 31, 2004
    Publication date: September 23, 2004
    Applicant: Agare Systems Inc.
    Inventors: Wen Lin, Charles W. Pearce
  • Publication number: 20040135208
    Abstract: A semiconductor substrate of the present invention is a DSP wafer or Semi-DSP wafer (FIG. 2) having a flatness of an SFQR value ≦70 (nm) and containing boron at a concentration not lower than 5×1016 (atoms/cm3) nor higher than 2×1017 (atoms/cm3) within 95% or more of rectangular regions of 25×8 (mm2) arranged on a front face of the substrate. Specifically, a silicon crystal layer by an epitaxial growth is formed on a front face of a silicon substrate having the above substrate boron concentration.
    Type: Application
    Filed: December 24, 2003
    Publication date: July 15, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Katsuto Tanahashi, Hiroshi Kaneta, Tetsuo Fukuda
  • Publication number: 20040099878
    Abstract: A structure that reduces signal cross-talk through the semiconductor substrate for System-On-Chip (SOC) (2) applications, thereby facilitating the integration of digital circuit blocks (6) and analog circuit blocks (8) onto a single IC. Cross-circuit interaction through a substrate (4) is reduced by strategically positioning the various digital circuit blocks (6) and analog circuit blocks (8) in an isolated wells (10), (12), (16) and (20) over a resistive substrate (4). These well structures (10), (12), (16), and (20) are then surrounded with a patterned low resistivity layer (22) and optional trench region (24). The patterned low resistivity region (22) is formed below wells (10) and (12) and functions as a low resistance AC ground plane. This low resistivity region (22) collects noise signals that propagate between digital circuit blocks (6) and analog circuit blocks (8).
    Type: Application
    Filed: November 26, 2002
    Publication date: May 27, 2004
    Applicant: Motorola, Inc.
    Inventors: Wen Ling M. Huang, Sushil Bharatan, Carl Kyono, David J. Monk, Kun-Hin To, Pamela J. Welch
  • Patent number: 6737709
    Abstract: A semiconductor device suppressing the lateral diffusion of impurities doped in a PMOS and NMOS and shortening the distance between the PMOS and NMOS to reduce the size of the semiconductor device, including PMOS and NMOS formation regions isolated by an element isolation region; a p-type gate electrode arranged on the PMOS formation region; an n-type gate electrode arranged on the NMOS formation region; and first and second impurity storage regions arranged in a direction different from that of the arrangement of the p-type and n-type gate electrodes. An end of the first impurity storage region is connected to the p-type gate electrode, an end of the second impurity storage region is connected to the n-type gate electrode, and the other ends of the first and second impurity storage regions are electrically connected.
    Type: Grant
    Filed: December 14, 1998
    Date of Patent: May 18, 2004
    Assignee: Sony Corporation
    Inventor: Hajime Nakayama
  • Patent number: 6734496
    Abstract: A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: May 11, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Tatsuhiko Fujihira
  • Publication number: 20040075144
    Abstract: A structure protects CMOS logic from substrate minority carrier injection caused by the inductive switching of a power device. A single Integrated Circuit (IC) supports one or more power MOSFETs and one or more arrays of CMOS logic. A highly doped ring is formed between the drain of the power MOSFET and the CMOS logic array to provide a low resistance path to ground for the injected minority carriers. Under the CMOS logic is a highly doped buried layer to form a region of high recombination for the injected minority carriers. One or more CMOS devices are formed above the buried layer. The substrate is a resistive and the injected current is attenuated. The well in which the CMOS devices rest forms a low resistance ground plane for the injected minority carriers.
    Type: Application
    Filed: October 16, 2002
    Publication date: April 22, 2004
    Applicant: Motorola, Inc.
    Inventors: Moaniss Zitouni, Edouard D. de Fresart, Richard J. De Souza, Xin Lin, Jennifer H. Morrison, Patrice Parris
  • Patent number: 6649983
    Abstract: A vertical bipolar transistor is described which utilizes ion implantation steps which are used to form an nMOS field effect device and a pMOS field effect device. The implantation steps form an n-well, a p-well region, a pocket base region and an emitter region which are vertically oriented within a semiconductor substrate. The resulting bipolar device may have a significant relative gain and is constructed with no additional mask steps.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: November 18, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Amitava Chatterjee
  • Patent number: 6566756
    Abstract: In a method of manufacturing a semiconductor device, semiconductor circuit elements or wiring patterns are formed on a semiconductor substrate. Then, a porous semiconductor oxide film is formed as an interlayer insulating film on the semiconductor substrate including the semiconductor circuit elements or wiring patterns by oxidizing semiconductor substance in a mixture gas containing an oxygen gas in a chamber.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: May 20, 2003
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Hiroshi Morisaki, Shinji Nozaki
  • Patent number: 6563159
    Abstract: Provided is a substrate of a semiconductor integrated circuit which can easily manufacture an integrated circuit having a soft error resistance, a latch up resistance and an ESD resistance increased. A thickness of a semiconductor surface layer having a lower impurity concentration than that of each of substrate single crystals 51 and 55 is varied according to a resistance which should be possessed by each section such as a memory cell section 5, a logic section 6, an input-output section 8 or the like for a region where each section is to be formed.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: May 13, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuya Kunikiyo, Ken-ichiro Sonoda
  • Patent number: 6563173
    Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: May 13, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ronald J. Bolam, Subhash B. Kulkarni, Dominic J. Schepis
  • Patent number: 6559486
    Abstract: An etching mask having high etching selectivity for an inorganic interlayer film of SiO2 or Si3N4, an organic interlayer film such as ARC and an electrically conductive film and a contact hole using such an etching mask, a process for forming same and a resultant semiconductor device. On formation of contact holes for connecting wirings disposed through interlayer films of inorganic or organic material (20, 23 in FIG. 2), a thin film of silicon carbide (21 in FIG. 2) having high etching selectivity for any of the inorganic and organic materials is deposited on an interlayer film, and a mask pattern of silicon carbide is formed using a resist pattern (22 in FIG. 2). Thereafter, high aspect ratio contact holes having a size which is exactly same as that of the mask is formed by etching the interlayer film using the silicon carbide mask.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: May 6, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Yasuhiko Ueda
  • Patent number: RE40339
    Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: May 27, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ronald J. Bolam, Subhash B. Kulkami, Dominic J. Schepis