With Polysilicon Interconnections To Source Or Drain Regions (e.g., Polysilicon Laminated With Silicide) Patents (Class 257/377)
  • Patent number: 10446567
    Abstract: To provide a nonvolatile storage element capable of being formed by an ordinary CMOS process using single layer polysilicon without requiring exclusive forming process and a reference voltage generation circuit with high versatility and high precision. A reference voltage generation circuit includes nonvolatile storage elements formed of single layer polysilicon. The nonvolatile storage elements each include a MOS transistor including a floating gate, a MOS transistor including a floating gate, and a MOS transistor including a floating gate.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: October 15, 2019
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Toshiro Sakamoto, Satoshi Takehara
  • Patent number: 10411018
    Abstract: Various embodiments provide semiconductor structures and their fabrication methods. An SRAM memory cell can include at least one semiconductor structure, and an SRAM memory can include at least one SRAM memory cell. An exemplary semiconductor structure can include at least two adjacent transistors formed on a semiconductor substrate. An opening can be formed and surrounded by gates of the two adjacent transistors and a doped region formed between the gates of the two adjacent transistors. A conductive layer can be formed to at least partially cover a bottom and a sidewall of the opening to electrically connect a gate of one transistor with the doped region of the other transistor of the two adjacent transistors.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: September 10, 2019
    Assignee: Semiconductor Manufacturing International Corp.
    Inventors: Tzu-Yin Chiu, Juilin Lu, Jianxiang Cai
  • Patent number: 10312245
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having a shared SRAM trench and a common contact having a low contact resistance. The method includes forming a first semiconductor fin opposite a surface of a substrate and forming a second semiconductor fin opposite the surface of the substrate and adjacent to the first semiconductor fin. A doped region is formed over portions of each of the first and second semiconductor fins and a dielectric layer is formed over the doped regions. A shared trench is formed in the dielectric layer exposing portions of the doped regions. The exposed doped regions are then amorphized and recrystallized.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zuoguang Liu, Gen Tsutsui, Heng Wu, Peng Xu
  • Patent number: 10254037
    Abstract: A fan assembly for a refrigeration appliance includes a fan for circulating air within a compartment of the refrigeration appliance. The fan includes a frame. A housing is provided for mounting the fan. The housing includes a plate with an opening extending through the plate. A plurality of walls extends from a surface of the plate. A first retaining member extends in a direction generally parallel to a surface of the plate and is disposed proximate the opening for hindering movement of the fan in a direction generally perpendicular to a surface of the plate. The plurality of walls and the first retaining member define a pocket for receiving the frame. A vibration damping member is provided for allowing the fan to vibrate relative to the housing and for hindering the transmission of vibrations from the fan to the housing.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: April 9, 2019
    Assignee: Electrolux Home Products, Inc.
    Inventors: Marcelo C. Candeo, Shawn Boiter, Justin Elgin
  • Patent number: 9941191
    Abstract: A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The opening in the first photoresist is transferred into a template layer to form a line trench therein. The lateral dimension of the trench is reduced by depositing a contiguous spacer layer that does not fill the trench completely. An etch-resistant material layer is conformally deposited and fills the trench, and is subsequently recessed to form an etch-resistant material portion filling the trench. A second photoresist layer is applied and patterned with a second pattern, which includes an opening that includes areas of two via holes and an area therebetween. A composite pattern of an intersection of the second pattern and the complement of the pattern of the etch-resistant material portion is transferred through the template layer.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chiahsun Tseng, Jin Liu, Lei Zhuang
  • Patent number: 9882125
    Abstract: Memory cells and methods of forming memory cells are disclosed. The memory cell includes a substrate and a select transistor. The select transistor includes a gate disposed over the substrate between first and second source/drain (S/D) terminals. The first and second S/D terminals are configured such that a resistance at the second S/D terminal is higher than a resistance at the first S/D terminal. A dielectric layer disposed over the substrate includes a plurality of inter level dielectric (ILD) layers. A lower portion of the dielectric layer includes a first contact level and a first metal level. A first contact plug disposed within the first contact level connects the first S/D terminal to a first metal line in the first metal level. A magnetic tunnel junction (MTJ) element is disposed directly on and in contact with a top of the first metal line.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: January 30, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Kiok Boone Elgin Quek
  • Patent number: 9793399
    Abstract: A semiconductor device includes a stressor and an insulating pattern. A device isolation layer is formed to define an active area on a substrate. A first gate electrode is formed on the active area. A second gate electrode is formed on the device isolation layer. A trench is formed in the active area between the first gate electrode and the second gate electrode. A stressor is formed in the trench. A cavity formed between the stressor and the device isolation layer and adjacent to the second gate electrode is disposed. An insulating pattern is formed in the cavity.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: October 17, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pan-Kwi Park, Koung-Min Ryu, Moon-Han Park, Hyung-suk Jung, Jong-hoon Baek, Su-Young Choi
  • Patent number: 9711649
    Abstract: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: July 18, 2017
    Assignee: STMicroelectronics, Inc.
    Inventor: John H. Zhang
  • Patent number: 9634113
    Abstract: A method of making a semiconductor device includes forming a source/drain region on a substrate; disposing a gate stack on the substrate and adjacent to the source/drain region, the gate stack including a gate spacer along a sidewall of the gate stack; disposing an inter-level dielectric (ILD) layer on the source/drain region and the gate stack; removing a portion of the ILD layer on the source/drain region to form a source/drain contact pattern; filling the source/drain contact pattern with a layer of silicon material, the layer of silicon material being in contact with the source/drain region and in contact with the gate spacer; depositing a metallic layer over the first layer of silicon material; and performing a silicidation process to form a source/drain contact including a silicide.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: April 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joshua M. Rubin, Tenko Yamashita
  • Patent number: 9607989
    Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: March 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xusheng Wu, Yue Hu, Xin Wang, Yong Meng Lee, Wen-Pin Peng, Lun Zhao, Wei-Hua Tong
  • Patent number: 9153586
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a gate dielectric layer formed on the substrate, and a metal electrode layer formed on the gate dielectric layer and including a compound of carbon and nitrogen, wherein a metal electrode formed from the metal electrode layer in the first region has a work function lower than a work function of a metal electrode formed from the metal electrode layer in the second region and a nitrogen concentration of the metal electrode of the first region is smaller than a nitrogen concentration of the metal electrode of the second region.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: October 6, 2015
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hyuck Ji, Woo-Young Park
  • Patent number: 9117692
    Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: August 25, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangjine Park, Boun Yoon, Jeongnam Han, Kee-Sang Kwon, Byung-Kwon Cho, Wonsang Choi
  • Patent number: 9018714
    Abstract: A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kerber, Christian Lavoie
  • Publication number: 20150076615
    Abstract: A semiconductor device includes a first fin rising out of a semiconductor base. It further includes a second fin rising out of the semiconductor base. The second fin is substantially parallel to the first fin that forms a span between the first fin and the second fin. A first dielectric layer is deposited on exposed surfaces of a first gate body area of the first fin, a second gate body area of the second fin, and an adjacent surface of the semiconductor base that defines the span between the first and second gate body areas. A gate electrode layer is sandwiched between the first dielectric layer and a second dielectric layer. The semiconductor device includes a third fin interdigitated between the first fin and the second fin within the span. Exposed surfaces of the gate body area of the third fin are in contact with the second dielectric layer.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 19, 2015
    Applicant: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
  • Patent number: 8981484
    Abstract: An integrated circuit (IC) including a well region of the IC having a first doping level and a plurality of semiconductor regions implanted in the well region. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. A plurality of polysilicon regions are arranged on the plurality of semiconductor regions. The polysilicon regions are respectively connected to the semiconductor regions. The plurality of semiconductor regions is a drain of a metal-oxide semiconductor field-effect transistor (MOSFET).
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: March 17, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Ravishanker Krishnamoorthy, Siew Yong Chui
  • Publication number: 20150061034
    Abstract: A method of fabricating Schottky barrier contacts for an integrated circuit (IC). A substrate including a silicon including surface is provided having a plurality of transistors formed thereon, where the plurality of transistors include at least one exposed p-type surface region and at least one exposed n-type surface region on the silicon including surface. A plurality of metals are deposited including Yb and Pt to form at least one metal layer on the substrate. The metal layer is heated to induce formation of an inhomogeneous silicide layer including both Ptsilicide and Ybsilicide on the exposed p-type and n-type surface regions.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Inventors: DEBORAH JEAN RILEY, JUDY BROWDER SHAW, CHRISTOPHER L. HINKLE, CREIGHTON T. BUIE
  • Patent number: 8928090
    Abstract: A metallic top surface of a replacement gate structure is oxidized to convert a top portion of the replacement gate structure into a dielectric oxide. After removal of a planarization dielectric layer, selective epitaxy is performed to form a raised source region and a raised drain region that extends higher than the topmost surface of the replacement gate structure. A gate level dielectric layer including a first dielectric material is deposited and subsequently planarized employing the raised source and drain regions as stopping structures. A contact level dielectric layer including a second dielectric material is formed over the gate level dielectric layer, and contact via holes are formed employing an etch chemistry that etches the second dielectric material selective to the first dielectric material. Raised source and drain regions are recessed. Self-aligned contact structures can be formed by filling the contact via holes with a conductive material.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Soon-Cheon Seo, Balasubramanian S. Haran, Alexander Reznicek
  • Patent number: 8907427
    Abstract: A semiconductor device may include a substrate, source and drain regions in the substrate, a recessed epitaxial channel layer in the substrate between the source and drain regions, and a high-K gate dielectric layer overlying the recessed epitaxial channel layer. The semiconductor device may further include a gate electrode overlying the high-K gate dielectric layer, a dielectric cap layer in contact with top and sidewall portions of the gate electrode, the dielectric cap layer having a lower dielectric constant than the high-K gate dielectric layer, and source and drain contacts coupled to the source and drain regions.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: John H Zhang
  • Patent number: 8900922
    Abstract: A method includes laminating a Non-Conductive Film (NCF) over a first package component, and bonding a second package component on the first package component. The NCF and the second package component are on a same side of the first package component. Pillars of a mold tool are then forced into the NCF to form openings in the NCF. The connectors of the first package component are exposed through the openings.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chung Lin, Kuei-Wei Huang, Ai-Tee Ang, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 8889554
    Abstract: The present invention provides a method for manufacturing a semiconductor structure, comprising: forming a first contact layer on an exposed active region of a first spacer; forming a second spacer at a region of the first contact layer close to a gate stack to partially cover the exposed active region; forming a second contact layer in the uncovered exposed active region, wherein when a diffusion coefficient of the first contact layer is the same as that of the second contact layer, the first contact layer has a thickness less than that of the second contact layer; and when the diffusion coefficient of the first contact layer is different from that of the second contact layer, the diffusion coefficient of the first contact layer is smaller than that of the second contact layer. Correspondingly, the present invention also provides a semiconductor structure.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: November 18, 2014
    Assignee: The Institue of Microelectronics Chinese Academy of Science
    Inventors: Haizhou Yin, Wei Jiang, Zhijiong Luo, Huilong Zhu
  • Patent number: 8878311
    Abstract: A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kerber, Christian Lavoie
  • Patent number: 8878275
    Abstract: In one general aspect, an apparatus can include a channel region disposed in a semiconductor substrate, a gate dielectric disposed on the channel region and a drift region disposed in the semiconductor substrate adjacent to the channel region. The apparatus can further include a field plate having an end portion disposed between a top surface of the semiconductor substrate and the gate dielectric The end portion can include a surface in contact with the gate dielectric, the surface having a first portion aligned along a first plane non-parallel to a second plane along which a second portion of the surface is aligned, the first plane being non-parallel to the top surface of the semiconductor substrate and the second plane being non-parallel to the top surface of the semiconductor substrate.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 4, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Sunglyong Kim, Mark Schmidt, Christopher Nassar, Steven Leibiger
  • Patent number: 8865556
    Abstract: Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph S. Newbury, Kenneth Parker Rodbell, Zhen Zhang, Yu Zhu
  • Patent number: 8865582
    Abstract: Disclosed are methods for manufacturing floating gate memory devices and the floating gate memory devices thus manufactured. In one embodiment, the method comprises providing a monocrystalline semiconductor substrate, forming a tunnel oxide layer on the substrate, and depositing a protective layer on the tunnel oxide layer to form a stack of the tunnel oxide layer and the protective layer. The method further includes forming at least one opening in the stack, thereby exposing at least one portion of the substrate, and cleaning the at least one exposed portion with a cleaning liquid. The method still further includes loading the substrate comprising the stack into a reactor and, thereafter, performing an in-situ etch to remove the protective layer, using the at least one exposed portion as a source to epitaxially grow a layer comprising the monocrystalline semiconductor material, and forming the layer into at least one columnar floating gate structure.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: October 21, 2014
    Assignee: IMEC
    Inventors: Roger Loo, Matty Caymax, Pieter Blomme, Geert Van den Bosch
  • Publication number: 20140246729
    Abstract: A semiconductor device including a substrate including an NMOS region and a PMOS region; first and second gate dielectrics on the NMOS and PMOS regions of the substrate and including a high-k dielectric material; a first gate structure on the first gate dielectric and including a sequentially stacked first n-type metal layer pattern and first electrode layer pattern; a second gate structure on the second gate dielectric and including a sequentially stacked p-type metal layer pattern, second n-type metal layer pattern, and second electrode layer pattern; first and second spacers on sidewalls of the first and second gate structures; a first offset pattern between the first gate structure and the first spacer; and a second offset pattern between the second gate structure and the second spacer, the second offset pattern being on the sidewalls of the second gate structure excluding sidewalls of the p-type metal layer pattern.
    Type: Application
    Filed: February 18, 2014
    Publication date: September 4, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Ho JANG, Tae-Ho LEE, Jung-Bun LEE
  • Patent number: 8803243
    Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yue Liang, Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon, Shreesh Narasimha, Xiaojun Yu
  • Patent number: 8766319
    Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: July 1, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Chih Lai, Chia Chang Hsu, Nien-Ting Ho, Bor-Shyang Liao, Shu Min Huang, Min-Chung Cheng, Yu-Ru Yang
  • Patent number: 8766236
    Abstract: A semiconductor device according to an embodiment includes: a substrate; a first semiconductor layer formed on the substrate and having a strain; a second and a third semiconductor layers formed at a distance from each other on the first semiconductor layer, and having a different lattice constant from a lattice constant of the first semiconductor layer; a gate insulating film formed on a first portion of the first semiconductor layer, the first portion being located between the second semiconductor layer and the third semiconductor layer; and a gate electrode formed on the gate insulating film.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Usuda, Tsutomu Tezuka
  • Patent number: 8754483
    Abstract: Embodiments of the present invention provide a structure. The structure includes a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, the gate stacks having spacers formed at sidewalls thereof; and one or more conductive contacts formed directly on top of the semiconductor substrate and interconnecting at least one source/drain of one of the plurality of field-effect-transistors to at least one source/drain of another one of the plurality of field-effect-transistors, wherein the one or more conductive contacts is part of a low-profile local interconnect that has a height lower than a height of the gate stacks.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shom Ponoth, David V. Horak, Charles W. Koburger, III, Chih-Chao Yang
  • Publication number: 20140151816
    Abstract: One device includes first and second spaced-apart active regions formed in a semiconducting substrate, a layer of gate insulation material positioned on the first active region, and a conductive line feature that has a first portion positioned above the gate insulation material and a second portion that conductively contacts the second active region. One method includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, performing an etching process to remove a portion of the gate insulation material formed on the second active region to expose a portion of the second active region, and forming a conductive line feature that comprises a first portion positioned above the layer of gate insulation material formed on the first active region and a second portion that conductively contacts the exposed portion of the second active region.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Frank Jakubowski, Juergen Faul
  • Patent number: 8742512
    Abstract: A semiconductor device according to the invention includes: a first region on a semiconductor substrate, in which a first transistor is formed, the first transistor including first gate insulating film 4 containing a high dielectric constant material and first metal gate electrode 5 formed on first gate insulating film 4; a second region adjacent to the first region on the semiconductor substrate, in which a second transistor is formed, the second transistor including second gate insulating film 4 and second metal gate electrode 12 formed on the second gate insulating film, a layered structure of electrode materials of the second transistor being different from a layered structure of electrode materials of the first transistor; and a first and a second line, the lines being of different potentials, wherein a border between the first and the second region overlaps with at most only the first or the second line.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: June 3, 2014
    Inventor: Takeshi Kishida
  • Patent number: 8729639
    Abstract: According to one embodiment, a semiconductor device includes a gate electrode formed on a substrate with a gate insulation film interposed therebetween, and a source region of a first conductivity type and a drain region of a second conductivity type reverse to the first conductivity type, which are formed so as to hold the gate electrode therebetween within the substrate. The work function of a first region on the source region side within the gate electrode is shifted toward the first conductivity type as compared to the work function of a second region on the drain region side within the gate electrode.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masakazu Goto
  • Patent number: 8723270
    Abstract: A SRAM includes a first CMOS inverter of first and second MOS transistors connected in series, a second CMOS inverter of third and fourth MOS transistors connected in series and forming a flip-flop circuit together with the first CMOS inverter, and a polysilicon resistance element formed on a device isolation region, each of the first and third MOS transistors is formed in a device region of a first conductivity type and includes a second conductivity type drain region at an outer side of a sidewall insulation film of the gate electrode with a larger depth than a drain extension region thereof, wherein a source region is formed deeper than a drain extension region, the polysilicon gate electrode has a film thickness identical to a film thickness of the polysilicon resistance element, the source region and the polysilicon resistance element are doped with the same dopant element.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: May 13, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Makoto Yasuda
  • Patent number: 8685809
    Abstract: Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Carl J. Radens, Anthony K. Stamper, Jay W. Strane
  • Patent number: 8652896
    Abstract: A SRAM includes a first CMOS inverter of first and second MOS transistors connected in series, a second CMOS inverter of third and fourth MOS transistors connected in series and forming a flip-flop circuit together with the first CMOS inverter, and a polysilicon resistance element formed on a device isolation region, each of the first and third MOS transistors is formed in a device region of a first conductivity type and includes a second conductivity type drain region at an outer side of a sidewall insulation film of the gate electrode with a larger depth than a drain extension region thereof, wherein a source region is formed deeper than a drain extension region, the polysilicon gate electrode has a film thickness identical to a film thickness of the polysilicon resistance element, the source region and the polysilicon resistance element are doped with the same dopant element.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: February 18, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Makoto Yasuda
  • Patent number: 8648472
    Abstract: In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper portions of the first metal interconnect and the second metal interconnect are recessed to form recesses. A second insulating film filling the recesses is then formed above a substrate, and the upper portion of the second insulating film is planarized. Next, a hole and a trench are formed to extend halfway through the second insulating film, and ashing and polymer removal are performed. Subsequently to this, the hole and the trench are allowed to reach the first metal interconnect and the second metal interconnect.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: February 11, 2014
    Assignee: Panasonic Corporation
    Inventor: Shusuke Isono
  • Patent number: 8629508
    Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tang Peng, Bing-Hung Chen, Tze-Liang Lee, Hao-Ming Lien
  • Patent number: 8569837
    Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: October 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsin Ko, Hung-Wei Chen, Chung-Hu Ke, Ta-Ming Kuan, Wen-Chin Lee
  • Patent number: 8569838
    Abstract: A method of fabricating gate level electrodes and interconnects in an integrated circuit, and an integrated circuit so fabricated, with improved process margin for the gate level interconnects of a width near the critical dimension. Off-axis illumination, as used in the photolithography of deep sub-micron critical dimension, is facilitated by the patterned features having a preferred orientation in a common direction, with a pitch constrained to within a relatively narrow range. Interconnects in that same gate level, for example “field poly” interconnects, that run parallel to an array of gate elements are placed within a specified distance range from the ends of the gate elements, or at a distance sufficient to allow sub-resolution assist features.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: October 29, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: James Walter Blatchford, Jr., Yong Seok Choi
  • Patent number: 8569803
    Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Christy S. Tyberg, Katherine L. Saenger, Jack O. Chu, Harold J. Hovel, Robert L. Wisnieff, Kerry Bernstein, Stephen W. Bedell
  • Patent number: 8563385
    Abstract: A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8558320
    Abstract: An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: October 15, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Haining Yang, Chock H. Gan, Zhongze Wang, Beom-Mo Han
  • Patent number: 8536711
    Abstract: A semiconductor device includes a through electrode that penetrates through a silicon substrate, an isolation trench provided to penetrate through the silicon substrate to surround the through electrode, a first silicon film in contact with an inner surface of the isolation trench, a second silicon film in contact with an outer surface of the isolation trench, and an insulation film provided between the first and second silicon films.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: September 17, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Shiro Uchiyama
  • Patent number: 8513122
    Abstract: A method forms an integrated circuit structure. The method patterns a protective layer over a first-type field effect transistor and removes a stress liner from above a second-type field effect transistors. Then, the method removes a first-type silicide layer from source and drain regions of the second-type field effect transistor, but leaves at least a portion of the first-type silicide layer on the gate conductor of the second-type field effect transistor. The method forms a second-type silicide layer on the gate conductor and the source and drain regions of the second-type field effect transistor. The second-type silicide layer that is formed is different than the first-type silicide layer. For example, the first-type silicide layer and the second-type silicide layer can comprise different materials, different thicknesses, different crystal orientations, and/or different chemical phases, etc.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Viorel C. Ontalus, Ahmet S. Ozcan
  • Patent number: 8507994
    Abstract: In a memory cell including CMOS inverters, an increase in an area of the memory cell caused by restrictions on a gate wiring due to a leakage current and restrictions due to design rules is suppressed. A first wiring and a second wiring are laid out as a first metal layer in the memory cell that includes a first inverter and a second inverter. The first wiring is connected with two drains in the first inverter and a second gate wiring in the second inverter. The second wiring is connected with two drains in the second inverter and a first gate wiring in the first inverter. The first wiring is laid out to overlap with the second gate wiring, and the second wiring is laid out to overlap with the first gate wiring. A second metal layer is laid out above the first metal layer, and a third metal layer is laid out above the second metal layer.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: August 13, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventor: Kouichi Yamada
  • Patent number: 8492854
    Abstract: A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Christian Lavoie
  • Patent number: 8492286
    Abstract: Embodiment of the present invention provides a method of forming electronic fuse or commonly known as e-fuse. The method includes forming a polysilicon structure and a field-effect-transistor (FET) structure together on top of a common semiconductor substrate, the FET structure having a sacrificial gate electrode; implanting at least one dopant into the polysilicon structure to create a doped polysilicon layer in at least a top portion of the polysilicon structure; subjecting the polysilicon structure and the FET structure to a reactive-ion-etching (RIE) process, the RIE process selectively removing the sacrificial gate electrode of the FET structure while the doped polysilicon layer being substantially unaffected by the RIE process; and converting the polysilicon structure including the doped polysilicon layer into a silicide to form the electronic fuse.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Henry K. Utomo, Ying Li, Gerald L. Leake
  • Patent number: 8445971
    Abstract: A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8432000
    Abstract: High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: April 30, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Thomas E. Grebs
  • Patent number: 8420491
    Abstract: A structure and method for replacement metal gate (RMG) field effect transistors is disclosed. Silicide regions are formed on a raised source-drain (RSD) structure. The silicide regions form a chemical mechanical polish (CMP) stopping layer during a CMP process used to expose the gates prior to replacement. Protective layers are then applied and etched in the formation of metal contacts.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: April 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Henry K. Utomo, Unoh Kwon, Dimitri Anastassios Levedakis, Ravikumar Ramachandran, Viraj Yashawant Sardesai, Rajasekhar Venigalla