Abstract: In a memory cell including CMOS inverters, an increase in an area of the memory cell caused by restrictions on a gate wiring due to a leakage current and restrictions due to design rules is suppressed. A first wiring and a second wiring are laid out as a first metal layer in the memory cell that includes a first inverter and a second inverter. The first wiring is connected with two drains in the first inverter and a second gate wiring in the second inverter. The second wiring is connected with two drains in the second inverter and a first gate wiring in the first inverter. The first wiring is laid out to overlap with the second gate wiring, and the second wiring is laid out to overlap with the first gate wiring. A second metal layer is laid out above the first metal layer, and a third metal layer is laid out above the second metal layer.

Abstract: A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.

Abstract: Embodiment of the present invention provides a method of forming electronic fuse or commonly known as e-fuse. The method includes forming a polysilicon structure and a field-effect-transistor (FET) structure together on top of a common semiconductor substrate, the FET structure having a sacrificial gate electrode; implanting at least one dopant into the polysilicon structure to create a doped polysilicon layer in at least a top portion of the polysilicon structure; subjecting the polysilicon structure and the FET structure to a reactive-ion-etching (RIE) process, the RIE process selectively removing the sacrificial gate electrode of the FET structure while the doped polysilicon layer being substantially unaffected by the RIE process; and converting the polysilicon structure including the doped polysilicon layer into a silicide to form the electronic fuse.

Abstract: A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.

Abstract: High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.

Abstract: A structure and method for replacement metal gate (RMG) field effect transistors is disclosed. Silicide regions are formed on a raised source-drain (RSD) structure. The silicide regions form a chemical mechanical polish (CMP) stopping layer during a CMP process used to expose the gates prior to replacement. Protective layers are then applied and etched in the formation of metal contacts.

Abstract: A manufacturing process of a semiconductor device includes generating a less random grain orientation distribution in metal features of a semiconductor device by employing a grain orientation layer. The less random grain orientation, e.g., a grain orientation distribution which has a higher percentage of grains that have a predetermined grain orientation, may lead to improved reliability of the metal features. The grain orientation layer may be deposited on the metal features wherein the desired grain structure of the metal features may be obtained by a subsequent annealing process, during which the metal feature is in contact with the grain orientation layer.

Abstract: In a semiconductor device, a gate electrode having a uniform composition prevents deviation in a work function. Controlling a Vth provides excellent operation properties. The semiconductor device includes an NMOS transistor and a PMOS transistor with a common line electrode. The line electrode includes electrode sections (A) and (B) and a diffusion barrier region formed over an isolation region so that (A) and (B) are kept out of contact. The diffusion barrier region meets at least one of: (1) The diffusion coefficient in the above diffusion barrier region of the constituent element of the above electrode section (A) is lower than the interdiffusion coefficient of the constituent element between electrode section (A) materials; and (2) The diffusion coefficient in the above diffusion barrier region of the constituent element of the above electrode section (B) is lower than the interdiffusion coefficient of the constituent element between electrode section (B) materials.

Abstract: A SRAM includes a first CMOS inverter of first and second MOS transistors connected in series, a second CMOS inverter of third and fourth MOS transistors connected in series and forming a flip-flop circuit together with the first CMOS inverter, and a polysilicon resistance element formed on a device isolation region, each of the first and third MOS transistors is formed in a device region of a first conductivity type and includes a second conductivity type drain region at an outer side of a sidewall insulation film of the gate electrode with a larger depth than a drain extension region thereof, wherein a source region is formed deeper than a drain extension region, the polysilicon gate electrode has a film thickness identical to a film thickness of the polysilicon resistance element, the source region and the polysilicon resistance element are doped with the same dopant element.

Abstract: A semiconductor device and a method for preparing the same that can solve crack of a semiconductor film, capacitance electrodes and the like due to stress when forming a source electrode and a drain electrode in a semiconductor device having a thin film transistor and a holding capacitance with three or more capacitance electrodes is provided. Before forming the source electrode and the drain electrode, a crystalline silicon film for relaxing the stress is formed, then a contact hole connecting to the semiconductor film of the thin film transistor is opened, and a metal film to be the source electrode and the drain electrode is formed.

Abstract: Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern. The heat treatment process includes diffuses the dopant into the semiconductor substrate.

Abstract: Embodiments of the present invention provide the ability to fabricate devices having similar physical dimensions, yet with different operating characteristics due to the different effective channel lengths. The effective channel length is controlled by forming an abrupt junction at the boundary of the gate and at least one source or drain. The abrupt junction impacts the diffusion during an anneal process, which in turn controls the effective channel length, allowing physically similar devices on the same chip to have different operating characteristics.

Abstract: A method of forming a semiconductor device includes forming line patterns on a substrate, the line patterns defining narrow and wide gap regions, forming spacer patterns in the narrow and wide gap regions on sidewalls of the line patterns, spacer patterns in the wide gap regions exposing an upper surface of the substrate, and spacer patterns in the narrow gap regions contacting each other to fill the narrow gap regions, forming an insulating interlayer to cover the spacer patterns and the line patterns, forming at least one opening through the insulating interlayer, the opening including at least one contact hole selectively exposing the upper surface of the substrate in the wide gap region, the contact hole being formed by using the spacer patterns in the narrow gap region as an etching mask, and forming a conductive pattern to fill the opening.

Abstract: A first and second gate electrodes are formed on a first and second active regions, respectively. The first and second gate electrodes have a first and second metal-containing conductive films, respectively. The first and second metal-containing conductive films are formed on the isolation region for segmenting the first and second active regions to be spaced apart from each other. A third metal-containing conductive film, which is a part of each of the first and second gate electrodes, is continuously formed from a top of the first metal-containing conductive film through a top of the isolation region to a top of the second metal-containing conductive film. The third metal-containing conductive film is in contact with the first and second metal-containing conductive films.

Abstract: A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the source/drain pattern. The metal germanosilicide layer is electrically connected to the source/drain pattern. Moreover, a proportion of germanium amount to the sum of the germanium amount and silicon amount in the metal germanosilicide layer is lower than that of germanium amount to the sum of the germanium amount and silicon amount in the source/drain pattern.

Abstract: Semiconductor fabricating technology is provided, and particularly, a method of fabricating a semiconductor device improving a contact characteristic between a silicon layer including carbon and a metal layer during a process of fabricating a semiconductor device is provided. A semiconductor device including the silicon layer including carbon and the metal layer formed on the silicon layer is provided. A metal silicide layer is interposed between the silicon layer including carbon and the metal layer.

Abstract: High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.

Abstract: Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.

Abstract: The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer.

Abstract: Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a first interconnection disposed on a substrate. The interconnection includes a first silicon interconnection region and a first metal interconnection region sequentially stacked on the substrate. A second interconnection includes a second silicon interconnection region and a second metal interconnection region that are stacked sequentially. The second silicon interconnection region has a lower resistivity than the first silicon interconnection region.

Abstract: First, a first layer made of Ni or an alloy including Ni may be formed on an upper surface of a semiconductor layer. Next, a second layer made of silicon oxide may be formed on an upper surface of the first layer. Next, a part, which corresponds to a semiconductor region, of the second layer may be removed. Next, second conductive type ion impurities may be injected from upper sides of the first and second layers to the semiconductor layer after the removing step.

Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode, a source region and a drain region, forming a first metal layer, forming silicide layers by first annealing, removing a remainder of the first metal layer after the first annealing, performing a second annealing, forming a second metal layer, performing a third annealing, and removing a remainder of the second metal layer.

Abstract: According to one embodiment, a semiconductor device includes a first transistor and a second transistor having a conductivity type which is different from a conductivity type of the first transistor, the first transistor and the second transistor being disposed on a semiconductor substrate such that a gate electrode of the first transistor and a gate electrode of the second transistor are connected to each other. The gate electrode of the first transistor includes first impurities and second impurities which suppress diffusion of the first impurities, and a concentration peak of the first impurities is formed at a shallower position than a concentration peak of the second impurities.

Abstract: A semiconductor device comprises a buffer layer 16 of an i-InAlAs layer formed over an SI-InP substrate 14, insulating films 24, 36 of BCB formed over the buffer layer 16, and a coplanar interconnection including a signal line 52 and ground lines 54 formed over the insulating film 36, a cavity 46 is formed in the SI-InP substrate 14, the buffer layer 16 and the insulating film below the signal line 52, and pillar-shaped supports in the cavity 46 support the insulating films 34, 36 which are the ceiling of the cavity 46.

Abstract: A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semiconductor material is removed from a first portion of the SOI semiconductor layer, wherein a remaining portion of the first conductivity in-situ doped first semiconductor material is present on a second portion of SOI semiconductor layer. A second conductivity in-situ doped second semiconductor material is formed on the first portion of the SOI semiconductor layer, wherein a mask prohibits the second conductivity in-situ doped semiconductor material from being formed on the second portion of the SOI semiconductor layer. The dopants from the first and second conductivity in-situ doped semiconductor materials are diffused into the first semiconductor layer to form dopant regions.

Abstract: An excessive metallic film on a device isolation region is prevented from contributing to silicidation in an end of a source-drain diffusion layer region to thereby form a silicide film with uniform film thickness. There are sequentially conducted a step of forming a device isolation region 3 in a substrate 1 including a silicon layer at least in a surface thereof and filling a first insulator in the device isolation region 3, a step of making height of an upper surface of the first insulator less than height of an upper surface of the substrate 1 and forming a sidewall film 10 on a sidewall of the device isolation region 3, and a step of depositing a metallic film 11 on the substrate 1 and then conducting silicidation through a thermal process.

Abstract: Semiconductor devices include a substrate having first and second active regions; a P-channel transistor associated with the first active region and including at least one of source and drain regions; an N-channel field-effect transistor associated with the second active region and including at least one of the source and drain regions; first and second contact pad layers each including silicon (Si) and SiGe epitaxial layers on the source and drain regions the SiGe epitaxial layers being sequentially stacked on the Si epitaxial layers; an interlayer insulating film; a first metal silicide film on the SiGe epitaxial layer of the P-channel transistor and a second metal silicide film on the Si epitaxial layer of the N-channel transistor; and contact plugs on the first and second metal silicide films.

Abstract: A thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device having the TFT, the TFT including a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the gate insulating layer and crystallized using a metal catalyst, and source and drain electrodes disposed on the semiconductor layer and electrically connected to source and drain regions of the semiconductor layer. A second metal is diffused into a surface region of the semiconductor layer, to getter the metal catalyst from a channel region of the semiconductor layer. The second metal can have a lower diffusion coefficient in silicon than the metal catalyst.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion thereof. A trench is disposed in the workpiece extending at least through the buried layer. At least one sinker contact is disposed in the top portion of the workpiece. The at least one sinker contact is proximate sidewalls of at least a portion of the trench and is adjacent the buried layer. An insulating material is disposed on the sidewalls of the trench. A conductive material is disposed within the trench and is coupled to a lower portion of the workpiece.

Abstract: The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer.

Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

Abstract: A fabricating method of a polysilicon layer is disclosed which can be applied for fabricating a semiconductor device such as a SRAM and so on. The method for fabricating the semiconductor device includes the steps of: forming a transistor included in the semiconductor device on a semi conductor substrate forming an insulating layer on the transistor; forming contact holes, through which a region of the transistor is exposed, by selectively removing the insulating layer forming a silicon layer in the contact holes forming a metal layer on the insulating layer and the silicon layer; forming a metal suicide layer through heat treatment of the silicon layer and the metal layer; removing the metal layer; forming an amorphous silicon layer on the insulating layer and the metal suicide layer; and forming a polysilicon layer through heat treatment of the amorphous silicon layer.

Abstract: A semiconductor device includes a dual gate CMOS logic circuit having gate electrodes with different conducting types and a trench capacitor type memory on a same substrate includes a trench of the substrate for the trench capacitor, a dielectric film formed in the trench, a first poly silicon film formed inside of the trench, and a cell plate electrode located above the dielectric film. The cell plate electrode includes a first poly silicon film formed on the dielectric film partially filling the trench, and a second poly silicon film formed on the first poly silicon film to completely fill the trench. The second poly silicon film includes a sufficient film thickness for forming gate electrodes, wherein the impurity concentration of the first poly silicon film is higher than the impurity concentration of the second poly silicon film.

Abstract: A phase change memory device is provided in which the area of contact between phase change material and heater electrode is reduced to suppress current required for heating and a phase change region is formed directly on a contact to raise the degree of integration. The device comprises a heater electrode in which the lower part thereof is surrounded by a side wall of a first insulating material and the upper part thereof protruding from the side wall has a sharp configuration covered by a second insulating material except for a part of the tip end thereof, and the exposed tip end is coupled to the phase change material layer.

Abstract: A method for fabricating a circuit structure is disclosed. The method includes depositing epitaxially a SiGe layer onto both NFET and PFET portions of a Si surface. Blanket disposing a first sequence of layers over the SiGe layer, including a high-k dielectric and a metal, and incorporating this first sequence of layers into the gatestacks and gate insulators of both NFET devices and PFET devices. This first sequence of layers is selected to yield desired device parameter values for the PFET devices. The method further includes removing the gatestack, the gate dielectric, and the SiGe layer, and re-forming the NFET devices by deploying a second sequence of layers that include a second high-k dielectric and a second metal. The second sequence of layers is selected to yield desired device parameter values for the NFET devices. A circuit structure is also disclosed. PFET devices have a gate dielectric with a high-k dielectric, a gatestack with a metal, and a silicide formed over the p-source/drain.

Abstract: A semiconductor device includes a gate electrode line provided to extend from an N-type area through a device isolation area to a P-type area, and source/drain diffused regions formed in N-type and P-type areas. The gate electrode line includes a first silicide region which configures a P-type MOSFET gate electrode and includes therein a silicide of metal M1, a second silicide region which configures an N-type MOSFET gate electrode and includes therein a silicide of metal M2, and an impurity-doped silicon region which is provided on a device isolation area and includes therein impurities at a higher concentration than both the gate electrodes.

Abstract: By forming a direct contact structure connecting, for instance, a polysilicon line with an active region on the basis of an increased amount of metal silicide by removing the sidewall spacers prior to the silicidation process, a significantly increased etch selectivity may be achieved during the contact etch stop layer opening. Hence, undue etching of the highly doped silicon material of the active region would be suppressed. Additionally or alternatively, an appropriately designed test structure is disclosed, which may enable the detection of electrical characteristics of contact structures formed in accordance with a specified manufacturing sequence and on the basis of specific design criteria.

Abstract: A CMOS device and method of forming the CMOS device. The device including a source and a drain formed in a semiconductor substrate, the source and the drain and separated by a channel region of the substrate; a gate dielectric formed on a top surface of the substrate and a very thin metal or metal alloy gate electrode formed on a top surface of the gate dielectric layer, a polysilicon line abutting and in electrical contact with the gate electrode, the polysilicon line thicker than the gate electrode. The method including, forming the gate electrode by forming a trench above the channel region and depositing metal into the trench.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a plurality of device isolation layers disposed in a semiconductor substrate, the device isolation layers extending in a word line direction and spaced apart from each other; a plurality of floating gate devices extending in a bit line direction perpendicular to the device isolation layer and spaced apart from each other; a source region and a drain region disposed at sides of the floating gate device; an insulation layer disposed on the floating gate device and the source region, and a polysilicon line extending in the word line direction and connected to the drain region.

Abstract: A monolithic pair of nanoscale probes, including: a substrate having a cavity that extends from a surface of the substrate into its body; a dielectric layer formed on the substrate; a pair of nanoscale probe precursors formed over the dielectric layer; a plurality of sub-monolayers of electrode material selectively atomic layer deposited over the pair of nanoscale probe precursors. The dielectric layer includes a window that extends through it to the cavity of the substrate such that a portion of the dielectric layer adjacent to the window extends over the cavity. The pair of nanoscale probe precursors includes a pair of edges facing each other across the window. These edges correspond to tips of the pair of nanoscale probes. The sub-monolayers of electrode material include the pair of edges, so that a distance between the tips of the nanoscale probes is between about 0.1 nm and about 20 nm.

Abstract: An integrated circuit is disclosed. One embodiment includes a first diode, a second diode, and a semiconductor line coupled to the first diode and the second diode. The line includes a first silicide region between the first diode and the second diode.

Abstract: A semiconductor device has a structure of contacts whose size and pitch are finer that those that can be produced under the resolution provided by conventional photolithography. The contact structure includes a semiconductor substrate, an interlayer insulating layer disposed on the substrate, annular spacers situated in the interlayer insulating layer, first contacts surrounded by the spacers, and a second contact buried in the interlayer insulating layer between each adjacent pair of the first spacers. The contact structure is formed by forming first contact holes in the interlayer insulating layer, forming the spacers over the sides of the first contact holes to leave second contact holes within the first contact holes, etching the interlayer insulating layer from between the spacers using the first spacers as an etch mask to form third contact holes, and filling the first and second contact holes with conductive material. In this way, the pitch of the contacts can be half that of the first contact holes.

Abstract: In this invention, etching is not performed in the step of planarizing a polycrystalline Si wafer, but only mechanical grinding is performed for planarization. This is because, since the etching rate is crystal-face dependent, etching of the polycrystalline Si wafer unavoidably results in formation of steps due to different crystal face orientations of individual crystal grains exposed on a surface of the wafer, thus hindering precision surface planarization. Subsequently, the Si wafer surface is coated with an oxide film to form an Si wafer with oxide film prior to the final polishing stage and then a surface of the oxide film is planarized, to give a planar substrate (i.e., Si substrate with oxide film) having no step on the surface thereof.

Abstract: A method for forming a metal silicide region in a silicon region of a semiconductor substrate. The method comprises forming a metal layer over the silicon region, then in succession forming a titanium and a titanium nitride layer thereover. As the substrate is heated to form the silicide, the titanium getters silicon dioxide on the surface of the silicon region and the titanium nitride promotes the formation of a smooth surface at the interface between the silicide layer and the underlying silicon region.

Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.

Abstract: Methods and apparatuses to selectively deposit a dielectric on a self-assembled monolayer (“SAM”) adsorbed metal are described. A wafer includes a device having a first electrode. A first self-assembled monolayer is deposited on the wafer covering the first electrode. Next, a portion of the first self-assembled monolayer is removed to expose the first electrode. The first self-assembled monolayer includes a hydrophobic layer. Further, second self-assembled monolayer is deposited on the first electrode. The second self-assembled monolayer includes a hydrophilic layer. Next, an insulating layer is deposited on the second self-assembled monolayer. Further, self-aligned contacts to one or more second electrodes of the device are formed.

Abstract: A semiconductor device includes a semiconductor substrate; an N-channel type transistor forming region formed on the semiconductor substrate; a P-channel type transistor forming region formed on the semiconductor substrate and arranged adjacent to the N-channel type transistor forming region; and a gate electrode formed on the semiconductor substrate over the N-channel type transistor forming region and the P-channel type transistor forming region. The gate electrode has a boundary inclusion portion formed in a first region including a boundary line between the N-channel type transistor forming region and the P-channel type transistor forming region and a boundary exclusion portion formed in a second region not including the boundary line. The gate electrode includes a conductive silicon layer and a metal silicide layer formed on the conductive silicon layer.

Abstract: Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface.