Abstract: A method and system for providing a bipolar transistor is described. The method and system include providing a compound base region, providing an emitter region coupled with the compound base region, and providing a collector region coupled with the compound base region. The bipolar transistor may also include at least one other predetermined portion. The method and system also include providing at least one predetermined amount of oxygen to at least one of the compound base region, the emitter region, the collector region, and the predetermined portion of the bipolar transistor.

Abstract: A hetero-BiMOS injection system comprises a MOSFET transistor formed on a substrate and a hetero-bipolar transistor formed within the substrate. The bipolar transistor can be used to inject charge carriers into a floating gate of the MOSFET transistor. This is done by operating the MOSFET transistor to form an inversion layer in its channel region and operating the bipolar transistor to drive minority charge carriers from the substrate into a floating gate of the MOSFET transistor. The substrate provides a silicon emitter and a silicon germanium containing base for the bipolar transistor. The inversion layer provides a silicon collector for the bipolar transistor.

Abstract: An isolated bipolar transistor formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains the bipolar transistor. The collector of the bipolar transistor may comprise the floor isolation region. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract: A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a second side of the collector region, and an emitter region of the first conduction type which is provided above the base region on the side remote from the collection region. A carbon-doped semiconductor region is provided on the first side alongside the collector region. The bipolar transistor is characterized in that the carbon-doped semiconductor region has a carbon concentration of 1019-1021 cm?3 and the base region has a smaller cross section than the collector region and the collector region has, in the overlap region with the base region, a region having an increased doping compared with the remaining region.

Abstract: Apparatus and a method are provided for reducing noise in mixed-signal and digital circuits. One apparatus (200) includes a metal-oxide-semiconductor field-effect transistor (MOSFET) (210). MOSFET (210) includes a doped substrate (2210) with a source formed proximate a substrate tie (2224) and a substrate tie (2250) adjacent substrate (2210). A ground rail (255) is coupled to the source and substrate tie (2224), and a ground rail (285) is coupled to substrate tie (2250). Ground rails (255) and (285) are configured to be coupled to different ground networks (250 and 280). One method includes producing a model of a semiconductor device including a standard semiconductor cell (710). The semiconductor cell is identified as a noise-sensitive or a noise-producing semiconductor cell (720), and the semiconductor cell is replaced with a corresponding noise-aware semiconductor cell (730).

Abstract: An inductor embedded in a substrate, including a substrate, a coil electrode formed by filling a metal in a spiral hole formed on the substrate, an insulation layer formed on the substrate, and an external connection pad formed on the insulation layer to be connected to the coil electrode. The inductor-embedded substrate can be used as a cap for a micro device package by forming a cavity on its bottom surface.

Abstract: A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and injected over a barrier to a floating gate of the cells.

Abstract: Embodiments discussed herein relate to processes of producing a field stop zone within a semiconductor substrate by implanting dopant atoms into the substrate to form a field stop zone between a channel region and a surface of the substrate, at least some of the dopant atoms having energy levels of at least 0.15 eV below the energy level of the conduction band edge of semiconductor substrate; and laser annealing the field stop zone.

Abstract: The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an n? type semiconductor layer in an SOI substrate. In addition, an n type impurity region is formed in the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly below an upper surface of the semiconductor layer between the source region and the drain region.

Abstract: The semiconductor device according to one of the aspects of the present invention includes a semiconductor substrate of a first conductivity type, having upper and lower surfaces. A collector region of a second conductivity type is formed on the lower surface of the semiconductor substrate, and a collector electrode is formed on the collector region. Also, at least one pair of isolation regions of the second conductivity type are formed extending from the upper surface of the semiconductor substrate to the collector layer for defining a drift region of the first conductivity type, in conjunction with the collector region. A base region of the second conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the drift region, and an emitter region of the first conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the base region. A gate electrode is formed opposing to the base region via an insulating layer.

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Abstract: A structure of an electrostatic discharge (ESD) device integrated with a pad is provided. The ESD device is integrated with the pad and formed under the pad. By using the area under the pad, the ESD device does not occupy additional space of an integrated circuit. Furthermore, since the pad is a large, plate, and ideal conductor, the connected pad and the ESD device are capable of distributing current in the ESD device averagely.

Abstract: A semiconductor system includes a self arc-extinguishing device, and an IGBT that works as a thyristor when a current between a first terminal and a second terminal connected to a second well electrode is small, and as a bipolar transistor when that current is large, and automatically switches between them according to the magnitude of the current. The IGBT is formed with a first conductivity-type semiconductor substrate. On a surface layer of the substrate is a second conductivity-type well region to which a first well electrode is connected. A first conductivity-type emitter region, to which an emitter electrode is connected, is disposed on a surface layer in the well region. A control electrode is disposed through an insulating film partially covering the well and emitter regions. A second conductivity-type well layer, to which the second well electrode is connected, is disposed on a back surface side of the substrate.

Abstract: An EEPROM memory cell uses an emitter polysilicon film for fabricating shallow source/drain regions to increase a breakdown voltage of the wells. The wells are fabricated to be approximately 100 nm (0.1 micrometers (?m)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.

Abstract: A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.

Abstract: A method of manufacturing a bipolar-complementary metal oxide semiconductor (BiCMOS) is provided. A gate in a CMOS area and a conductive layer pattern defining an opening, which opens an active region in a bipolar transistor area, are simultaneously formed by patterning a gate conductive layer. Thereafter, bipolar transistor manufacturing processes are performed while CMOS manufacturing processes are performed. Accordingly, the number of masks is decreased, and degradation of device characteristics is prevented.

Abstract: A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. A first isolation structure is formed adjacent at least a portion of the buried layer. A second isolation structure is formed adjacent at least a portion of the active region. A base layer is formed adjacent at least a portion of the active region. A dielectric layer is formed adjacent at least a portion of the base layer, and then at least part of the dielectric layer is removed at an emitter contact location and at a sinker contact location. An emitter structure is formed at the emitter contact location. Forming the emitter structure includes etching the semiconductor device at the sinker contact location to form a sinker contact region. The sinker contact region has a first depth. The method may also include forming a gate structure.

Abstract: A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the reverse leakage current and the on-voltage by bringing portions of an n?-type drift region 1 that extend between p-type base regions and an emitter electrode into Schottky contact to form Schottky junctions.

Abstract: An emitter switching configuration having at least one bipolar transistor and a MOS transistor having a common conduction terminal and a Zener diode inserted between a control terminal of the bipolar transistor and the common conduction terminal. A monolithic structure is also provided that is effective in implementing the emitter switching configuration.

Abstract: A PMOS transistor (Q2) provided for developing a short circuit between the base and emitter of an N-type IGBT during turn-OFF includes a P diffusion region (5), a P diffusion region (6), and a conductive film (10) and a second gate electrode (15) provided via a gate oxide film (21) on a surface of an N? epitaxial layer (2) between the P diffusion regions (5 and 6). The gate oxide film (21) is formed in a thickness having a gate breakdown voltage higher than the element breakdown voltage of a typical field oxide film and the like.

Abstract: The formation of vertical trench DMOS devices can be added to existing integrated BCD process flows in order to improve the efficiency of the BCD devices. The formation of this trench DMOS varies from existing approaches used with discrete trench DMOS devices, in that only two extra mask steps are added to the existing BCD process, instead of the 10 or so mask steps used in existing discrete trench DMOS processes. Further, the location of these additional heat cycles in the BCD process steps can be placed so as to have minimal impact on the other components created in the process. Utilizing an integrated trench device in a BCD process can offer at least a factor-of-two RDS(ON) area advantage over a planar counterpart.

Abstract: When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the collector of the NPN transistor between the emitter and collector of the PNP transistor.

Abstract: Bipolar transistors and methods for fabricating bipolar transistors are disclosed wherein an emitter-base dielectric stack is formed between emitter and base structures, comprising a carbide layer situated between first and second oxide layers. The carbide layer provides an etch stop for etching the overlying oxide layer, and the underlying oxide layer provides an etch stop for etching the carbide layer to form an emitter-base contact opening.

Abstract: The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of the source/drain regions of the FET to act as a storage node for the memory cell. The semiconductor material of the SOI constructions can comprise Si/Ge, and the active region of the FET can extend into the Si/Ge. The SOI constructions can be formed over any of a number of substrates, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metals and/or plastics.

Abstract: A semiconductor device includes a p?-silicon substrate, n?-epitaxial growth layers on the p?-silicon substrate, a field insulating film at the surface of the n?-epitaxial growth layer, an npn transistor formed at the n?-epitaxial growth layer, an pnp transistor formed at the n?-epitaxial growth layer, a DMOS transistor on the n?-epitaxial growth layer, and a resistance. The DMOS transistor includes an n+-diffusion layer forming a source, a p-type diffusion layer forming a back gate region, a lightly doped n-type diffusion layer forming a drain, and a heavily doped n+-diffusion layer forming the drain.

Abstract: A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminal portion side.

Abstract: Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the lightly-doped base region, a low-resistance current path into the base region may be provided. The low-resistance current path may be provided by a base conductor formed from heavily-doped epitaxial crystalline semiconductor. Metal-oxide-semiconductor (MOS) transistors with narrow gates may be formed on the same substrate as bipolar transistors. The MOS gates may be formed using a self-aligned process in which a patterned gate conductor layer serves as both an implantation mask and as a gate conductor. A base masking layer that is separate from the patterned gate conductor layer may be used as an implantation mask for defining the lightly-doped base region.

Abstract: A bipolar transistor structure is described incorporating an emitter, base, and collector having a fully depleted region on an insulator of a Silicon-On-Insulator (SOI) substrate without the need for a highly doped subcollector to permit the fabrication of vertical bipolar transistors on semiconductor material having a thickness of 300 nm or less and to permit the fabrication of SOI BiCMOS. The invention overcomes the problem of requiring a thick semiconductor layer in SOI to fabricate vertical bipolar transistors with low collector resistance.

Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

Abstract: A method for quantifying safe operating regions within a safe operating area (SOA) for a bipolar junction transistor (BJT) by driving the device under test (DUT) as part of a current mirror circuit and monitoring variances in the current mirror ratio for various biasing conditions.

Abstract: In a semiconductor device having a semiconductor element having a plurality of SOI-Si layers, the height of element isolation regions from the surface of the semiconductor substrate are substantially equal to each other. Alternatively, the element isolation regions are formed at the equal height on the semiconductor substrate and then a plurality of SOI-Si layers appropriately different in thickness are formed. In this manner, it is possible to obtain element isolation regions having substantially the same height from the semiconductor substrate and desired element regions having SOI-Si layers different in height. The thickness of a single crystalline silicon film (SOI-Si layer) may be appropriately changed by another method which includes depositing an amorphous silicon film and applying a heat processing to form an epi layer, and removing an unnecessary portion.

Abstract: A structure of and a method for making an isolated NMOS transistor using standard BiCMOS processing steps and techniques. No additional masks and processing steps are needed for the isolated NMOS device relative to the standard process flow. A P-type substrate with an overlaying buried N-type layer overlaid with a buried p-type layer below a P-well is shown. An N-type region surrounds and isolates the P-well from other devices on the same wafer. N+ regions are formed in the p-well for the source and drain connections and poly or other such electrical conductors are formed on the gate, drain and source structures to make the NMOS device operational. Parasitic bipolar transistors are managed by the circuit design, current paths and biasing to ensure the parasitic bipolar transistors do not turn on.

Abstract: The invention is directed to reducing of the number of steps in a BiCMOS process. A first N-well 3A and a second N-well 3B are formed deeply on a surface of a P-type semiconductor substrate. A first P-well 4A is formed in the first N-well 3A, and an N-channel MOS transistor is formed in the first P-well 4A. The second N-well 3B is used as a collector of a vertical NPN bipolar transistor. A second P-well 4B is formed in the second N-well 3B. The second P-well 4B is formed simultaneously with the first P-well 4A. The second P-well 4B is used as a base of the vertical NPN bipolar transistor. An N+ emitter layer and a P+ base electrode layer of the vertical NPN bipolar transistor are formed on a surface of the second P-well 4B.

Abstract: A semiconductor device in which a vertical pnp-bipolar transistor is formed in a prescribed element region on a semiconductor substrate includes: a buried n+-layer of a high concentration formed in the prescribed element region; and a p-type collector layer formed on the buried n+-layer. By introducing impurities that has a larger diffusion coefficient than the buried n+-layer, the collector layer can be formed on the buried n+-layer formed in common with other element regions, without any special masking.

Abstract: Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.

Abstract: A semiconductor device raises the maximum oscillation frequency fmax of the bipolar transistor. The stopper dielectric layer is formed on the substrate to cover the transistor section and the isolation dielectric. The interlayer dielectric layer is formed on the stopper dielectric layer. The base contact plug, which is formed in the interlayer dielectric layer, is located over the isolation dielectric in such a way as to contact the graft base region near its bottom end corner. Therefore, the base contact needs not to entirely overlap with the graft base region, which means that the graft base region can be narrowed without increasing the base resistance Rb and that the collector-base capacitance Ccb is reduced. Also, electrical short circuit between the graft base region and the collector region can be effectively suppressed by the stopper dielectric layer.

Abstract: A temperature-protected semiconductor switch having a semiconductor switch element composed of a number of cells connected in parallel and an integrated reverse diode, and further having a temperature sensor wherein the semiconductor switch element and the temperature sensor are integrated together in a semiconductor body of a first conductivity type. Upon occurrence of an excess temperature, the temperature sensor generates a first signal. A charge carrier detector is also provided which generates a second signal given the occurrence of free charged carriers caused by the integrated reverse diode in the semiconductor body. The first and second signals are supplied to an evaluation means that, for examples, undertakes the shut-off of the semiconductor switch only in the case of a true excess temperature.

Abstract: The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of the source/drain regions of the FET to act as a storage node for the memory cell. The semiconductor material of the SOI constructions can comprise Si/Ge, and the active region of the FET can extend into the Si/Ge. The SOI constructions can be formed over any of a number of substrates, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metals and/or plastics.

Abstract: A method including a buried layer formed on a semiconductor substrate, an active region formed adjacent to at least a portion of the buried layer, an isolation structure formed adjacent to at least a portion of the active region, and a gate oxide formed adjacent to at least a portion of the active region. The method also includes a polysilicon layer formed adjacent to at least a portion of the gate oxide having a portion removed to form a polysilicon definition structure that substantially surrounds and defines an emitter contact region. The method also includes forming a self-aligned implant region of the emitter contact region.

Abstract: A semiconductor structure includes a monocrystalline silicon substrate, an amorphous oxide material overlying the monocrystalline silicon substrate, a monocrystalline perovskite oxide material overlying the amorphous oxide material, and a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material. A composite transistor includes a first transistor having first active regions formed in the monocrystalline silicon substrate, a second transistor having second active regions formed in the monocrystalline compound semiconductor material, and a mode control terminal for controlling the first transistor and the second transistor.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: A bipolar transistor structure is described incorporating an emitter, base, and collector having a fully depleted region on an insulator of a Silicon-On-Insulator (SOI) substrate without the need for a highly doped subcollector to permit the fabrication of vertical bipolar transistors on semiconductor material having a thickness of 300 nm or less and to permit the fabrication of SOI BiCMOS. The invention overcomes the problem of requiring a thick semiconductor layer in SOI to fabricate vertical bipolar transistors with low collector resistance.

Abstract: An emitter switching configuration having at least one bipolar transistor and a MOS transistor having a common conduction terminal and a Zener diode inserted between a control terminal of the bipolar transistor and the common conduction terminal. A monolithic structure is also provided that is effective in implementing the emitter switching configuration.

Abstract: A Bipolar Junction Transistor (BJT) that reduces the variation in the current gain through the use of a trench pullback structure. The trench pullback structure is comprised of a trench and an active region. The trench reduces recombination in the emitter-base region through increasing the distance charge carriers must travel between the emitter and the base. The trench also reduces recombination by reducing the amount of interfacial traps that the electrons injected from the emitter are exposed to. Further, the trench is pulled back from the emitter allowing an active region where electrons injected from a sidewall of the emitter can contribute to the overall injected emitter current. This structure offers the same current capability and current gain as a device without the trench between the emitter and the base while reducing the current gain variation.

Abstract: A semiconductor integrated circuit device includes: a substrate; a first conductivity type of semiconductor layers arranged above the substrate as being insulated from the substrate and insulated from each other; cell transistors formed on the respective semiconductor layers, each of which has a second conductivity type of source, drain layers and a gate electrode to store data in a channel body thereof corresponding to an accumulation state of majority carriers; and the first conductivity type of emitter layers formed in the respective semiconductor layers to be contacted to the respective drain layers of the cell transistors so as to constitute PN junctions therebetween, the emitter layers serving for injecting majority carriers into the respective channel bodies of the cell transistors.

Abstract: A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.

Abstract: An evaluation configuration has a first MOS evaluation stage, an isolation stage, and a bipolar evaluation stage. The isolation stage is connected between the first MOS evaluation stage and the bipolar evaluation stage. The isolation stage isolates the first MOS evaluation stage from the bipolar evaluation stage. The evaluation configuration can reliably detect very small read signals and allows a high integration density.

Abstract: In the manufacturing process of a Bi-CMOS semiconductor device, which includes a CMOSFET and a bipolar transistor, the steps for forming a well region, source regions, and drain regions of the CMOSFET are also used for forming the bipolar transistor. One of the steps is used for introducing impurities of the same conductivity type in a surface of a base region of the bipolar transistor in order to form a high impurity concentration region in the surface. The high impurity concentration region is formed such that the distance between an emitter region of the bipolar transistor and the high impurity concentration region becomes 1 to 2 &mgr;m. The shift in device characteristics of the bipolar transistor is improved by the high impurity concentration region even if the impurity concentration is relatively low at the surface of the base region of the bipolar transistor.

Abstract: A semiconductor device in accordance with present invention includes a first conduction type first semiconductor layer; a second conduction type second semiconductor layer which is formed on the first semiconductor layer and has a substantially uniform impurity concentration; a plurality of first conduction type base layers formed in the surface of the second semiconductor layer; a plurality of second conduction type emitter layers formed in the surfaces of the respective base layers; channel regions formed in the surfaces of the respective base layers and between the emitter layers and the second semiconductor layer; a first conduction type auxiliary base layer formed in the surface of the second semiconductor layer between two base layers adjacent to each other; a gate electrode formed via a gate insulating film on the second semiconductor layer between the auxiliary base layer and the two base layers and on the channel regions; an emitter electrode connected to the base layers and the emitter layers; and a

Abstract: A protection circuit prevents a circuit component from static charge unavoidably applied to a signal terminal, and includes a vertical bipolar transistor having an n-type deep well serving as an emitter region, a p-type well formed on the n-type deep well and serving as a base region and an n-type impurity region formed in the p-type well and serving as a collector region so as to reduce a base resistance regardless of a shallow trench isolation.