Abstract: The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of the source/drain regions of the FET to act as a storage node for the memory cell. The semiconductor material of the SOI constructions can comprise Si/Ge, and the active region of the FET can extend into the Si/Ge. The SOI constructions can be formed over any of a number of substrates, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metals and/or plastics.

Abstract: The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of the source/drain regions of the FET to act as a storage node for the memory cell. The semiconductor material of the SOI constructions can comprise Si/Ge, and the active region of the FET can extend into the Si/Ge. The SOI constructions can be formed over any of a number of substrates, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metals and/or plastics.

Abstract: A semiconductor device 1000 may include first and second switch elements 1000A and 1000B formed in first and second element forming regions 16a and 16b of a SOI layer 10a, respectively. The first and second switch elements 1000A and 1000B form a BiCMOS inverter circuit, and each includes a field effect transistor and a bi-polar transistor. A first p-type body region 50a is electrically connected to an n-type source region 120. The first p-type body region 50a is electrically connected to a first p-type base region 220. A second n-type body region 54a is electrically connected to a second n-type collector region 430. A p-type drain region 330 is electrically connected to a second p-type base region 420.

Abstract: A structure and a process for fabricating a bipolar junction transistor (BJT) that is compatible with the fabrication of a vertical MOSFET is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate, where the substrate includes a buried collector region for the BJT and a source region for the MOSFET. After the at least three layers are formed on the substrate, two windows or trenches are formed in the layers. The first window terminates at the surface of the silicon substrate where the source region has been formed; the second window terminates at the buried collector region. Both windows are then filled with semiconductor material. For the BJT, the bottom portion of the window is filled with material of a conductivity type matching the conductivity of the buried collector, while the upper region of the semiconductor material is doped the opposite conductivity to form the BJT base.

Abstract: A semiconductor integrated circuit includes cells, cell rows and potential feeders. Each cell includes a partial trunk that is used to constitute a power supply trunk and/or a ground trunk, and that is electrically isolated from the remaining components within the cell. Each cell row includes a plurality of cells placed adjacently, and the power supply trunk and/or ground trunk composed of the partial trunks. The potential feeders selectively connect one of the power supply trunk and ground trunk of any one of the plurality of cell rows to the components within the cells to supply them with the potential of the power supply trunk and/or ground trunk. This enables the components in the adjacent cells to be supplied with different potentials.

Abstract: A semiconductor device 1000 may include an element isolation region 14, an n-type field effect transistor 100 and an npn-type bipolar transistor 200 formed on a SOI substrate 10. A p-type body region 50a may be electrically connected to an n-type source region 120. The p-type body region 50a may be electrically connected to a p-type base region 220. An n-type drain region 130 may be electrically connected to an n-type collector region 230. An n-type source region 120 may be formed structurally isolated from an n-type emitter region 210.

Abstract: The memory cell is formed in a body of a P-type semiconductor material forming a channel region and housing N-type drain and source regions at two opposite sides of the channel region. A floating gate region extends above the channel region. A P-type charge injection region extends in the body contiguously to the drain region, at least in part between the channel region and the drain region. An N-type base region extends between the drain region, the charge injection region, and the channel region. The charge injection region and the drain region are biased by special contact regions so as to forward bias the PN junction formed by the charge injection region and the base region. The holes thus generated in the charge injection region are directly injected through the base region into the body, where they generate, by impact, electrons that are injected towards the floating gate region.

Abstract: A vertical bipolar transistor having low breakdown voltage, low ESD clamping voltage and high beta is fabricated in a semiconductor 301 of a first conductivity type, which has a buried layer 360 of the opposite conductivity type with sharp junctions, suitable as collector. This layer extends laterally to deep wells 371 of the opposite conductivity type, thus isolating the subsurface band 301a of the semiconductor of the first conductivity type. This band is suitable as the base and has a width 301c controlled by the proximity of the buried layer junction 360a. The emitter 310 is supplied by a surface region of the opposite conductivity type. The photomask, which is needed for implanting the low energy ions to create the extended emitter, is also used for the process step of implanting, at high energy and high dose, the ions needed (opposite conductivity type) to create the buried layer.

Abstract: In a semiconductor device having a semiconductor element having a plurality of SOI-Si layers, the height of element isolation regions from the surface of the semiconductor substrate are substantially equal to each other. Alternatively, the element isolation regions are formed at the equal height on the semiconductor substrate and then a plurality of SOI-Si layers appropriately different in thickness are formed. In this manner, it is possible to obtain element isolation regions having substantially the same height from the semiconductor substrate and desired element regions having SOI-Si layers different in height. The thickness of a single crystalline silicon film (SOI-Si layer) may be appropriately changed by another method which includes depositing an amorphous silicon film and applying a heat processing to form an epi layer, and removing an unnecessary portion.

Abstract: A triple poly nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor operates as a charge injector. The charge injector may provide electrons for substrate hot electron injection of electrons onto the floating gate for programming. The select transistor may include a gate formed as a self-aligned sidewall spacer on said sense transistor.

Abstract: A method is disclosed for the improvement of BiCMOS or CMOS manufactured device performance, specifically bipolar junction transistor performance, in a cost effective manner. The method provides for fewer masking operations during bipolar junction transistor formation, in a CMOS flow process, yet also provides for the bipolar junction transistor to be optimized.

Abstract: The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

Abstract: A metal oxide semiconductor field effect transistor structure is disclosed. A p-shape gate, disposed over a semiconductor substrate. A gate dielectric layer is disposed in between the p-shape gate and the semiconductor substrate. A drain region is disposed within the semiconductor substrate, wherein the drain region is surrounded by the p-shape gate. A source region is disposed within the semiconductor substrate, wherein the source region surrounds the p-shape gate. A silicide structure is disposed on the source/drain regions and the p-shape gate.

Abstract: A transistor that includes a doped buried region 320 within a semiconductor body 300, 340. The doped buried region includes a portion having a first thickness 348 and a second thickness, the first thickness being less than the second thickness. In one embodiment the first thickness is about half the second thickness. The transistor also includes a collector region 342 over the buried region, a base region 396 within the collector region, and an emitter region 422 within the base region.

Abstract: An electronic device, integrated monolithically in a semiconductor substrate and comprising a bipolar transistor connected in series to at least one MOS transistor, the bipolar transistor having a base region that includes a first buried region and a first diffused region extending continuously from the substrate surface down to the buried region, and the diffused region is bordered by an isolation trench region extending in the buried region.

Abstract: Form a semiconductor device with dielectric, isolation structures in a top surface of a silicon semiconductor substrate, separating the substrate into emitter, NMOS and PMOS areas. Form a gate oxide layer above the isolation structures on the top surface of the silicon semiconductor substrate. Form a conductive polysilicon layer above the thin silicon oxide layer. Mask the NMOS and PMOS regions of the substrate with an emitter mask having a window over the emitter area of the substrate. Ion implant emitter dopant into a portion of the conductive polysilicon layer over the emitter area of the substrate through the window in the emitter mask. Strip the emitter mask. Anneal the substrate including the thin silicon oxide layer, and the polysilicon layer to drive the dopant into an emitter region in the emitter area in the substrate. Form doped source/drain regions and a base in the emitter area of the substrate.

Abstract: A bipolar transistor has metal silicide as a base lead-out electrode instead of conventional polysilicon, and the metal silicide film extends to an edge of an etching stopper layer, to reduce an emitter resistance and restrain an occurrence of an emitter plug effect. Such bipolar transistor can be utilized in a CMOS semiconductor device.

Abstract: A high voltage MOSgated semiconductor device has a generally linear MOSFET type forward current versus forward voltage characteristic at low voltage and the high current, low forward drop capability of an IGBT. The device is particularly useful as the control transistor for a television tube deflection coil. The device is formed by a copacked discrete IGBT die and power MOSFET die in which the ratio of the MOSFET die area is preferably about 25% that of the IGBT. Alternatively, the IGBT and MOSFET can be integrated into the same die, with the IGBT and MOSFET elements alternating laterally with one another and overlying respective P+ injection regions and N+ contact regions respectively on the bottom of the die. The MOSFET and IGBT elements are preferably spaced apart by a distance of about 1 minority carrier length (50-100 microns for a 1500 volt device).

Abstract: The present invention creates a useful BJT by increasing the gain associated with the parasitic BJT on an SOI or bulk type MOSFET. This is done by masking those manufacturing steps that minimize the BJT's beta value, by intentionally increasing the beta value of the BJT, and by driving the base of the BJT with the circuit. Once the gain is increased sufficiently, the BJT may be used productively in the circuit. Because the physical structure of the BJT is already part of the silicon water, its productive use does not require additional space.

Abstract: An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of the P type buried layer dopant is greater than the N type buried layer dopant so that connections can be made to the P type buried layer by P wells which have a lower dopant concentration than the N buried layer.

Abstract: A semiconductor device includes an active layer of a first conductive type. A base layer of a second conductive type is selectively formed on a surface region of said active layer. A source layer of the first conductive type is selectively formed on a surface region of the base layer. An anode layer of the second conductive type is selectively formed on a surface region of the active layer, the anode layer being spaced from the base layer. A drain layer of the first conductive type is formed on a surface region between the base layer and the anode layer. A resistive layer of the first conductive type is formed on a surface region between the base layer and the drain layer. And, a gate electrode is formed above a region of the base layer between the source layer and the active layer, a gate insulating film being disposed between the base layer and the gate electrode.

Abstract: The preferred embodiment of the present invention provides a buried layer that improves the latch up immunity of digital devices while providing isolation structures that provide noise isolation for both the digital and analog devices. The buried layer of the preferred embodiment is formed to reside within or below the subcollector region in the transistor. Additionally, in the preferred embodiment the subcollector is isolated from buried layer outside the transistor region by deep isolation trenches formed at the edges of the subcollector. Additionally, an array of deep isolation trenches provides increased isolation between devices where needed. Thus, the preferred embodiment of the present invention provides an integrated circuit structure and method that provides improved latchup immunity while also providing improved noise tolerance.

Abstract: An IGBT has a thick buffer region with increased doping to improve self-clamped inductive switching and device manufacture. A planar or trench gate IGBT has a buffer layer more than 25 microns thick. The buffer layer is doped high enough so that its carriers are more numerous than minority carriers, particularly at the transition between the N buffer & N drift region.

Abstract: A semiconductor wafer has a first element forming section, a second element forming section adjoining the first element forming section, and a third element forming section adjoining the second element forming section. The first element forming section has a first supporting substrate, a first buried insulating film formed on the first supporting substrate, and a first active layer formed on the first buried insulating film. The second element forming section has a second supporting substrate, a second buried insulating film formed on the second supporting substrate, and a second active layer formed on the second buried insulating film. The second active layer has a thickness being different from a thickness of the first active layer. The third element forming section has a third active layer.

Abstract: An insulated gate bipolar transistor includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on a top surface of the first semiconductor layer, a base layer of the first conductivity type formed on a top surface of the second semiconductor layer, a plurality of gate electrodes each of which is buried in a trench with a gate insulation film interposed therebetween, the trench being formed in the base layer to a depth reaching said second semiconductor layer from a surface of the base layer, each the gate electrode having an upper surface of a rectangular pattern with different widths in two orthogonal directions, the gate electrodes being disposed in a direction along a short side of the rectangular pattern, and emitter layers of the second conductivity type formed in the surface of the base layer to oppose both end portions of each the gate electrode in a direction along a long side of the rectangular pattern.

Abstract: A semiconductor circuit is provided which has a high breakdown voltage and is capable of outputting a large current. Field transistors (Q1, Q11) are cross-coupled. The gate of the first field transistor (Q1) and the drain of the second field transistor (Q11) are not directly connected to the drain of an MOS transistor (Q4) but are connected to the base of a bipolar transistor (Q12). The second field transistor (Q11) has its source connected to the collector of the bipolar transistor (Q12) and the MOS transistor (Q4) has its drain connected to the emitter of the bipolar transistor (Q12). When the current amplification factor of the bipolar transistor (Q12) is taken as &bgr;, then the current of the output (SO) can be increased approximately &bgr; times.

Abstract: An insulated gate transistor comprising a first semiconductor region, a second semiconductor region includes plural portions, a third semiconductor region, a fourth semiconductor region, a first insulation layer, control electrodes, a first main electrode, and a second main electrode, wherein a metallic wiring layer is provided on the first main surface plane via an insulating layer, plural regions insulated from the first main electrode are provided through said first main electrode, and the metallic wiring layer is connected electrically to the control electrode through the insulating layer via the region insulated from the main electrode.

Abstract: Terminal regions of source/drain zones of an MOS transistor are configured over the substrate in the form of conductive structures, are separated from the substrate by separating layers, and exhibit a larger horizontal cross-section than doped regions forming the source/drain zones that are arranged in the substrate.

Abstract: A semiconductor device causes less element characteristic fluctuation and hardly causes parasitic actions even when a wire having a barrier metal made of a titanium material is provided. The semiconductor device includes a MOS transistor provided on the surface side of a semiconductor substrate, a first silicon oxide film, a silicon nitride film and a second silicon oxide film provided on the semiconductor substrate while covering the MOS transistor, and a wire having a barrier metal made of titanium material and provided on the insulating film, wherein the silicon nitride film covers the MOS transistor and has an opening on an element isolating region for isolating the MOS transistors. The silicon nitride film is formed in one and the same process as that of a dielectric film of a capacitor element.

Abstract: An LDMOS structure is formed in a region of a first type of conductivity of a semiconductor substrate and comprises a gate, a drain region and a source region. The source region is formed by a body diffusion of a second type of conductivity within the first region, and a source diffusion of the first type of conductivity is within the body diffusion. An electrical connection diffusion of the second type of conductivity is a limited area of the source region, and extends through the source diffusion and reaches down to the body diffusion. At least one source contact is on the source diffusion and the electrical connection diffusion. The LDMOS structure further comprises a layer of silicide over the whole area of the source region short-circuiting the source diffusion and the electrical connection diffusion. The source contact is formed on the silicide layer.

Abstract: A vertical MOS semiconductor device exhibits a high breakdown voltage and low on-resistance, reduces the tradeoff relation between the on-resistance and the breakdown voltage, and realizes high speed switching. The semiconductor device has a breakdown-voltage sustaining layer, such as an n-type drift layer, and a well region, such as a p-type well region, in the breakdown-voltage sustaining layer. The resistivity &rgr; (&OHgr;cm) of the breakdown-voltage layer is within a range expressed in terms of the breakdown voltage Vbr (V). The semiconductor device also has stripe shaped surface drain regions that extend from the well region and are surrounded by the well region. The surface area ratio between surface drain regions and the well region, which includes the source region, is from 0.01 to 0.2.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: In a semiconductor device having high voltage resistance and low ON voltage characteristics, charge-storage regions (insulation layer) are formed in a drift region. Formed above the drift region are a channel region, an emitter region, trench-type gate electrodes, and an emitter electrode. Strips of the insulation layer extend in a direction intersecting a direction of extension of the gate electrodes, and form a stripe pattern. The insulation layer curbs extraction of holes into the channel region. Openings in the stripe pattern of the insulation layer form depletion layers.

Abstract: A semiconductor structure for a high frequency monolithic switch matrix includes a monocrystalline silicon substrate, an amorphous oxide material overlying the monocrystalline silicon substrate, a monocrystalline perovskite oxide material overlying the amorphous oxide material, a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material, and a high frequency semiconductor integrated formed in and over the monocrystalline compound semiconductor material having one or more input ports and one or more output ports. The high frequency semiconductor integrated circuit also includes a high frequency switch circuit that is electrically coupled to a switch driver control circuit that is fabricated on the monocrystalline compound semiconductor material and which provides the DC signals required to control the high frequency circuit.

Abstract: A semiconductor structure includes a monocrystalline silicon substrate, an amorphous oxide material overlying the monocrystalline silicon substrate, a monocrystalline perovskite oxide material overlying the amorphous oxide material, and a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material. A composite transistor includes a first transistor having first active regions formed in the monocrystalline silicon substrate, a second transistor having second active regions formed in the monocrystalline compound semiconductor material, and a mode control terminal for controlling the first transistor and the second transistor.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: High quality epitaxial layers of monocrystalline oxide materials (24) are grown overlying monocrystalline substrates such as large silicon wafers (22) using RHEED information to control the stoichiometry of the growing film. The monocrystalline oxide layer (24) may be used to form a compliant substrate for monocrystalline growth of additional layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer (24) on a silicon wafer (22) spaced apart from the silicon wafer (22) by an amorphous interface layer of silicon oxide (28). The amorphous interface layer (28) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer (24).

Abstract: The semiconductor switching element blocks in both directions between a first and a second load terminal. The switching element has a field effect transistor and a bipolar transistor. The field effect transistor has a controlled gate, a source connected to the first load terminal, a drain connected to the second load terminal and a body connection. The bipolar transistor has a base, an emitter, and a collector. The emitter is connected to the body connection of the field effect transistor.

Abstract: Power combining amplifiers using two different monocrystalline materials in a monolithic device are provided. High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract: Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate type transistor formed in the semiconductor layer, a highly-doped collector layer of a bipolar transistor embedded in an insulating-layer-free portion of the semiconductor substrate, and a low-doped collector layer disposed on the highly-doped collector layer of the bipolar transistor, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of the insulating layer so as to attain high breakdown voltage and high speed operation of the bipolar transistor.

Abstract: An N type buried layer is buried in a P type silicon substrate. An N type epitaxial layer is formed on this buried layer. A P type intrinsic base region and an extrinsic base region are formed on the surface of the epitaxial layer. An N type emitter region is formed in the intrinsic base region. An emitter electrode is formed to contact the emitter region. A collector plug region is formed in an area separated from the extrinsic base region through a filed insulating film. A cobalt silicide film is formed on the extrinsic base region to surround the emitter electrode. An extrinsic base contact hole is formed at only one side of the emitter electrode. In the semiconductor device, the base resistance Rb and the collector-base capacity Ccb are reduced to make the maximum oscillation frequency fmax sufficiently large.

Abstract: A semiconductor device may include an element isolation region 14, an npn-type bipolar transistor 200, and a p-type field effect transistor 100, which are formed on a SOI substrate. The bi-polar transistor 200 and the field effect transistor 100 are formed in the same element forming region 16. An n-type body region 52a is electrically connected to an n-type collector region 230. A p-type source region 210 is electrically connected to the n-type collector region 230. A p-type drain region 130 is electrically connected to a p-type base region 220.

Abstract: A voltage controlled capacitor sandwiched between a buried oxide and a shallow trench insulator to form a near ideal P+ to n-well diode with minimal parasitic capacitance and resistance.

Abstract: A semiconductor device and a method of producing the same are disclosed. After boron or similar p-type impurity has been introduced into a polysilicon layer constituting a pMOS gate, annealing can be effected at an optimal temperature low enough to prevent the impurity from entering a silicon substrate via a gate oxide film, e.g., 800° C. or below in the case of boron. This prevents the characteristic of a transistor, e.g., threshold voltage from being varied. Further, in an nMOS gate electrode and source-drain region, the n-type impurity can be provided with a concentration reducing the resistance of a silicide layer. In addition, in the emitter diffusion layer of a bipolar transistor, the concentration of the n-type impurity does not fall and allows a current amplification factor to be increased while allowing an emitter resistance to be reduced.

Abstract: An ESD power clamp circuit provides ESD protection for semiconductor chips through a power clamping device. The power clamping device includes a FET and a bipolar element, formed in an isolation region, and a buried diffusion. The buried diffusion is used as a subcollector for the bipolar element, and is used as an isolation for the FET.

Abstract: An N type buried layer is buried in a P type silicon substrate. An N type epitaxial layer is formed on this buried layer. A P type intrinsic base region and an extrinsic base region are formed on the surface of the epitaxial layer. An N type emitter region is formed in the intrinsic base region. An emitter electrode is formed to contact the emitter region. A collector plug region is formed in an area separated from the extrinsic base region through a filed insulating film. A cobalt silicide film is formed on the extrinsic base region to surround the emitter electrode. An extrinsic base contact hole is formed at only one side of the emitter electrode. In the semiconductor device, the base resistance Rb and the collector-base capacity Ccb are reduced to make the maximum oscillation frequency fmax sufficiently large.

Abstract: A semiconductor device 1 comprises a body 2 of insulating material having a surface 3 to which a semiconductor element 4 and an interconnect structure 5 are fastened, which interconnect structure 5 is disposed between the semiconductor element 4 and the body 2 of insulating material and has a patterned metal layer 7 facing the body 2 of insulating material, which patterned metal layer 7 comprises conductor tracks 8 and 9. In order to reduce the power consumption of the semiconductor device 1, an insulating layer 12 having a dielectric constant ∈r below 3 is disposed between the patterned metal layer 7 of the interconnect structure 5 and the body 2 of insulating material, and an insulating barrier layer 13 is disposed between the semiconductor element 4 and the insulating layer 12 having a dielectric constant ∈r below 3, so as to counteract that contaminants from the insulating layer 12 having a dielectric constant ∈r below 3 can reach the semiconductor element 4.

Abstract: According to the present invention, there are proposed semiconductor devices each constituted in such a manner that the ON resistance thereof is lowered without increasing the area of the element. More specifically, as the insulated gate structure, there is used a trench gate structure constituted in such a manner that a gate electrode is formed in a state buried, through a gate insulation film, in trenches formed in the surface of an n-type high-resistance layer. Further, an n-type RESURF (Reduced Surface Field) diffused-layer extending as far as the trenches in a state contacted with the n-type drain layer is formed in the surface of the n-type high-resistance layer. As a result, the channel width can be increased with the area of the element remaining unvaried corresponding to the depth of the trenches to thereby reduce the channel resistance.

Abstract: A circuit incorporated IGBT is provided with a semiconductor substrate having an IGBT area and a circuit area which are adjacent to each other. In a semiconductor layer of one conductivity type in which a circuit element is formed in the circuit area, there is provided another semiconductor layer of another conductivity type which adjoins the circuit element and has an impurity concentration higher than that of the semiconductor layer of the one conductivity type. An electrode contacts the other semiconductor layer and is connected to an electrode of the IGBT. Carriers are ejected from the other semiconductor layer to the electrode of the IGBT, thereby making it possible to prevent an erroneous operation of the circuit.

Abstract: A semiconductor device 1000 may include an element isolation region 14, an n-type field effect transistor 100 and an npn-type bipolar transistor 200 formed on a SOI substrate 10. A p-type body region 50a may be electrically connected to an n-type source region 120. The p-type body region 50a may be electrically connected to a p-type base region 220. An n-type drain region 130 may be electrically connected to an n-type collector region 230. An n-type source region 120 may be formed structurally isolated from an n-type emitter region 210.