Abstract: A semiconductor device includes: a semiconductor substrate divided into a first region and a second region; a first MIS transistor formed in the first region of the semiconductor substrate and including a stack of a first gate insulating film and a fully-silicided first gate electrode; and a second MIS transistor formed in the second region of the semiconductor substrate and including a stack of a second gate insulating film and a fully-silicided second gate electrode. The second gate electrode has a gate length larger than that of the first gate electrode. A middle portion in the gate length direction of the second gate electrode has a thickness smaller than the thickness of the first gate electrode.

Abstract: A semiconductor device comprising a multi Fin-FET structure capable of suppressing short channel effects, controlling a threshold voltage, driving a high current, and operating in a high-speed comprises a source region and a drain region disposed on a semiconductor substrate, a plurality of fins interconnecting the source region and drain region, a first gate electrode disposed on the semiconductor substrate and to one side face of each fin, a second gate electrode disposed on the semiconductor substrate and to the other side face of the fin to face the first gate electrode, and separated from the first gate electrode, a plurality of first pad electrodes connected to respective first gate electrode, a first wiring interconnecting the plurality of first pad electrodes, a plurality of second pad electrodes connected to respective second gate electrode, and a second wiring interconnecting the plurality of second pad electrodes.

Abstract: A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in the substrate beside the spacer, and then an S/D region is formed in or on the substrate at the bottom of the opening. A metal silicide layer is formed on the S/D region and the gate structure, and then a stress layer is formed over the substrate.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) which is provided with at least one semiconductor element (E), wherein on the surface of the semiconductor body (12) a mesa-shaped semiconductor region (1) is formed, an insulating layer (2) is deposited over the mesa-shaped semiconductor region (1) having a smaller thickness on top of the mesa-shaped semiconductor region (1) than in a region (3) bordering the mesa-shaped semiconductor region (1), subsequently a part of the insulating layer (2) on top of the mesa-shaped semiconductor region (1) is removed freeing the upper side of the mesa-shaped semiconductor region (1), and subsequently a conducting layer (4) contacting the mesa-shaped semiconducting region (1) is deposited over the resulting structure. According to the invention the insulating layer (2) is deposited using a high-density plasma deposition process.

Abstract: The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation 112 and then an extended cleaning operation 114 that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation 114 is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation 112.

Abstract: Switches having an in situ grown carbon nanotube as an element thereof, and methods of fabricating such switches. A carbon nanotube is grown in situ in mechanical connection with a conductive substrate, such as a heavily doped silicon wafer or an SOI wafer. The carbon nanotube is electrically connected at one location to a terminal. At another location of the carbon nanotube there is situated a pull electrode that can be used to elecrostatically displace the carbon nanotube so that it selectively makes contact with either the pull electrode or with a contact electrode. Connection to the pull electrode is sufficient to operate the device as a simple switch, while connection to a contact electrode is useful to operate the device in a manner analogous to a relay. In various embodiments, the devices disclosed are useful as at least switches for various signals, multi-state memory, computational devices, and multiplexers.

Abstract: A transistor and method of manufacturing thereof. A gate dielectric and gate are formed over a workpiece, and the source and drain regions of a transistor are recessed. The recesses are filled with a dopant-bearing metal, and a low-temperature anneal process is used to form doped regions within the workpiece adjacent the dopant-bearing metal regions. A transistor having a small effective oxide thickness and a well-controlled junction depth is formed.

Abstract: A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.

Abstract: Methods of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, and then laser annealing the substrate.

Abstract: A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and a capacitor. A source of the switching device may be connected to a first end of a metal-insulator transition film resistor, and at least one electrode of the capacitor may be connected to a second end of the metal-insulator transition film resistor. The metal-insulator transition film resistor may transition between an insulator and a conductor according to a voltage supplied to the first and second ends thereof.

Abstract: Methods of forming silicided contacts self-aligned to a gate from polysilicon germanium and a structure so formed are disclosed. One embodiment of the method includes: forming a polysilicon germanium (poly SiGe) pedestal over a gate dielectric over a substrate; forming a poly SiGe layer over the poly SiGe pedestal, the poly SiGe layer having a thickness greater than the poly SiGe pedestal; doping the poly SiGe layer; simultaneously forming a gate and a contact to each side of the gate from the poly SiGe layer, the gate positioned over the poly SiGe pedestal; annealing to drive the dopant from the gate and the contacts into the substrate to form a source/drain region below the contacts; filling a space between the gate and the contacts; and forming silicide in the gate and the contacts.

Abstract: A semiconductor device and method of its manufacture is disclosed. The device comprises an active semiconductor region (1A) comprising one or more conductive gates (11) and a contact region (1 B) remote from the active region (1A), typically comprising a field oxide region (3). An insulating layer (17) overlies the remote contact region (1 B) and at least a part of the active semiconductor region (1A) with one or more contact windows (19a) formed therethrough at locations between the conductive gates (11). A metallisation contact pad (23) overlying the insulating layer (17) is provided in the remote contact region (1 B). The metallisation contact pad (23) is contacted with a polysilicon contact strip (15) underlying the insulating layer (17) by a conductive pattern of a plurality of filled contact windows (19b) extending across a substantial part of the area of the contact pad (23). In a preferred embodiment, the pattern is a series of filled parallel trenches.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions between the gate patterns include first spaces having a first width and second spaces having a second width greater than the first width. Spacers are formed on sidewalls of the second spaces, and spacer layer patterns filling the first spaces are also formed together with the spacers. The spacers are selectively removed to expose the sidewalls of the first spaces. As a result, the semiconductor integrated circuit includes wide spaces enlarged by the removal of the spacers and narrow and deep spaces filled with the spacer layer patterns.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a body pattern of a first conductivity type disposed on an insulating layer. A gate electrode is disposed on the body pattern. A drain region of a second conductivity type is disposed on the insulating layer and having a sidewall in contact with a first sidewall of the body pattern. An impurity-doped region of the first conductivity type is disposed on the insulating layer and having a sidewall in contact with a second sidewall of the body pattern. The MOSFET further includes a source region of the second conductivity type disposed on the impurity-doped region and having a sidewall in contact with the second sidewall of the body pattern, and a contact plug extending through the source region to contact the impurity-doped region.

Abstract: A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.

Abstract: A field effect transistor (“FET”) is formed to include a stress in a channel region of an active semiconductor region of an SOI substrate. A gate is formed to overlie the active semiconductor region, after which a sacrificial stressed layer is formed which overlies the gate and the active semiconductor region. Then, the SOI substrate is heated to cause a flowable dielectric material in a buried dielectric layer of the SOI substrate to soften and reflow. As a result of the reflowing, the sacrificial stressed layer induces stress in a channel region of the active semiconductor region underlying the gate. A source region and a drain region are formed in the active semiconductor region, desirably after removing the sacrificial stressed layer.

Abstract: A semiconductor device may include, but is not limited to, a single crystal silicon diffusion layer, a polycrystal silicon conductor, and a diffusion barrier layer. The diffusion barrier layer separates the polycrystal silicon conductor from the single crystal silicon diffusion layer. The diffusion barrier layer prevents a diffusion of at least one of silicon-interstitial and silicon-vacancy between the single crystal silicon diffusion layer and the polycrystal silicon conductor.

Abstract: A MOSFET device includes a semiconductor substrate having an active region including storage node contact forming areas and a device isolation region and having a device isolation structure which is formed in the device isolation region to delimit the active region; screening layers formed in portions of the device isolation structure on both sides of the storage node contact forming areas of the active region; a gate line including a main gate which is located in the active region and a passing gate which is located on the device isolation structure; and junction areas formed in a surface of the active region on both sides of the main gate.

Abstract: A semiconductor structure. The semiconductor structure includes (a) a semiconductor layer, (b) a gate dielectric region, and (c) a gate electrode region. The gate electrode region is electrically insulated from the semiconductor layer. The semiconductor layer comprises a channel region, a first and a second source/drain regions. The channel region is disposed between the first and second source/drain regions and directly beneath and electrically insulated from the gate electrode region. The semiconductor structure further includes (d) a first and a second electrically conducting regions, and (e) a first and a second contact regions. The first electrically conducting region and the first source/drain region are in direct physical contact with each other at a first and a second common surfaces. The first and second common surfaces are not coplanar. The first contact region overlaps both the first and second common surfaces.

Abstract: NFET and PFET devices with separately stressed channel regions, and methods of their fabrication is disclosed. A FET is disclosed which includes a gate, which gate includes a metal in a first state of stress. The FET also includes a channel region hosted in a single crystal Si based material, which channel region is overlaid by the gate and is in a second state of stress. The second state of stress of the channel region is of an opposite sign than the first state of stress of the metal included in the gate. The NFET channel is usually in a tensile state of stress, while the PFET channel is usually in a compressive state of stress. The methods of fabrication include the deposition of metal layers by physical vapor deposition (PVD), in such manner that the layers are in stressed states.

Abstract: A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate 11 and having a connection terminal 14a connected to the flat type external connection terminal 12a, a molding resin 15 for coating the semiconductor device 14 on the second surface of the wiring substrate 11, a card type supporting frame 10a having a concave portion or a hole portion fitting the wiring substrate 11, the semiconductor device 14, and the molding resin 15 in such a manner that the flat type external connection terminal 12a is exposed to the first surface of the wiring substrate 11, and adhesive resin a adhering integrally the flat type external connection terminal 12a, the wiring substrate 11, the semiconductor device 14, the molding resin 15, and the card type supporting frame 10a.

Abstract: A semiconductor device includes a semiconductor substrate, and a MOS transistor provided on the semiconductor substrate and having a channel type of a first conductivity, the MOS transistor comprising a semiconductor region of the first conductivity type including first and second channel regions, gate insulating films provided on the first and second channel regions, a gate electrode provided on the gate insulating films, and first and second source/drain regions which are located at a distance from each other so as to sandwich the first and second channel regions, the first and second source/drain regions contacting the semiconductor region of the first conductivity type and forming a Schottky junction.

Abstract: A method is described for manufacturing an n-MOS semiconductor transistor. Recesses are formed in a semiconductor substrate adjacent a gate electrode structure. Silicon is embedded in the recesses via a selective epitaxial growth process. The epitaxial silicon is in-situ alloyed with substitutional carbon and in-situ doped with phosphorus. The silicon-carbon alloy generates a uniaxial tensile strain in the channel region between the source and drain, thereby increasing electron channel mobility and the transistor's drive current. The silicon-carbon alloy decreases external resistances by reducing contact resistance between source/drain and silicide regions and by reducing phosphorous diffusivity, thereby permitting closer placement of the transistor's source/drain and channel regions.

Abstract: Example embodiments relate to a method of manufacturing a germanosilicide and a semiconductor device having the germanosilicide. A method according to example embodiments may include providing a substrate having at least a portion formed of silicon germanium. A metal layer may be formed on the silicon germanium. A thermal process may be performed on the substrate at a relatively high pressure to form the germanosilicide.

Abstract: A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.

Abstract: A semiconductor device including a semiconductor substrate having source/drain regions, a gate electrode formed on and/or over the semiconductor substrate, spacers formed against sidewalls of the gate electrode, an interlayer insulating layer formed over the semiconductor substrate and the gate electrode and having a plurality of contact holes formed therein, and contact plugs formed within the contact holes. The contact plugs can include a first contact plug and a second contact plug electrically connected to the gate electrode, and a third contact plug and a fourth contact plug electrically connected to the source/drain regions.

Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.

Abstract: A semiconductor device having nickel silicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer is formed on the semiconductor substrate, and a first rapid thermal process (RTP) is performed to react the nickel layer with the doped regions disposed thereunder. Thereafter, the unreacted nickel layer is removed, and a second rapid thermal process is performed to form a semiconductor device having nickel silicide. The second rapid thermal process is a spike anneal process whose process temperature is between 400 and 600° C.

Abstract: A semiconductor structure and a method for forming the same. The semiconductor structure includes (a) a semiconductor layer, (b) a gate dielectric region, and (c) a gate electrode region. The gate electrode region is electrically insulated from the semiconductor layer. The semiconductor layer comprises a channel region, a first and a second source/drain regions. The channel region is disposed between the first and second source/drain regions and directly beneath and electrically insulated from the gate electrode region. The semiconductor structure further includes (d) a first and a second electrically conducting regions, and (e) a first and a second contact regions. The first electrically conducting region and the first source/drain region are in direct physical contact with each other at a first and a second common surfaces. The first and second common surfaces are not coplanar. The first contact region overlaps both the first and second common surfaces.

Abstract: A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method making is described. The multilayered doped conductor creates a high dopant concentration in the active area close to the channel region. The rich dopant layer created by the multilayered doped conductor is less susceptible to depletion from trapped charges in the oxide. This improves device reliability at burn-in and lowers junction leakage, thereby providing a longer period between refresh cycles.

Abstract: An integrated semiconductor device includes at least one transistor. A first and a second source/drain diffusion region are arranged in a doped well. A contact structure is arranged on or above the substrate surface and abuts the lateral sidewall of a gate electrode isolation and electrically contacts the first source/drain diffusion region. The first source/drain diffusion region includes a highly doped main dopant region and a further dopant region, both formed of dopants of the same dopant type and spatially overlapping one another. The further dopant region extends deeper into the substrate below the substrate surface than the main dopant region.

Abstract: A thin film transistor including a substrate, a first buffer layer, a gate, a gate insulation layer, a channel layer, a source and a drain is provided. The first buffer layer is disposed on the substrate and the first buffer is a silicide. The gate covers a portion of the first buffer layer, and the gate includes a first aluminum metal layer and a first protective layer disposed thereon. The gate insulation layer covers the gate, and the channel layer is disposed on part of the gate insulation layer. The source and the drain are disposed on the channel layer and separated form each other. Each of the source and the drain includes a second buffer layer, a second aluminum metal layer and a second protective layer. The second aluminum metal layer is disposed on the second buffer layer and the second protective layer is disposed thereon.

Abstract: A stressed liner for improving carrier mobility in a transistor and a method for fabricating the same is disclosed. The stressed liner includes an intrinsically stressed conductive film encapsulated between two insulating layers such as silicon nitride, silicon oxide, or oxynitride. The stressed liner may be compressively-stressed or tensile-stressed depending on whether an n-FET or p-FET is required.

Abstract: A system or apparatus including an N-type transistor structure including a gate electrode formed on a substrate and source and drain regions formed in the substrate; a contact to the source region; and a pinning layer disposed between the source region and the first contact and defining an interface between the pinning layer and the source region, wherein the pinning layer has donor-type surface states in a conduction band. A method including forming a transistor structure including a gate electrode on a substrate and source and drain regions formed in the substrate; depositing a pinning layer having donor-type surface states on the source and drain regions such that an interface is defined between the pinning layer and the respective one of the source and drain regions; and forming a first contact to the source region and a second contact to the drain region.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.

Abstract: The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.

Abstract: An MOS device includes a gate stack overlying a semiconductor substrate and a graded source/drain region adjacent to the gate stack. The graded source/drain region includes a first grade having a first depth, a second grade spaced further apart from a channel region than the first grade, and a third grade spaced further apart from the channel region than the second grade. The depth of the second grade is between the respective depths of the first and the third grades. The MOS device further includes a silicide region on a top surface of the source/drain region wherein the silicide region has an inner edge substantially aligned with an inner edge of the third grade, and a graded gate spacer comprising an inner portion on a sidewall of the gate stack and an outer portion on a sidewall of the inner portion.

Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.

Abstract: A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.

Abstract: Wirings including first conductive layer patterns and insulating mask layer patterns are formed on a substrate. Insulating spacers are formed on sidewalls of the wirings. Self-aligned contact pads including portions of a second conductive layer are formed to contact with surfaces of the insulating spacers and to fill up a gap between the wirings. An interlayer dielectric layer is formed on the substrate where the contact pads are formed and is then partially etched to form contact holes exposing the contact pads. A selective epitaxial silicon layer is formed on the contact pads exposed through the contact holes to cover the insulating mask layer patterns. Thus, a short-circuit between the lower wiring and an upper wiring formed in the contact holes is prevented.

Abstract: According to example embodiments of the present invention, there are provided an electrical node of a transistor and a method of forming the same, which may reduce or minimize current leakage between the electrical node and a semiconductor substrate when a buried contact hole exposing at least the side of an active region is arranged on the semiconductor substrate. Two gate patterns may be formed on the active region of the semiconductor substrate. Conductive layer patterns may be formed in the gate patterns and in the semiconductor substrate between the gate patterns. A buried interlayer insulating layer may be formed on the semiconductor substrate to cover the gate patterns. A buried contact hole which passes through the buried interlayer insulating layer and exposes the conductive layer pattern of the semiconductor substrate may be formed. The buried contact hole may be formed to expose at least the side of the active region.

Abstract: Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.

Abstract: A semiconductor device includes a substrate having first and second device regions separated from each other by a device isolation region, a first field effect transistor having a first polysilicon gate electrode and formed in the first device region, a second field effect transistor having a second polysilicon gate electrode and formed in the second device region, a polysilicon pattern extending over the device isolation region from the first polysilicon gate electrode to the second polysilicon gate electrode, and a silicide layer formed on a surface of the first polysilicon gate electrode, a surface of said the polysilicon gate electrode and a surface of the polysilicon pattern so as to extend on the polysilicon pattern from the first polysilicon gate electrode to the second polysilicon gate electrode, the silicide layer having a region of increased film thickness on the polysilicon pattern, wherein the silicide layer has a surface protruding upward in the region of increased film thickness.

Abstract: A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a plurality of PECVD dielectric sublayers and plasma-treating each sublayer. Compressive stress from the dielectric capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in the PMOS channel. To form a compressive dielectric layer, a deposition reactant mixture containing A1 atoms and A2 atoms is provided in a vacuum chamber. Element A2 is more electronegative than element A1, and A1 atoms have a positive oxidation state and A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms. A deposition plasma is generated by applying HF and LF radio-frequency power to the deposition reactant mixture, and a sublayer of compressive dielectric material is deposited.

Abstract: To an output of an NMOS having one end connected to a power source, a capacitor and a PMOS are connected. A capacitor is connected to the output of the PMOS. The NMOS and the PMOS are turned on alternately. A pulse is applied to other end of the capacitor which is connected to the output of the NMOS, to shift the output of the NMOS for boosting. Then, a back gate of the NMOS is connected, via a PMOS in an on state, to the power source. With this structure, the PMOS provides a resistor component when the output terminal short-circuits.

Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.

Abstract: A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.

Abstract: A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical contact with first and second S/D regions, respective. First and second silicide regions are formed such that the first silicide region is in direct physical contact with the first S/D region and the first S/D extension region, whereas the second silicide region is in direct physical contact with the second S/D region and the second S/D extension region. The first silicide region is thinner for regions in contact with first S/D extension region than for regions in contact with the first S/D region. Similarly, the second silicide region is thinner for regions in contact with second S/D extension region than for regions in contact with the second S/D region.

Abstract: Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misleading a reverse engineer. A method for fabricating such devices.

Abstract: Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate; forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region; implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region; forming a first interlayer insulating film; and patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions. The method further comprises forming a first ohmic film, a first barrier film, and a metal film; and removing portions of each of the metal film, the first barrier film, and the first ohmic film.