Including Silicide Patents (Class 257/384)
  • Patent number: 10797133
    Abstract: A method for depositing a phosphorus doped silicon arsenide film is disclosed. The method may include, providing a substrate within a reaction chamber, heating the substrate to a deposition temperature, exposing the substrate to a silicon precursor, an arsenic precursor, and a phosphorus dopant precursor, and depositing the phosphorus doped silicon arsenide film over a surface of the substrate. Semiconductor device structures including a phosphorus doped silicon arsenide film deposited by the methods of the disclosure are also provided.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: October 6, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Chi-Wei Lo, Alexandros Demos, Raj Kumar
  • Patent number: 10755935
    Abstract: A semiconductor device and fabrication method are provided. The method includes providing a first dielectric layer with a first groove on a base substrate. A first gate electrode is formed in the first groove, with a top surface lower than the first dielectric layer. A first protective layer is formed on a portion of the top surface of the first gate electrode, with a first oxygen ionic concentration. A compensating protective layer is formed on a remaining portion of the top surface of the first gate electrode exposed by the first protective layer, with a second oxygen ionic concentration. A second dielectric layer is formed on the first protective layer, on the compensating protective layer, and on the first dielectric layer, with a third oxygen ionic concentration. The first oxygen ionic concentration and second oxygen ionic concentration are smaller than the third oxygen ionic concentration.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: August 25, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10714579
    Abstract: A gate all around field effect transistor (GAAFET) device may include a plurality of nanostructures that are spaced apart from one another in a channel region of the FET device above a substrate. A gate electrode can be in a GAA arrangement with the plurality of nanostructures and a semiconductor pattern can be on one side of the gate electrode. A contact in a contact trench in the semiconductor pattern and a silicide film can extend conformally on a side wall of the contact trench to a level in the channel region that is lower an uppermost one of the plurality of nanostructures.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: July 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Heon Bok Lee, Chul Sung Kim, Sang Jin Hyun
  • Patent number: 10636697
    Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Wang-Jung Hsueh, Kuo-Yi Chao, Mei-Yun Wang
  • Patent number: 10636870
    Abstract: The present disclosure describes a fabrication method that prevents divots during the formation of isolation regions in integrated circuit fabrication. In some embodiments, the method of forming the isolation regions includes depositing a protective layer over a semiconductor layer; patterning the protective layer to expose areas of the semiconductor layer; depositing an oxide on the exposed areas the semiconductor layer and between portions of the patterned protective layer; etching a portion of the patterned protective layer to expose the semiconductor layer; etching the exposed semiconductor layer to form isolation openings in the semiconductor layer; and filling the isolation openings with a dielectric to form the isolation regions.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Hsin-Chi Chen, Kun-Tsang Chuang
  • Patent number: 10600899
    Abstract: Provided is a low cost semiconductor device in which occurrence of chipping and a crack during dicing is suppressed. A nitride layer (silicon nitride layer) 23 is formed on an oxide layer 22. In FIG. 1, a thick organic layer 24 is formed as a top layer. The semiconductor device 1 is characterized by its structure on a side of its end portion. In FIG. 1, the end portion E of the semiconductor device 1 is formed by cutting with a blade in the vertical direction during dicing. An edge E1 of both the oxide layer 22 and the nitride layer is located apart from an edge of a semiconductor substrate 10. An edge E2 of the organic layer 24 on the nitride layer 23 is located inside the edge E1 of the nitride layer 23 (on a side more distant from the edge E).
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 24, 2020
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Hironori Aoki
  • Patent number: 10559422
    Abstract: A method for fabricating an electronic device including a semiconductor memory includes: forming a variable resistance element over a substrate, the variable resistance element including a metal-containing layer and an MTJ (Magnetic Tunnel Junction) structure which is located over the metal-containing layer and includes a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; forming an initial spacer containing a metal over the variable resistance element; performing an oxidation process to transform the initial spacer into a middle spacer including an insulating metal oxide; and performing a treatment using a gas or plasma including nitrogen and hydrogen to transform the middle spacer produced by the oxidation process into a final spacer including an insulating metal nitride or an insulating metal oxynitride.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventors: Ga-Young Ha, Ki-Seon Park, Jong-Han Shin, Jeong-Myeong Kim, Bo-Kyung Jung
  • Patent number: 10535655
    Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ali Keshavarzi, Ta-Pen Guo, Shu-Hui Sung, Hsiang-Jen Tseng, Shyue-Shyh Lin, Lee-Chung Lu, Chung-Cheng Wu, Li-Chun Tien, Jung-Chan Yang, Ting-Yu Chen, Min Cao, Yung-Chin Hou
  • Patent number: 10505041
    Abstract: A semiconductor device includes: a substrate; a gate structure on the substrate; and an epitaxial layer in the substrate adjacent to the gate structure, in which the epitaxial layer includes a planar surface and protrusions adjacent to two sides of the planar surface. Preferably, a contact plug is embedded in part of the epitaxial layer, and a silicide is disposed under the contact plug, in which a bottom surface of the silicide includes an arc.
    Type: Grant
    Filed: March 26, 2017
    Date of Patent: December 10, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Wei Yu, Hsu Ting, Chueh-Yang Liu, Yu-Ren Wang, Kuang-Hsiu Chen
  • Patent number: 10483385
    Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael G. Haverty, Sadasivan Shankar
  • Patent number: 10483164
    Abstract: A method for manufacturing a semiconductor includes following steps. An epitaxial structure including a first semiconductor material and a second semiconductor material is provided. A lattice constant of the second semiconductor material is greater than a lattice constant of the first semiconductor material. A metal-containing layer is deposited on the epitaxial structure. The metal containing layer includes a first metal material and a second metal material. An atomic size of the second metal material is greater than an atomic size of the first metal material. The metal-containing layer and the epitaxial structure are annealed to form a metal silicide layer on the epitaxial structure. The metal silicide layer includes the first semiconductor material, the second semiconductor material, the first metal material, and the second metal material.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yan-Ming Tsai, Wei-Yip Loh, Yu-Ming Huang, Hung-Hsu Chen, Chih-Wei Chang
  • Patent number: 10475790
    Abstract: The present disclosure describes an exemplary asymmetric CPP layout for a semiconductor structure with a different gate pitch over the source and the drain regions to mitigate gate-to-gate parasitic capacitances over the drain region, thus improving cutoff frequency. For example, the semiconductor structure can include a fin on a substrate. The semiconductor structure can also include first and second gate structures formed on the fin and separated by a first space. The semiconductor structure can also include a third gate structure formed on the fin between the first and the second gate structures. The third gate structure can be separated from the first gate structure by a second pitch and separated from the second gate structure by a third pitch that is greater than the second pitch. The semiconductor structure further includes a source region formed between the first and third gate structures, and a drain region formed between the third and the second gate structures.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Barn Chen, Chi-Cherng Jeng, Shiu-Ko Jangjian, Ting-Huang Kuo
  • Patent number: 10460995
    Abstract: A semiconductor device and method of manufacture are provided in which an the physical characteristics of a dielectric material are modified in order to provide additional benefits to surrounding structures during further processing. The modification may be performed by implanting ions into the dielectric material to form a modified region. Once the ions have been implanted, further processing relies upon the modified structure of the modified region instead of the original structure.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Li-Te Hsu
  • Patent number: 10453921
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate; forming a gate structure on a top surface of the base substrate; and forming a first doped source/drain layer at both sides of the gate structure. A minimum distance between a sidewall surface of the first doped source/drain doping layer and an adjacent sidewall surface of the gate structure is a first distance. The method also includes forming a second doped source/drain layer on the first doped source/drain layer at both sides of the gate structure. A minimum distance between a sidewall surface of the second doped source/drain doping layer and an adjacent sidewall surface of the gate structure is a second distance; and the second distance is greater than the first distance.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: October 22, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Poren Tang
  • Patent number: 10366982
    Abstract: The present disclosure provides a method of fabricating an integrated circuit in accordance with some embodiments. The method includes forming a source and a drain on a fin active region of a semiconductor substrate; depositing an interlayer dielectric (ILD) layer on the source and drain; patterning the ILD layer to form a first contact hole and a second contact hole aligning with the source and drain, respectively; forming a dielectric material layer in the first contact hole; and forming a first conductive feature and a second conductive feature in the first and second contact holes, respectively.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fan-Shuen Meng, Huang-Kui Chen, Min-Yann Hsieh
  • Patent number: 10340381
    Abstract: The present invention provides a method for fabricating a semiconductor structure, the method at least comprises: firstly, a substrate is provided, a dielectric layer is formed on the substrate, a gate conductive layer and two spacers are formed and disposed in the dielectric layer, wherein the two spacers are respectively disposed on both sides of the gate conductive layer, next, parts of the gate conductive layer are removed, and parts of the two spacers are removed, wherein a top surface of the two spacers is lower than a top surface of the gate conductive layer, and afterwards, a stress cap layer is then formed, overlying the gate conductive layer and the two spacers, wherein parts of the stress cap layer is located right above the two spacers.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: July 2, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10332842
    Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kiseok Lee, Sooho Shin, Juik Lee, Jun Ho Lee, Kwangmin Kim, Ilyoung Moon, Jemin Park, Bumseok Seo, Chan-Sic Yoon, Hoin Lee
  • Patent number: 10325999
    Abstract: A method for manufacturing a semiconductor device comprises forming a silicide region on a semiconductor substrate, forming a gate structure on the semiconductor substrate adjacent the silicide region, forming a dielectric layer on the gate structure and on the silicide region, forming a first liner layer on the dielectric layer, removing a portion of the first liner layer and a portion of the dielectric layer to form an opening exposing a top surface of the silicide region, forming a second liner layer on the first liner layer and on sides and a bottom of the opening, removing a portion of the second liner layer from a top surface of the first liner layer and from the bottom of the opening to re-expose a portion of the top surface of the silicide region, and forming a contact layer in the opening directly on the re-exposed portion of the top surface of the silicide region.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10325922
    Abstract: A semiconductor device includes a substrate, a stacked structure of insulating layers and gate electrodes alternately and repeatedly stacked on the substrate, and a pillar passing through the stacked-layer structure. The insulating layers include lower insulating layers, intermediate insulating layers disposed on the lower insulating layers, and upper insulating layers disposed on the intermediate insulating layers. The lower insulating layers have a hardness less than that of the intermediate insulating layers, and the upper insulating layers have a hardness greater than that of the intermediate insulating layers.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: June 18, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong Dae Lim, Seung Jae Jung, Jin Young Bang, Il Woo Kim, Ho Gil Jung
  • Patent number: 10304930
    Abstract: In forming an n+-type source region in a surface region of a p-type base layer by ion implantation, ion implantation of arsenic and ion implantation of nitrogen are sequentially performed. The ion implantation of nitrogen is performed by acceleration energy higher than that of the ion implantation of arsenic. The n+-type source region has an arsenic concentration profile and a nitrogen concentration profile formed to overlap each other at a different depth from the front surface of the base substrate. A peak of the nitrogen concentration profile is positioned deeper than a peak of the arsenic concentration profile from the front surface of the base substrate. The overall impurity concentration distribution of the n+-type source region is a concentration profile that is formed by summing the arsenic concentration profile and the nitrogen concentration profile with each other and whose diffusion depth is large.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: May 28, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Ohse, Makoto Utsumi, Yasuhiko Oonishi
  • Patent number: 10294101
    Abstract: A semiconductor arrangement includes a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement includes a second semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The second semiconductor column is separated a first distance from the first semiconductor column along a first axis. The semiconductor arrangement includes a third semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The third semiconductor column is separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis. The second distance is different than the first distance.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Jean-Pierre Colinge, Ta-Pen Guo, Chih-Hao Wang, Carlos H. Diaz
  • Patent number: 10297499
    Abstract: Techniques and methods related to forming a wrap-around contact on a semiconductor device, and apparatus, system, and mobile platform incorporating such semiconductor devices.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Jeffrey S. Leib, Ralph T. Troeger, Daniel Bergstrom
  • Patent number: 10283360
    Abstract: Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, forming a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: May 7, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan Sic Yoon, Ki Seok Lee, Dong Oh Kim, Yong Jae Kim
  • Patent number: 10276678
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chun-Han Tsao, Chih-Ming Chen, Han-Yu Chen, Szu-Yu Wang, Lan-Lin Chao, Cheng-Yuan Tsai
  • Patent number: 10177005
    Abstract: In a method for manufacturing a semiconductor device, a dummy gate layer and a hard mask layer are sequentially formed on a substrate. A first doped portion is formed in the dummy gate layer, and has an etching selectivity with respect to the other portion of the dummy gate layer. Etching masks are formed on portions of the hard mask layer. The hard mask layer and the dummy gate layer are etched to pattern the first doped portion and the other portion of the dummy gate layer into first dummy gates and second dummy gates. The first dummy gates and the second dummy gates have different widths. A dielectric layer is formed to peripherally enclose each of the first dummy gates and each of the second dummy gates. The first dummy gates and the second dummy gates are replaced with first metal gates and second metal gates.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10170427
    Abstract: A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of depositing a first insulating material over a substrate, and forming a first conductive contact in the first insulating material. The first conductive contact has a protruding uppermost surface, with a first height along a central portion of the first conductive contact, and a second height along a vertical vector projection of a sidewall of the first conductive contact. The first height is larger than the second height. A second insulating material is deposited over the first insulating material, and a second conductive contact is formed in the second insulating material. The second conductive contact is disposed over and at least partially within the first conductive contact. A distance between a bottommost surface of the second conductive contact and the protruding uppermost surface of the first conductive contact is less than about 1.0 nm.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10153369
    Abstract: The present invention provides a semiconductor structure, the semiconductor structure comprises a substrate having a dielectric layer disposed thereon, a gate conductive layer disposed on the substrate and disposed in the dielectric layer, two spacers, disposed on two sides of the gate conductive layer respectively, wherein a top surface of the two spacers is lower than a top surface of the gate conductive layer, and a cap layer overlying the top surface and two sidewalls of the gate conductive layer, wherein parts of the cap layer are located right above the two spacers.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10153353
    Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Rung-Yuan Lee, Chih-Wei Yang
  • Patent number: 10134860
    Abstract: A semiconductor device includes a first dielectric layer on a substrate, the first dielectric layer including a first dielectric portion over a first doped well region of a first conductivity type and a second dielectric portion over a second doped well region of a second conductivity type, and a second dielectric layer on the substrate directly adjacent the first dielectric layer. The second dielectric layer is over the second doped well region. A first conductive gate structure is over the first and second dielectric layers. A third dielectric layer is on the substrate over the second doped well region and separated a first distance from the second dielectric layer. A second conductive gate structure is over the third dielectric layer. A third doped region of the second conductivity type is implanted in the second doped well region a second distance from the third dielectric layer and the second conductive gate structure.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: November 20, 2018
    Assignee: NXP B.V.
    Inventors: Jan Sonsky, Viet Thanh Dinh, Jan Claes
  • Patent number: 10121702
    Abstract: At least one method, apparatus and system disclosed herein involves performing an early-process of source/drain (S/D) contact cut and S/D contact etch steps for manufacturing a finFET device. A gate structure, a source structure, and a drain structure of a transistor are formed. The gate structure comprises a dummy gate region, a gate spacer, and a liner. A source/drain (S/D) contact cut process is performed. An S/D contact etch process is performed. A replacement metal gate (RMG) process is performed subsequent to performing the S/D contact etch process. An S/D contact metallization process is performed.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Min Gyu Sung, Ruilong Xie, Puneet H. Suvarna
  • Patent number: 10121966
    Abstract: A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals onto a substrate, and exposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate. Additional methods are also described, as are semiconductor device structures including the silicon-containing dielectric material and methods of forming the semiconductor device structures.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Thomas R. Omstead, Cole S. Franklin
  • Patent number: 10108771
    Abstract: At least one method, apparatus and system disclosed herein for forming a semiconductor device comprising a plurality of cells having metal features formed using triple patterning processes. An overall pattern layout is created for a first cell that is to be manufactured using a triple patterning process for forming a plurality of metal features on a metal layer. A first color metal feature is formed in the metal layer. The first color metal feature is associated with a first patterning process of the triple patterning process. A second color metal feature is formed in the metal layer. The second color metal feature is associated with a second patterning process of the triple patterning process. A third color metal feature is formed in the metal layer. The third color metal feature is associated with a third patterning process of the triple patterning process. At least one of the first, second, and third color metal features is re-colorable.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Juhan Kim, Mahbub Rashed
  • Patent number: 10090197
    Abstract: An interconnect structure including a semiconductor structure on a semiconductor substrate, the semiconductor structure having a gate structure, shallow trench isolation and a source and a drain; a trench adjacent to the gate structure; a metal line adjacent to the gate structure and filling the trench, the metal line contacts one of the source and the drain; a gap in the metal line so as to create segments of the metal line; and a dielectric material filling the gap such that ends of the metal line abut the dielectric material wherein the ends of the metal line have a flat surface.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: October 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Wilfried E.-A. Haensch
  • Patent number: 10008456
    Abstract: Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. First and second spacers are formed adjacent to a surface of a device component from respective conformal layers. The first spacer is positioned between the surface of the device component and the second spacer. The second spacer includes a plurality of first lamina and a plurality of second lamina that are arranged in an alternating sequence with the first lamina. The first spacer has a first dielectric constant, and the second spacer has a second dielectric constant that is greater than the first dielectric constant.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: June 26, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tao Han, Man Gu, Jinping Liu
  • Patent number: 9966454
    Abstract: A method for manufacturing a semiconductor device comprises forming a silicide region on a semiconductor substrate, forming a gate structure on the semiconductor substrate adjacent the silicide region, forming a dielectric layer on the gate structure and on the silicide region, forming a first liner layer on the dielectric layer, removing a portion of the first liner layer and a portion of the dielectric layer to form an opening exposing a top surface of the silicide region, forming a second liner layer on the first liner layer and on sides and a bottom of the opening, removing a portion of the second liner layer from a top surface of the first liner layer and from the bottom of the opening to re-expose a portion of the top surface of the silicide region, and forming a contact layer in the opening directly on the re-exposed portion of the top surface of the silicide region.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: May 8, 2018
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 9916979
    Abstract: Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, forming a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: March 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan Sic Yoon, Ki Seok Lee, Dong Oh Kim, Yong Jae Kim
  • Patent number: 9899257
    Abstract: A method of forming a shallow trench isolation (STI) in a semiconductor-on-insulator (SOI) substrate, including an etch stop liner, to mitigate punch through in SOI substrates is disclosed. The method may include providing an SOI substrate, forming an STI recess within the SOI substrate, forming a first STI dielectric fill within the STI recess wherein a top surface of the first STI dielectric fill is at a location above a top surface of the base substrate, forming a first etch stop liner on the first STI dielectric fill, and forming a second STI dielectric fill over the first etch stop liner. The first etch stop liner is configured so that portion of a contact opening later formed is positioned over the first etch stop liner such that the etch stop liner prevents punch through into the STI. The method may also include forming a second etch stop liner after forming the STI recess and before forming the first STI dielectric fill.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: February 20, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jin Z. Wallner, Haoren Zhuang
  • Patent number: 9893064
    Abstract: An integrated circuit device includes a substrate, first and second fin-type active areas which extend in a first direction on the substrate, first and second gate lines on the substrate that extend in a second direction that crosses the first direction, and first and second contact structures. The first and second gate lines intersect the first and second fin-type active areas, respectively. The first contact structure is on the first fin-type active area at a side of the first gate line and contacts the first gate line. The second contact structure is on the second fin-type active area at a side of the second gate line. The first contact structure includes a first lower contact including metal silicide and a first upper contact on the first lower contact. The second contact structure includes a second lower contact including metal silicide and a second upper contact on the second lower contact.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: February 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jae-yup Chung
  • Patent number: 9887133
    Abstract: Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts. First gate contacts and terminal contacts are recessed to form a metal layer on top. Second gate contacts are recessed to be separately on each of the second gates. Filling material is formed on top of the recessed second gate contacts and metal layer. An upper layer is on top of the filling material. First metal vias are formed through filling and upper layers down to metal layer over first gate contacts. Second metal vias are formed through filling and upper layers down to metal layer over terminal contacts. Third metal vias are formed through filling and upper layers down to recessed second gate contacts over second gates. Third metal vias are taller than first.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: February 6, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Cheng Chi, Ruilong Xie
  • Patent number: 9837351
    Abstract: Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer. The gate contact is formed on top of the gate. A second layer is formed on the cap layer. The second layer and cap layer are recessed to remove a portion of the cap layer from a top part and upper sidewall parts of the gate contact. A third layer is formed on the second layer, cap layer, and gate contact. The third layer is etched through to form a gate trench over the gate contact to be around the upper sidewall parts of the gate contact. The gate trench is an opening that stops on the cap layer. Gate metal via is formed on top of the gate contact and around upper sidewall parts of the gate contact.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: December 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Victor W. C. Chan, Xuefeng Liu, Yann A. M. Mignot, Yongan Xu
  • Patent number: 9837302
    Abstract: A method includes performing an etching process from a second side of a buried dielectric layer to expose an etch stop layer, where the second side of the buried dielectric layer is opposite a first side of the buried dielectric layer, and where a first semiconductor device is positioned on the first side of the buried dielectric layer. The method further includes forming a second semiconductor device on the second side of the buried dielectric layer.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: December 5, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Stephen Alan Fanelli
  • Patent number: 9831271
    Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: November 28, 2017
    Assignee: SOCIONEXT INC.
    Inventor: Masaki Tamaru
  • Patent number: 9831123
    Abstract: One method disclosed herein includes performing a plurality of conformal deposition processes to form first, second and third layers of material within a contact opening, wherein the first layer comprises a contact insulating material, the second layer comprises a metal-containing material and the third layer comprises a conductive cap material, wherein the third layer is positioned above the second layer. The method further includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, forming a conductive material above the third layer and removing portions of the layers of material positioned outside of the contact opening.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: November 28, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Suraj K. Patil, Zhiguo Sun, Keith Tabakman
  • Patent number: 9786557
    Abstract: Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts. First gate contacts and terminal contacts are recessed to form a metal layer on top. Second gate contacts are recessed to be separately on each of the second gates. Filling material is formed on top of the recessed second gate contacts and metal layer. An upper layer is on top of the filling material. First metal vias are formed through filling and upper layers down to metal layer over first gate contacts. Second metal vias are formed through filling and upper layers down to metal layer over terminal contacts. Third metal vias are formed through filling and upper layers down to recessed second gate contacts over second gates. Third metal vias are taller than first.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: October 10, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Cheng Chi, Ruilong Xie
  • Patent number: 9766519
    Abstract: An array substrate is disclosed. The array substrate includes a substrate, a first film layer on a side surface of the substrate, an insulation layer on the side surface of the substrate, an electrostatic charge dispersion layer on the side surface of the substrate, and a second film layer arranged on the side surface of the substrate. The first film layer, the insulation layer, the electrostatic charge dispersion layer, and the second film layer are sequentially arranged on the substrate. In addition, the insulation layer and the electrostatic charge dispersion layer include via holes, the second film layer is electrically connected with the first film layer through the via holes, and the electrostatic charge dispersion layer is in a same profile as the second film layer.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: September 19, 2017
    Assignees: XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventor: Liang Wen
  • Patent number: 9761496
    Abstract: A method comprises forming a first gate of a first field effect transistor (FET) device over a first channel region of a first fin arranged on a substrate, forming a second gate of a second FET device over a second channel region of a second fin arranged on the substrate, the second channel region having a width that is greater than a width of the first channel region, etching to remove portions of the insulator material and define a first cavity that exposes an active region of the first FET device and a second cavity that exposes an active region of the second FET device, and depositing a conductive material in the first cavity to define a first contact and depositing a conductive material in the second cavity to define a second contact, the second contact having a width that is greater than a width of the first contact.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: September 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 9660075
    Abstract: Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures having source/drain regions in PFET areas and in NFET areas. The method includes selectively forming a contact resistance modulation material on the source/drain regions in the PFET areas. Further, the method includes depositing a band-edge workfunction metal overlying the source/drain regions in the PFET areas and in the NFET areas.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 23, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Shao Ming Koh, Guillaume Bouche, Jeremy A. Wahl, Andy C. Wei
  • Patent number: 9607840
    Abstract: A method for forming spacers of a gate of a transistor is provided, including forming a protective layer covering the gate; after the forming the protective layer, at least one step of forming a carbon film on the transistor; removing portions of the carbon film located on a top and on either side of the gate; modifying the protective layer on the top of the gate and on either side of the gate; and removing the modified protective layer.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: March 28, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Nicolas Posseme
  • Patent number: 9536988
    Abstract: A method of making a semiconductor device includes forming a gate on a substrate; removing an end portion of the gate to form a recess at an end of the gate; depositing a low-k material in the recess such that an air gap is formed in the low-k material; removing a portion of the low-k material; depositing an insulating material on the low-k material that was recessed to form a bilayer insulating stack; and forming a source/drain contact on an active area positioned on the substrate and alongside the gate.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: January 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Balasubramanian Pranatharthiharan, Junli Wang
  • Patent number: 9530890
    Abstract: A method of making a semiconductor device includes forming a gate on a substrate; removing an end portion of the gate to form a recess at an end of the gate; depositing a low-k material in the recess such that an air gap is formed in the low-k material; removing a portion of the low-k material; depositing an insulating material on the low-k material that was recessed to form a bilayer insulating stack; and forming a source/drain contact on an active area positioned on the substrate and alongside the gate.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: December 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Balasubramanian Pranatharthiharan, Junli Wang