Abstract: A device includes a transistor, a backside via, and a pair of sidewall spacers. The transistor includes a gate structure, a channel layer surrounded by the gate structure, and a first source/drain structure and a second source/drain structure connected to the channel layer. The backside via is under and connected to the first source/drain structure and includes a first portion, a second portion between the first portion and the first source/drain structure, and a third portion tapering from the first portion to the second portion in a cross-sectional view. The pair of sidewall spacers are on opposite sidewalls of the second portion of the backside via but not on opposite sidewalls of the first portion of the backside via.

Abstract: The present invention disclosures an oxide semiconductor transistor and a method of fabricating the same. The oxide semiconductor transistor according to an embodiment of the present invention includes a first gate electrode formed on a substrate; a first gate insulating film formed using a solution process on the first gate electrode; a source electrode and a drain electrode separately formed on one surface of the first gate insulating film; an oxide semiconductor film formed using a solution process on the first gate insulating film and the source and drain electrodes; a second gate insulating film formed using a solution process on the oxide semiconductor film; pixel electrodes separately formed on one surface of the second gate insulating film and electrically connected to the source and drain electrodes, respectively; and a second gate electrode formed on the second gate insulating film.

Abstract: Display device is provided and includes scanning line; semiconductor layer; pixel electrode; first insulating film having first contact hole; organic insulating film having second contact hole; and second insulating film having third contact hole, wherein semiconductor layer has first linear portion that is orthogonal to scanning line, pixel electrode is electrically connected to first linear portion via first, second and third contact holes, first linear portion overlaps first, second and third contact holes that are aligned along first linear portion, and center of second contact hole is located between center of first contact hole and center of third contact hole.

Abstract: A transistor display panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate; and a pixel electrode connected to the first transistor, wherein the first transistor includes a lower electrode disposed on the substrate, a first semiconductor overlapping the lower electrode, a first insulating layer covering the first semiconductor, a first gate electrode disposed on the first insulating layer and overlapping the first semiconductor, and a first source connecting member and a first drain connecting member disposed on the same layer as the first gate electrode and connected to the first semiconductor, wherein the first gate electrode is formed as a triple layer, the first source connecting member and first drain connecting member are formed as a double layer, and the first source connecting member is connected to the lower electrode.

Abstract: A memory device is provided. The memory device includes a plurality of memory cells. Each memory cell includes a latch circuit formed of N-type field effect transistors (NFETs) and P-type field effect transistors (PFETs). The NFETs are formed at a surface of a semiconductor substrate, and the PFETs are disposed at an elevated level over the NFETs.

Abstract: Provided are a deposition mask, a method of manufacturing a display device using the deposition mask, and a display device. The deposition mask includes a main frame defining a first opening; ribs extending away from a side of the main frame, the ribs being apart from each other and defining second openings; and bridges connecting the ribs to one another across the second openings, wherein the bridges and the ribs form the same top surface, and a thickness of each of the bridges is less than a thickness of each of the ribs.

Abstract: A method for forming a multilayer conductive structure includes forming a first conductive portion; forming a second conductive portion containing ruthenium (Ru) therein on the first conductive portion; forming a third conductive portion on the second conductive portion; and performing a silicidation process on the second conductive portion.

Abstract: Gate-all-around (GAA) device and the manufacturing method thereof are disclosed herein. An exemplary integrated circuit (IC) device comprises a first nanostructure and a second nanostructure formed on a substrate, wherein each of the first nano structure and the second nanostructure includes a plurality of semiconductor layers and each of the first nanostructure and the second nanostructure includes a channel region and a source/drain (S/D) region; a first gate structure wrapping the plurality of semiconductor layers of the first nanostructure and a second gate structure wrapping the plurality of semiconductor layers of the second nanostructure; and a S/D contact that contacts at least one of the plurality of semiconductor layers of the first nanostructure and at least one of the plurality of semiconductor layers of the second nanostructure.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin structure; forming spacers on sides of the dummy gate; forming a doped region within the fin structure; replacing the dummy gate with a metal gate; replacing an upper portion of the metal gate with a first dielectric layer; forming a conductive layer directly on the doped region; replacing an upper portion of the conductive layer with a second dielectric layer; removing the first dielectric layer thereby exposing a sidewall of the spacer; removing an upper portion of the spacer to thereby expose a sidewall of the second dielectric layer; removing at least a portion of the second dielectric layer to form a trench; and forming a conductive plug in the trench.

Abstract: Field effect transistor and manufacturing method thereof are disclosed. The field effect transistor includes a substrate, fins, a gate structure, a first spacer and a second spacer. The fins protrude from the substrate and extend in a first direction. The gate structure is disposed across and over the fins and extends in a second direction perpendicular to the first direction. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed on the first spacer and surrounds the gate structure. The first spacer is fluorine-doped and includes fluorine dopants.

Abstract: A semiconductor structure is provided which includes a nanosheet stack structure on a base. The nanosheet stack structure includes a multilayered nanosheet between adjacent nanosheet layers. The multilayered nanosheet includes one or more first layers of a first material and one or more second layers of a second material, wherein the first material has an etch selectivity different than the second material. The one or more first layers of the multilayered nanosheet are recessed. A first inner spacer includes a third material is formed by depositing the third material into an outer portion of the one or more recessed first layers of the multilayered nanosheet. The one or more second layers of the multilayered nanosheet are recessed. A second inner spacer includes a fourth material which is formed by depositing the fourth material into an outer portion of the one or more recessed second layers of the first multilayered nanosheet.

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) device is provided. The device comprising: a substrate; an oxide layer on the substrate; a gate on the oxide layer; a source and a drain on the substrate, wherein the source and the drain are doped with a dopant of a first type; and a cold source coupled to the source, wherein the cold source comprises a junction between a semiconductor doped with a dopant of a second type, and a material selected from the group consisting of metal and semimetal.

Abstract: Thin film transistors are described. An integrated circuit structure includes a first source or drain contact above a substrate. A gate stack pedestal is on the first source or drain contact, the gate stack pedestal including a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer. A channel material layer is over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact. Dielectric spacers are adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal. A second source or drain contact is over a portion of the channel material layer over the gate stack pedestal.

Abstract: Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.

Abstract: Embodiments of the invention include semiconductor devices having a first n-type S/D region, a second n-type S/D region, and a first layer of protective material over the second n-type S/D region, wherein the first layer of protective material includes a first type of material and a second type of material. A second layer of protective material is formed over the first layer of protective material, wherein the second layer of protective material includes an oxide of the second type of material. The devices further include a first p-type S/D region, a second p-type S/D region, and the second layer of protective material over the second p-type S/D region, wherein the second p-type S/D region second layer of protective material includes the first type of material and the second type of material, and wherein the second layer of protective material includes the oxide of the second type of material.

Abstract: Semiconductor devices and fabrication methods thereof are provided. An exemplary semiconductor device includes a base substrate; a gate structure group, having a plurality of gate structures, formed over the base substrate; first source/drain doping regions formed in the base substrate between adjacent gate structures; second source/drain doping regions formed in the base substrate at two sides of the gate structure group, respectively; a first conductive layer formed on a surface of each of the first source/drain doping regions. The second source/drain doing regions at one side of the gate structure group are electrically connected with source voltages; and the second source/drain doping regions at other side of the gate structure group are electrically connected with drain voltages.

Abstract: The present invention disclosures an oxide semiconductor transistor and a method of fabricating the same. The oxide semiconductor transistor according to an embodiment of the present invention includes a first gate electrode formed on a substrate; a first gate insulating film formed using a solution process on the first gate electrode; a source electrode and a drain electrode separately formed on one surface of the first gate insulating film; an oxide semiconductor film formed using a solution process on the first gate insulating film and the source and drain electrodes; a second gate insulating film formed using a solution process on the oxide semiconductor film; pixel electrodes separately formed on one surface of the second gate insulating film and electrically connected to the source and drain electrodes, respectively; and a second gate electrode formed on the second gate insulating film.

Abstract: It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a gate stack positioned on the substrate, a plurality of programmable contacts positioned on the gate stack, a pair of heavily-doped regions positioned adjacent to two sides of the gate stack and in the substrate, and a plurality of first contacts positioned on the pair of heavily-doped regions. A width of the plurality of programmable contacts is less than a width of the plurality of first contacts.

Abstract: A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.

Abstract: A semiconductor structure and a method of forming the same are provided. In the semiconductor structure, contact spacers are formed at least on sidewalls of contact trenches in the substrate, so that the distance between the gate and the silicide layers disposed only on the bottom surfaces, rather than on the sidewalls and the bottom surfaces, of the contact trenches can be increased, and thus the current leakage induced by gate can be decreased.

Abstract: The back reflection in photodiodes is caused by an abrupt index contrast between the input waveguide and the composite waveguide/light absorbing material. In order to improve the back reflection, it is proposed to introduce an angle between the waveguide and the leading edge of the light absorbing material. The angle will result in gradually changing the effective index between the index of the waveguide and the index of the composite section, and consequently lower the amount of light reflecting back.

Abstract: A semiconductor device comprises: a substrate; a semiconductor layer formed on the substrate; a source electrode, a drain electrode and a gate electrode between the source electrode and the drain electrode formed on the semiconductor layer; and a source field plate formed on the semiconductor layer. The source field plate sequentially comprises: a start portion electrically connected to the source electrode; a first intermediate portion spaced apart from the semiconductor layer with air therebetween; a second intermediate portion disposed between the gate electrode and the drain electrode in a horizontal direction, without air between the second intermediate portion and the semiconductor layer; and an end portion spaced apart from the semiconductor layer with air therebetween.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A disposable gate contacts the at least one semiconductor fin. A spacer is disposed on the at least one semiconductor fin and in contact with the disposable gate. Epitaxially grown source and drain regions are disposed at least partially within the at least one semiconductor fin. A first one of silicide and germanide is disposed on and in contact with the source region. A second one of one of silicide and germanide is disposed on and in contact with the drain region. The method includes epitaxially growing source/drain regions within a semiconductor fin. A contact metal layer contacts the source/drain regions. One of a silicide and a germanide is formed on the source/drain regions from the contact metal layer prior to removing the disposable gate.

Abstract: An integrated circuit includes a three-dimensional cross-point memory having a plurality of levels of memory cells disposed in cross points of first access lines and second access lines with alternating wide and narrow regions. The manufacturing process of the three-dimensional cross-point memory includes patterning with three patterns: a first pattern to define the memory cells, a second pattern to define the first access lines, and a third pattern to define the second access lines.

Abstract: Embodiments described herein relate generally to one or more methods for forming a barrier layer for a conductive feature in semiconductor processing. In some embodiments, an opening is formed through a dielectric layer to a conductive feature. A barrier layer is formed in the opening along a sidewall of the dielectric layer and on a surface of the conductive feature. Forming the barrier layer includes depositing a layer including using a precursor gas. The precursor gas has a first incubation time for deposition on the surface of the conductive feature and has a second incubation time for deposition on the sidewall of the dielectric layer. The first incubation time is greater than the second incubation time. A conductive fill material is formed in the opening and on the barrier layer.

Abstract: A method of forming a fin field effect transistors (finFET) on a substrate includes forming a fin structure on the substrate, forming a protective layer on the fin structure, and forming a polysilicon structure on the protective layer. The method further includes modifying the polysilicon structure such that a first horizontal dimension of a first portion of the modified polysilicon structure is smaller than a second horizontal dimension of a second portion of the modified polysilicon structure. The method further includes replacing the modified polysilicon structure with a gate structure having a first horizontal dimension of a first portion of the gate structure that is smaller than a second horizontal dimension of a second portion of the gate structure.

Abstract: An object of the present invention is to provide a semiconductor device and a method of manufacturing thereof capable of relaxing a level difference thereon. A semiconductor device according to the present invention includes a first interlayer insulating film having a first opening, and a second interlayer insulating film having a second opening wherein a following expression is satisfied: (H2?H1)/((W2?W1)/2)?3.6 where, in sectional view, W1 represents a width of the first opening, W2 represents a width of the second opening, H1 represents a minimum value of a height from a surface of the semiconductor substrate to a surface of the third interlayer insulating film in the second opening, and H2 represents a height from the surface of the semiconductor substrate to the surface of the third interlayer insulating film in an end of the second opening.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a high mobility low contact resistance semiconducting oxide in metal contact vias for thin film transistors.

Abstract: An interconnect structure including a conductive layer, a spacer, a dielectric layer, and a contact is provided. The conductive layer is disposed on a substrate. The spacer is disposed on a sidewall of the conductive layer. The dielectric layer covers the conductive layer and the spacer. The contact is disposed in the dielectric layer and located on the conductive layer.

Abstract: Devices and methods are provided for fabricating shared contact trenches for source/drain layers of n-type and p-type field-effect transistor devices, wherein the shared contact trenches include dual silicide layers and dual epitaxial layers. For example, a semiconductor device includes first and second field-effect transistor devices having respective first and second source/drain layers, and a shared contact trench, wherein the first and second source/drain layers are disposed adjacent to each other within the shared contact trench, and are commonly connected to each other by the shared contact trench. The shared contact trench includes a first silicide contact layer disposed on the first source/drain layer, and a second silicide contact layer disposed on the second source/drain layer, wherein the first and second silicide contact layers comprise different silicide materials, and a metallic fill layer disposed on the first and second silicide contact layers.

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a plurality of spacers over the first mask layer, and forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, where in a plan view a major axis of the opening extends in a direction that is perpendicular to a major axis of a spacer of the plurality of spacers. The method also includes depositing a sacrificial material in the opening, patterning the sacrificial material, etching the first mask layer using the plurality of spacers and the patterned sacrificial material, etching the target layer using the etched first mask layer to form second openings in the target layer, and filling the second openings in the target layer with a conductive material.

Abstract: A device includes a semiconductor substrate, a gate stack, and an interlayer dielectric. The gate stack is over the semiconductor substrate. The interlayer dielectric is over the semiconductor substrate and surrounds the gate stack. The interlayer dielectric includes a liner layer and a filling layer. The liner layer lines the gate stack. The filling layer is over the liner layer and includes a metal-contained ternary dielectric material.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a semiconductor substrate, and an inter-tier interconnecting structure disposed within the semiconductor substrate. The inter-tier interconnect structure includes a first connection point at a lower surface of the inter-tier interconnecting structure and a second connection point at an upper surface of the inter-tier interconnecting structure. The first connection point and the second connection point are not vertically aligned. The inter-tier interconnecting structure includes one or more conductive layers extending between the first and second connection points.

Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.

Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.

Abstract: Disclosed herein is a device that includes a substrate, a contact plug disposed on the substrate, an interlayer dielectric over the substrate to define the contact plug, a titanium silicide extending continuously from an upper portion of the contact plug to over the interlayer dielectric, a conductive material disposed over the titanium silicide.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: The present disclosure discloses a flexible display panel and a flexible display device. The flexible display panel includes a first flexible substrate, a buffer layer, a display function layer, and a conduction function layer. The buffer layer and the display function layer are placed on a first side of the first flexible substrate. The conduction function layer is placed between the first flexible substrate and the display function layer, and is connected to a constant potential through a through-hole or by an end portion of the conduction function layer. By arranging the conduction function layer and connecting to the constant potential, an external interference signal from a back side of the substrate can be effectively shielded, and the conduction function layer can also serve as a blocking layer.

Abstract: A microelectronic method for etching a layer containing silicon nitride is provided, including the following successive steps: modifying the layer containing silicon nitride (SiN) so as to form at least one modified zone, the modifying including at least one implantation of ions made from hydrogen (H) in the layer containing SiN; and removing the at least one modified zone, the removing of the at least one modified zone including at least one step of etching of the at least one modified zone using a chemistry including at least: at least one compound chosen from the fluorocarbon compounds (CxFz) and the hydrofluorocarbon compounds (CxHyFz), and at least one compound chosen from SiwCl(2w+2) and SiwF(2w+2).

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.

Abstract: In a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer. A second source/drain epitaxial layer is formed over the etched first source/drain epitaxial layer. A conductive material is formed over the second source/drain epitaxial layer.

Abstract: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

Abstract: A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.

Abstract: A method of forming a semiconductor device includes etching an inter-layer dielectric (ILD) to form a contact opening exposing a portion of a source/drain (S/D). The method further includes depositing a titanium-containing material into the contact opening, wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of a material of the S/D along sidewalls of the ILD to form protrusions extending from a top surface of the S/D. The method further includes annealing the semiconductor device to form a silicide layer in the S/D and in the protrusions.

Abstract: Some embodiments include methods of removing particles from over surfaces of semiconductor substrates. Liquid may be flowed across the surfaces and the particles. While the liquid is flowing, electrophoresis and/or electroosmosis may be utilized to enhance transport of the particles from the surfaces and into the liquid. In some embodiments, temperature, pH and/or ionic strength within the liquid may be altered to assist in the removal of the particles from over the surfaces of the substrates.

Abstract: A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon, dielectric spacers on sidewalls of the gate electrode, a source and drain in the semiconductor surface on opposing sides of the gate electrode, and a pre-metal dielectric (PMD) layer over the gate electrode and over the source and drain regions. Contact holes are formed through the PMD layer to form a contact to the gate electrode and contacts to the source and drain. A post contact etch dielectric layer is then deposited on the contacts to source and drain and on sidewalls of the PMD layer. The post contact etch dielectric layer is selectively removed from the contacts to leave a dielectric liner on sidewalls of the PMD layer. A metal silicide layer is formed on the contacts to the source and drain.

Abstract: A semiconductor device includes first and second well regions having a first conductivity type, and a third well region between the first and second well regions having a second conductivity type different from the first conductivity type. A first active region is in the first well region. A second active region is in the second well region. A third active region is in the third well region. The third active region is closer to the second active region than to the first active region. A fourth active region is in the third well region. The fourth active region is closer to the first active region than to the second active region. A first conductive pattern is across the first and third active regions. A second conductive pattern is across the second and fourth active regions and parallel to the first conductive pattern.

Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.

Abstract: In a semiconductor device including a transistor including an oxide semiconductor film and a protective film over the transistor, an oxide insulating film containing oxygen in excess of the stoichiometric composition is formed as the protective film under the following conditions: a substrate placed in a treatment chamber evacuated to a vacuum level is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C.; a source gas is introduced into the treatment chamber so that the pressure in the treatment chamber is set to be higher than or equal to 100 Pa and lower than or equal to 250 Pa; and a high-frequency power higher than or equal to 0.17 W/cm2 and lower than or equal to 0.5 W/cm2 is supplied to an electrode provided in the treatment chamber.