With Contact To Source Or Drain Region Of Refractory Material (e.g., Polysilicon, Tungsten, Or Silicide) Patents (Class 257/382)
  • Patent number: 10741672
    Abstract: A method of forming a fin field effect transistors (finFET) on a substrate includes forming a fin structure on the substrate, forming a protective layer on the fin structure, and forming a polysilicon structure on the protective layer. The method further includes modifying the polysilicon structure such that a first horizontal dimension of a first portion of the modified polysilicon structure is smaller than a second horizontal dimension of a second portion of the modified polysilicon structure. The method further includes replacing the modified polysilicon structure with a gate structure having a first horizontal dimension of a first portion of the gate structure that is smaller than a second horizontal dimension of a second portion of the gate structure.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 10741442
    Abstract: Embodiments described herein relate generally to one or more methods for forming a barrier layer for a conductive feature in semiconductor processing. In some embodiments, an opening is formed through a dielectric layer to a conductive feature. A barrier layer is formed in the opening along a sidewall of the dielectric layer and on a surface of the conductive feature. Forming the barrier layer includes depositing a layer including using a precursor gas. The precursor gas has a first incubation time for deposition on the surface of the conductive feature and has a second incubation time for deposition on the sidewall of the dielectric layer. The first incubation time is greater than the second incubation time. A conductive fill material is formed in the opening and on the barrier layer.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Pang Kuo, Ya-Lien Lee
  • Patent number: 10665547
    Abstract: An object of the present invention is to provide a semiconductor device and a method of manufacturing thereof capable of relaxing a level difference thereon. A semiconductor device according to the present invention includes a first interlayer insulating film having a first opening, and a second interlayer insulating film having a second opening wherein a following expression is satisfied: (H2?H1)/((W2?W1)/2)?3.6 where, in sectional view, W1 represents a width of the first opening, W2 represents a width of the second opening, H1 represents a minimum value of a height from a surface of the semiconductor substrate to a surface of the third interlayer insulating film in the second opening, and H2 represents a height from the surface of the semiconductor substrate to the surface of the third interlayer insulating film in an end of the second opening.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: May 26, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuji Kawasaki, Manabu Yoshino
  • Patent number: 10644123
    Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a high mobility low contact resistance semiconducting oxide in metal contact vias for thin film transistors.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Van H. Le, Rafael Rios, Jack T. Kavalieros, Shriram Shivaraman
  • Patent number: 10580718
    Abstract: An interconnect structure including a conductive layer, a spacer, a dielectric layer, and a contact is provided. The conductive layer is disposed on a substrate. The spacer is disposed on a sidewall of the conductive layer. The dielectric layer covers the conductive layer and the spacer. The contact is disposed in the dielectric layer and located on the conductive layer.
    Type: Grant
    Filed: January 14, 2018
    Date of Patent: March 3, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Ming-Chung Chiang
  • Patent number: 10566246
    Abstract: Devices and methods are provided for fabricating shared contact trenches for source/drain layers of n-type and p-type field-effect transistor devices, wherein the shared contact trenches include dual silicide layers and dual epitaxial layers. For example, a semiconductor device includes first and second field-effect transistor devices having respective first and second source/drain layers, and a shared contact trench, wherein the first and second source/drain layers are disposed adjacent to each other within the shared contact trench, and are commonly connected to each other by the shared contact trench. The shared contact trench includes a first silicide contact layer disposed on the first source/drain layer, and a second silicide contact layer disposed on the second source/drain layer, wherein the first and second silicide contact layers comprise different silicide materials, and a metallic fill layer disposed on the first and second silicide contact layers.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Kangguo Cheng, Junli Wang, Zuoguang Liu
  • Patent number: 10559492
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a plurality of spacers over the first mask layer, and forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, where in a plan view a major axis of the opening extends in a direction that is perpendicular to a major axis of a spacer of the plurality of spacers. The method also includes depositing a sacrificial material in the opening, patterning the sacrificial material, etching the first mask layer using the plurality of spacers and the patterned sacrificial material, etching the target layer using the etched first mask layer to form second openings in the target layer, and filling the second openings in the target layer with a conductive material.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: February 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Wen-Yen Chen, Chih-Hao Chen
  • Patent number: 10510895
    Abstract: A device includes a semiconductor substrate, a gate stack, and an interlayer dielectric. The gate stack is over the semiconductor substrate. The interlayer dielectric is over the semiconductor substrate and surrounds the gate stack. The interlayer dielectric includes a liner layer and a filling layer. The liner layer lines the gate stack. The filling layer is over the liner layer and includes a metal-contained ternary dielectric material.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 10497661
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a semiconductor substrate, and an inter-tier interconnecting structure disposed within the semiconductor substrate. The inter-tier interconnect structure includes a first connection point at a lower surface of the inter-tier interconnecting structure and a second connection point at an upper surface of the inter-tier interconnecting structure. The first connection point and the second connection point are not vertically aligned. The inter-tier interconnecting structure includes one or more conductive layers extending between the first and second connection points.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiang-Jen Tseng, Wei-Yu Chen, Ting-Wei Chiang, Li-Chun Tien
  • Patent number: 10490454
    Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
  • Patent number: 10483158
    Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 19, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Hsuan-Tai Hsu, Kuan-Hsuan Ku
  • Patent number: 10468347
    Abstract: Disclosed herein is a device that includes a substrate, a contact plug disposed on the substrate, an interlayer dielectric over the substrate to define the contact plug, a titanium silicide extending continuously from an upper portion of the contact plug to over the interlayer dielectric, a conductive material disposed over the titanium silicide.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: November 5, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Tomohiro Kadoya
  • Patent number: 10446646
    Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: October 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chao Huang, Yee-Chia Yeo, Chao-Hsiung Wang, Chun-Chieh Lin, Chenming Hu
  • Patent number: 10446634
    Abstract: The present disclosure discloses a flexible display panel and a flexible display device. The flexible display panel includes a first flexible substrate, a buffer layer, a display function layer, and a conduction function layer. The buffer layer and the display function layer are placed on a first side of the first flexible substrate. The conduction function layer is placed between the first flexible substrate and the display function layer, and is connected to a constant potential through a through-hole or by an end portion of the conduction function layer. By arranging the conduction function layer and connecting to the constant potential, an external interference signal from a back side of the substrate can be effectively shielded, and the conduction function layer can also serve as a blocking layer.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: October 15, 2019
    Assignee: TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Xu Qian, Wenxin Jiang, Yuan Li
  • Patent number: 10446408
    Abstract: A microelectronic method for etching a layer containing silicon nitride is provided, including the following successive steps: modifying the layer containing silicon nitride (SiN) so as to form at least one modified zone, the modifying including at least one implantation of ions made from hydrogen (H) in the layer containing SiN; and removing the at least one modified zone, the removing of the at least one modified zone including at least one step of etching of the at least one modified zone using a chemistry including at least: at least one compound chosen from the fluorocarbon compounds (CxFz) and the hydrofluorocarbon compounds (CxHyFz), and at least one compound chosen from SiwCl(2w+2) and SiwF(2w+2).
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: October 15, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Nicolas Posseme
  • Patent number: 10411113
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: September 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Kuo-Hui Chang, Yi-Cheng Chao
  • Patent number: 10325911
    Abstract: In a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer. A second source/drain epitaxial layer is formed over the etched first source/drain epitaxial layer. A conductive material is formed over the second source/drain epitaxial layer.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yuan Lu, Sai-Hooi Yeong
  • Patent number: 10199505
    Abstract: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: February 5, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 10163643
    Abstract: A method of forming a semiconductor device includes etching an inter-layer dielectric (ILD) to form a contact opening exposing a portion of a source/drain (S/D). The method further includes depositing a titanium-containing material into the contact opening, wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of a material of the S/D along sidewalls of the ILD to form protrusions extending from a top surface of the S/D. The method further includes annealing the semiconductor device to form a silicide layer in the S/D and in the protrusions.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yang Wu, Shiu-Ko Jangjian, Keng-Chuan Chang, Ting-Siang Su
  • Patent number: 10164030
    Abstract: A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: December 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-bum Kim, Chul-sung Kim, Deok-han Bae, Bon-young Koo
  • Patent number: 10137481
    Abstract: Some embodiments include methods of removing particles from over surfaces of semiconductor substrates. Liquid may be flowed across the surfaces and the particles. While the liquid is flowing, electrophoresis and/or electroosmosis may be utilized to enhance transport of the particles from the surfaces and into the liquid. In some embodiments, temperature, pH and/or ionic strength within the liquid may be altered to assist in the removal of the particles from over the surfaces of the substrates.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: November 27, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Joseph Neil Greeley, Dan Millward, Wayne Huang
  • Patent number: 10134731
    Abstract: A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon, dielectric spacers on sidewalls of the gate electrode, a source and drain in the semiconductor surface on opposing sides of the gate electrode, and a pre-metal dielectric (PMD) layer over the gate electrode and over the source and drain regions. Contact holes are formed through the PMD layer to form a contact to the gate electrode and contacts to the source and drain. A post contact etch dielectric layer is then deposited on the contacts to source and drain and on sidewalls of the PMD layer. The post contact etch dielectric layer is selectively removed from the contacts to leave a dielectric liner on sidewalls of the PMD layer. A metal silicide layer is formed on the contacts to the source and drain.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: November 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Tom Lii
  • Patent number: 10128255
    Abstract: A semiconductor device includes first and second well regions having a first conductivity type, and a third well region between the first and second well regions having a second conductivity type different from the first conductivity type. A first active region is in the first well region. A second active region is in the second well region. A third active region is in the third well region. The third active region is closer to the second active region than to the first active region. A fourth active region is in the third well region. The fourth active region is closer to the first active region than to the second active region. A first conductive pattern is across the first and third active regions. A second conductive pattern is across the second and fourth active regions and parallel to the first conductive pattern.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: November 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Me Lim, Kyung-Woo Kim, Myung-Soo Seo
  • Patent number: 10109599
    Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Cathryn J. Christiansen, Anthony K. Stamper, Tom C. Lee, Ian Mccallum-Cook
  • Patent number: 10096719
    Abstract: In a semiconductor device including a transistor including an oxide semiconductor film and a protective film over the transistor, an oxide insulating film containing oxygen in excess of the stoichiometric composition is formed as the protective film under the following conditions: a substrate placed in a treatment chamber evacuated to a vacuum level is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C.; a source gas is introduced into the treatment chamber so that the pressure in the treatment chamber is set to be higher than or equal to 100 Pa and lower than or equal to 250 Pa; and a high-frequency power higher than or equal to 0.17 W/cm2 and lower than or equal to 0.5 W/cm2 is supplied to an electrode provided in the treatment chamber.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: October 9, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kenichi Okazaki, Toshinari Sasaki, Shuhei Yokoyama, Takashi Hamochi
  • Patent number: 10075664
    Abstract: A light receiving element includes a first semiconductor layer of a first conductivity type to which a first potential is to be applied, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, first and second regions of the first conductivity type formed in an upper portion of the second semiconductor layer, a first electrode that is located on the first region and is to be subjected to application of a second potential, a second electrode located on the second region, an insulation layer formed on the second semiconductor layer between the first and the second regions, and a gate electrode that is formed on the insulation layer and is to be subjected to application of a gate voltage. A current readout unit detects, as a pixel signal reflecting an amount of light received, a current flowing from the first region to the second region.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: September 11, 2018
    Assignees: Technology Hub Inc., MegaChips Corporation
    Inventors: Yukihiro Ukai, Takashi Sawada
  • Patent number: 10032793
    Abstract: A method for forming a semiconductor device. It includes forming fin structures on a substrate, where the fin structure defines source and drain regions. It also includes forming a gate stack in contact with the fin structure, depositing an insulator on the substrate, and applying an etching process to remove portions of the insulator to form a trench to the source region. It also includes implanting a damaged epitaxial material into the trench and to the source regions, and applying a second etching process to remove portions of the insulator to form a trench in the insulator to the drain regions. Finally, the method includes growing an epitaxial junction material over the source and drain regions, and depositing a metal over the substrate.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 10020378
    Abstract: Methods of forming a semiconductor device include laterally etching a dummy gate to recess the dummy gate underneath a spacer layer, such that the spacer layer overhangs the dummy gate. A sidewall of the dummy gate is nitridized. The dummy gate is etched away without removing the nitridized sidewall.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: July 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Dechao Guo, Zuoguang Liu
  • Patent number: 10002968
    Abstract: A first transistor and a second transistor are stacked. The first transistor and the second transistor have a gate electrode in common. At least one of semiconductor films used in the first transistor and the second transistor is an oxide semiconductor film. With the use of the oxide semiconductor film as the semiconductor film in the transistor, high field-effect mobility and high-speed operation can be achieved. Since the first transistor and the second transistor are stacked and have the gate electrode in common, the area of a region where the transistors are disposed can be reduced.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: June 19, 2018
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Seiichi Yoneda
  • Patent number: 9958736
    Abstract: The liquid crystal display device includes an island-shaped first semiconductor film 102 which is formed over a base insulating film 101 and in which a source 102d, a channel forming region 102a, and a drain 102b are formed; a first electrode 102c which is formed of a material same as the first semiconductor film 102 to be the source 102d or the drain 102b and formed over the base insulating film 101; a second electrode 108 which is formed over the first electrode 102c and includes a first opening pattern 112; and a liquid crystal 110 which is provided over the second electrode 108.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: May 1, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 9947796
    Abstract: The present invention provides an oxide thin film transistor and a manufacturing method thereof, an array substrate and a display device. The oxide thin film transistor of the present invention comprises a substrate, and a gate, a gate insulation layer, an oxide semiconductor active layer, a source and a drain, which are sequentially formed on the substrate, wherein, the oxide thin film transistor further comprises a transition layer formed between the oxide semiconductor active layer and the source and between the oxide semiconductor active layer and the drain, the transition layer comprises a metal layer and a protective layer, and the protective layer is in contact with the oxide semiconductor active layer, the metal layer is arranged on the protective layer and in contact with the source and the drain, and the protective layer is made of a metal oxide.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: April 17, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xiang Liu
  • Patent number: 9899521
    Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and wherein a surface of the strained material has received a passivation treatment; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; a metal barrier coating an opening of the dielectric layer; and a metal layer filling a coated opening of the dielectric layer.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Ding-Kang Shih, Chih-Hsin Ko
  • Patent number: 9899522
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first recess adjacent to two sides of the gate structure; forming an epitaxial layer in the first recess; removing part of the epitaxial layer to forma second recess; and forming an interlayer dielectric (ILD) layer on the gate structure and into the second recess.
    Type: Grant
    Filed: January 8, 2017
    Date of Patent: February 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Patent number: 9893195
    Abstract: A highly reliable transistor which includes an oxide semiconductor and has high field-effect mobility and in which a variation in threshold voltage is small is provided. By using the transistor, a high-performance semiconductor device, which has been difficult to realize, is provided. The transistor includes an oxide semiconductor film which contains two or more kinds, preferably three or more kinds of elements selected from indium, tin, zinc, and aluminum. The oxide semiconductor film is formed in a state where a substrate is heated. Further, oxygen is supplied to the oxide semiconductor film with an adjacent insulating film and/or by ion implantation in a manufacturing process of the transistor, so that oxygen deficiency which generates a carrier is reduced as much as possible. In addition, the oxide semiconductor film is highly purified in the manufacturing process of the transistor, so that the concentration of hydrogen is made extremely low.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: February 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kosei Noda, Shunpei Yamazaki, Tatsuya Honda, Yusuke Sekine, Hiroyuki Tomatsu
  • Patent number: 9882063
    Abstract: The present disclosure relates to the field of manufacturing technologies for semiconductor devices and provides a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor includes: an active layer located on a plane; a source electrode, which is located on the active layer and is in contact with the active layer; a first insulation layer located on the source electrode and including a first via hole; and a drain electrode located on the first insulation layer, where the drain electrode is in contact with the active layer via the first via hole.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: January 30, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Li Zhang
  • Patent number: 9852947
    Abstract: A method includes etching a dielectric layer to form an opening, with a component of a transistor being exposed through the opening. A spacer layer is formed, and includes a horizontal portion at a bottom of the opening, and a vertical portion in the opening. The vertical portion is on a sidewall of the dielectric layer. An isotropic etch is performed on the spacer layer to remove the horizontal portion, and the vertical portion remains after the isotropic etch. The remaining vertical portion forms a contact plug spacer. A conductive material is filled into the opening to form a contact plug.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: December 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ting Ko, Kuang-Yuan Hsu
  • Patent number: 9853059
    Abstract: A semiconductor device includes a first transistor including a first electrode, a first insulating layer above the first electrode, the first insulating layer having a first side wall, a first oxide semiconductor layer on the first side wall, the first oxide semiconductor layer being connected with the first electrode, a first gate electrode, a first gate insulating layer, and a second electrode above the first insulating layer, the second electrode being connected with the first oxide semiconductor layer; and a second transistor including a third electrode, a fourth electrode separated from the third electrode, a second oxide semiconductor layer between the third electrode and the fourth electrode, the second oxide semiconductor layer being connected with each of the third electrode and the fourth electrode, a second gate electrode, and a second gate insulating layer.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: December 26, 2017
    Assignee: Japan Display Inc.
    Inventor: Toshinari Sasaki
  • Patent number: 9810956
    Abstract: The liquid crystal display device includes an island-shaped first semiconductor film 102 which is formed over a base insulating film 101 and in which a source 102d, a channel forming region 102a, and a drain 102b are formed; a first electrode 102c which is formed of a material same as the first semiconductor film 102 to be the source 102d or the drain 102b and formed over the base insulating film 101; a second electrode 108 which is formed over the first electrode 102c and includes a first opening pattern 112; and a liquid crystal 110 which is provided over the second electrode 108.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: November 7, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 9779988
    Abstract: A semiconductor device includes a semiconductor substrate having an inactive area and a pair of active areas separated by the inactive area, a control terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area to define a conduction path during operation between a first conduction region in each active area and a second conduction region in each active area, a conduction terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area for electrical connection to each first conduction region, and a via extending through the semiconductor substrate, electrically connected to the conduction terminal, and positioned in the inactive area.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: October 3, 2017
    Assignee: NXP USA, INC.
    Inventors: Darrell G. Hill, Marcel N. Tutt
  • Patent number: 9728648
    Abstract: A miniaturized transistor having excellent electrical characteristics is provided with high yield. Further, a semiconductor device including the transistor and having high performance and high reliability is manufactured with high productivity. In a semiconductor device including a transistor in which an oxide semiconductor film including a channel formation region and low-resistance regions between which the channel formation region is sandwiched, a gate insulating film, and a gate electrode layer whose top surface and side surface are covered with an insulating film including an aluminum oxide film are stacked, a source electrode layer and a drain electrode layer are in contact with part of the oxide semiconductor film and the top surface and a side surface of the insulating film including an aluminum oxide film.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: August 8, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata
  • Patent number: 9685456
    Abstract: A transistor device is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at a position where a gate is to be located. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are then converted into a transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are converted into a transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: June 20, 2017
    Assignee: STMicroelectronics, Inc.
    Inventor: John Hongguang Zhang
  • Patent number: 9679889
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a substrate; forming a well region on the substrate; forming at least one first gate structure on the well region, wherein the first gate structure includes a gate insulating layer and a first gate electrode formed on the gate insulating layer, wherein the first gate electrode is formed having a first enclosed pattern on a surface of the well region; wherein an area inside the first enclosed pattern is defined as a first region, and an area outside the first enclosed pattern is defined as a second region; performing ion implantation on the first region such that the first region has a first conductivity type, and performing ion implantation on the second region such that the second region has a second conductivity type, wherein the first conductivity type and the second conductivity type are different.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: June 13, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Zhenghao Gan
  • Patent number: 9666800
    Abstract: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: May 30, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 9653364
    Abstract: Provided is a FinFET device including a substrate having at least one fin, first and second gate stacks, first and second strained layers, first and second dielectric layers, and first and second connectors. The first and second gate stacks are across the fin. The first and second strained layers are respectively aside the first and second gate stacks. The first and second dielectric layer are respectively over the first and second strained layers, and the top surface of the first dielectric layer is lower than the top surface of the second dielectric layer. The first connector is through the first dielectric layer and is electrically connected to the first strained layer. The second connector is through the second dielectric layer and is electrically connected to the second strained layer. Besides, the width of the second connector is greater than the width of the first connector.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 9640539
    Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: May 2, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Steven Alan Lytle
  • Patent number: 9627537
    Abstract: Provided is a FinFET device including a substrate having at least one fin, first and second gate stacks, first and second strained layers, a shielding layer and first and second connectors. The first and second gate stacks are across the fin. The first and second strained layers are respectively aside the first and second gate stacks. The shielding layer is over the second gate stack, over a top surface and a sidewall of the first gate stack and discontinuous around a top corner of the first gate stack. The first connector is through the shielding layer and is electrically connected to the first stained layer. The second connector is through the shielding layer and is electrically connected to the second stained layer. Besides, the width of the second connector is greater than the width of the first connector.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 9627502
    Abstract: A circuit arrangement may be provided. The circuit arrangement may include a semiconductor substrate including a first surface, a second surface opposite the first surface, and a first doped region of a first conductivity type extending from the first surface into the semiconductor substrate. The circuit arrangement may include at least one capacitor including a first electrode including a doped region of the first conductivity type extending from the second surface into the semiconductor substrate, a dielectric layer formed over the first electrode extending from the second surface away from the semiconductor substrate, and a second electrode formed over the dielectric layer opposite the first electrode. The circuit arrangement may further include at least one semiconductor device monolithically integrated in the semiconductor substrate.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: April 18, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Detlef Wilhelm
  • Patent number: 9620566
    Abstract: A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: April 11, 2017
    Assignee: SK Hynix Inc.
    Inventor: Nam Kyun Park
  • Patent number: 9620524
    Abstract: An array substrate and a manufacturing method thereof as well as a display device are disclosed. The array substrate includes a gate (21) and a gate insulating layers (22) of TFT formed in this order on a surface of a base substrate (20); a semiconductor active layer (23), an etching stop layer (24), and a source (251)/drain (252) of the TFT formed in this order on a surface of the gate insulating layer (22) corresponding to the gate (21) of the TFT. The source (251) and drain (252) of the TFT contact the semiconductor active layer (23) through respective vias. The array substrate further includes: a shielding electrode (26) formed between the gate (21) of the TFT and the base substrate (20); and an insulating layer (27) formed between the gate (21) of the TFT and the shielding electrode (26).
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: April 11, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Heecheol Kim, Youngsuk Song, Seongyeol Yoo, Seungjin Choi
  • Patent number: 9614050
    Abstract: The present invention provides a method for manufacturing a semiconductor device, comprising: forming a contact sacrificial pattern on a substrate to cover source and drain regions and expose a gate region; forming an interlayer dielectric layer on the substrate to cover the contact sacrificial pattern and expose the gate region; forming a gate stack structure in the exposed gate region; removing the contact sacrificial pattern to form the source/drain contact trench; and forming a source/drain contact in the source/drain contact trench. By means of a contact sacrificial layer process, the method of manufacturing a semiconductor device according to the present invention effectively reduces the distance between the gate spacer and the contact region and increases the area of the contact region, thus effectively reducing the parasitic resistance of the device.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: April 4, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Haizhou Yin, Keke Zhang