Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.

Abstract: Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers.

Abstract: A field effect transistor having a source, drain, and a gate can include a semiconductor substrate, a buried insulator layer positioned on the semiconductor substrate, and a semiconductor overlayer positioned on the buried insulator layer; a low dopant channel region positioned below the gate and between the source and the drain and in an upper portion of the semiconductor overlayer; and a plurality of doped regions having a predetermined dopant concentration profile, including a screening region positioned in the semiconductor overlayer below the low dopant channel region, the screening region extending toward the buried insulator layer, and a threshold voltage set region positioned between the screening region and the low dopant channel, the screening region and the threshold voltage set region having each a peak dopant concentration, the threshold voltage region peak dopant concentration being between 1/50 and ½ of the peak dopant concentration of the screening region.

Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral sidewall. A hard mask layer may be formed on the top surface of the fin (e.g., providing a dual-gate device). A gate dielectric layer and work function metal layer are formed on the first and second lateral sidewalls of the fin. A silicide layer is formed on the work function metal layer on the first and the second lateral sidewalls of the fin. The silicide layer may be a fully-silicided layer and may provide a stress to the channel region of the device disposed in the fin.

Abstract: Provided is a production method for a semiconductor device comprising a metal silicide layer. According to one embodiment of the present invention, the production method for a semiconductor device comprises the steps of: forming an insulating layer on a substrate, on which a polysilicon pattern has been formed, in such a way that the polysilicon pattern is exposed; forming a silicon seed layer on the exposed polysilicon pattern that has been selectively exposed with respect to the insulating layer; forming a metal layer on the substrate on which the silicon seed layer has been formed; and forming a metal silicide layer by carrying out a heat treatment on the substrate on which the metal layer has been formed.

Abstract: A transistor is formed in a semiconductor substrate with a gate over a channel region, source/drain extension regions in the substrate adjacent the channel region, and source/drain regions in the substrate adjacent the source/drain extension regions. Silicide is formed on the source/drain extension regions and the source/drain regions so that the silicide has a first thickness over the source/drain extension regions and a second thickness over source/drain regions, with the second thickness being greater than the first thickness. Silicide on the source/drain extension regions lowers transistor series resistance which boosts transistor performance and also protects the source/drain extension regions from silicon loss and silicon damage during contact etch.

Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. A substrate with plural metal gates formed thereon is provided, wherein the adjacent metal gates are separated by insulation. A sacrificial layer is formed for capping the metal gates and the insulation, and the sacrificial layer and the insulation are patterned to form at least an opening for exposing the substrate. A silicide is formed corresponding to the opening at the substrate, and a conductive contact is formed in the opening. The conductive contact has a top area with a second diameter CD2 for opening the insulation. A patterned dielectric layer, further formed on the metal gates, the insulation and the conductive contact, at least has a first M0 opening with a third diameter CD3 for exposing the conductive contact, wherein CD2>CD3.

Abstract: A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes.

Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. A substrate with plural metal gates formed thereon is provided, wherein the adjacent metal gates are separated by insulation. A sacrificial layer is formed for capping the metal gates and the insulation, and the sacrificial layer and the insulation are patterned to form at least an opening for exposing the substrate. A silicide is formed corresponding to the opening at the substrate, and a conductive contact is formed in the opening. The conductive contact has a top area with a second diameter CD2 for opening the insulation. A patterned dielectric layer, further formed on the metal gates, the insulation and the conductive contact, at least has a first M0 opening with a third diameter CD3 for exposing the conductive contact, wherein CD2>CD3.

Abstract: A semiconductor device including buried bit lines formed of a metal silicide and silicidation preventing regions formed in a substrate under trenches that separate the buried bit lines.

Abstract: A multi-wavelength semiconductor laser device includes a block having a V-shaped groove with two side faces extending in a predetermined direction; and laser diodes with different light emission wavelengths mounted on the side faces of the groove in the block so that their laser beams are emitted in the predetermined direction.

Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.

Abstract: A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.

Abstract: Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a contact electrode. The silicon carbide substrate includes an n type region and a p type region that makes contact with the n type region. The contact electrode makes contact with the n type region and the p type region. The contact electrode contains Ni atoms and Si atoms. The number of the Ni atoms is not less than 87% and not more than 92% of the total number of the Ni atoms and the Si atoms. Accordingly, there can be provided a silicon carbide semiconductor device, which can achieve ohmic contact with an n type impurity region and can achieve a low contact resistance for a p type impurity region, as well as a method for manufacturing such a silicon carbide semiconductor device.

Abstract: Embodiments of the present invention provide a contact structure for transistor. The contact structure includes a first epitaxial-grown region between a first and a second gate of, respectively, a first and a second transistor; a second epitaxial-grown region directly on top of the first epitaxial-grown region with the second epitaxial-grown region having a width that is wider than that of the first epitaxial-grown region; and a silicide region formed on a top portion of the second epitaxial-grown region with the silicide region having an interface, with rest of the second epitaxial-grown region, that is wider than that of the first epitaxial-grown region. In one embodiment, the second epitaxial-grown region is at a level above a top surface of the first and second gates of the first and second transistors.

Abstract: A method for performing silicidation of a gate electrode is provided that includes forming both a first transistor with a first gate electrode covered by a cap layer and a semiconductor device on the same semiconductor substrate, forming an organic planarization layer (OPL) on the first transistor and the semiconductor device, back etching the OPL such that an upper surface of the OPL is positioned at a level that is below a level of an upper surface of the cap layer, forming a mask layer covering the semiconductor device without covering the first transistor, removing the cap layer while the back-etched OPL and the mask layer are present, and performing silicidation of the first gate electrode.

Abstract: A fin field-effect transistor structure comprises a substrate, a fin channel, a source/drain region, a high-k metal gate and a plurality of slot contact structures. The fin channel is formed on the substrate. The source/drain region is formed in the fin channel. The high-k metal gate formed on the substrate and the fin channel comprises a high-k dielectric layer and a metal gate layer, wherein the high-k dielectric layer is arranged between the metal gate layer and the fin channel. The slot contact structures are disposed at both sides of the metal gate.

Abstract: Disclosed is a semiconductor structure incorporating a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure. The structure comprises a semiconductor device (e.g., a two-terminal device, such as a PN junction diode or Schottky diode, or a three-terminal device, such as a field effect transistor (FET), a bipolar junction transistor (BJT), etc.) and a dielectric layer that covers the semiconductor device. A contact extends vertically through the dielectric layer to a terminal of the semiconductor device (e.g., in the case of a FET, to a source/drain region of the FET). A contact sidewall spacer is positioned on the contact sidewall and incorporates an airgap. Since air has a lower dielectric constant than other typically used dielectric spacer or interlayer dielectric materials, the contact size can be increased for reduced parasitic resistance while minimizing corresponding increases in parasitic capacitance or the probability of shorts.

Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode structure including a gate electrode located on an active region of the semiconductor substrate, first and second epitaxial regions located in the active region at opposite sides of the gate electrode structure, and first and second silicide layers on upper surfaces of the first and second epitaxial regions, respectively. The first and second epitaxial regions include Si—X, where X is one of germanium and carbon, and at least a portion of each of the first and second silicide layers is devoid of X and includes Si—Y, where Y is a metal or metal alloy.

Abstract: A method for manufacturing a semiconductor structure comprises: providing a substrate (100) on which a dummy gate stack is formed, forming a spacer (240) at sidewalls of the dummy gate stack, and forming a source/drain region (110) and a source/drain extension region (111) at both sides of the dummy gate stack; removing at least part of the spacer (240), to expose at least part of the source/drain extension region (111); forming a contact layer (112) on the source/drain region (110) and the exposed source/drain extension region (111), the contact layer (112) being [made of] one of CoSi2, NiSi and Ni(Pt)Si2-y or combinations thereof, and a thickness of the contact layer (112) being less than 10 nm. Correspondingly, the present invention further provides a semiconductor structure which is beneficial to reducing contact resistance and can maintain excellent performance in a subsequent high temperature process.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate.

Abstract: Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

Abstract: A semiconductor device, comprising a substrate, a plurality of polysilicon portions formed on the substrate, wherein the polysilicon portions are spaced apart from each other, a plurality of source/drain regions formed in the substrate between adjacent polysilicon portions, and a dielectric layer formed on the polysilicon portions and on the source/drain regions, wherein the dielectric layer includes a cavity filled with conductive material to form a contact area, the contact area overlapping part of a source/drain region and part of a polysilicon portion to electrically connect the polysilicon portion with the source/drain region, and wherein part of the contact area extends below an upper surface of the substrate to contact an implant region with the same doping as the source/drain region. The implant region is next to the source/drain region and includes part of a channel region in the substrate under the polysilicon portion.

Abstract: A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes.

Abstract: A semiconductor device according to an embodiment includes: a substrate; a first semiconductor layer formed on the substrate and having a strain; a second and a third semiconductor layers formed at a distance from each other on the first semiconductor layer, and having a different lattice constant from a lattice constant of the first semiconductor layer; a gate insulating film formed on a first portion of the first semiconductor layer, the first portion being located between the second semiconductor layer and the third semiconductor layer; and a gate electrode formed on the gate insulating film.

Abstract: Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA.

Abstract: Structures and methods of fabrication thereof related to an improved semiconductor on insulator (SOI) transistor formed on an SOI substrate. The improved SOI transistor includes a substantially undoped channel extending between the source and the drain, an optional threshold voltage set region positioned below the substantially undoped channel, and a screening region positioned below the threshold voltage set region. The threshold voltage of the improved SOI transistor can be adjusted without halo implants or threshold voltage implants into the channel, using the position and/or dopant concentration of the screening region and/or the threshold voltage set region.

Abstract: Disclosed herein are various methods of forming replacement gate structures and conductive contacts on semiconductor devices and devices incorporating the same. One exemplary device includes a plurality of gate structures positioned above a semiconducting substrate, at least one sidewall spacer positioned proximate respective sidewalls of the gate structures, and a metal silicide region in a source/drain region of the semiconducting substrate, the metal silicide region extending laterally so as to contact the sidewall spacer positioned proximate each of the gate structures.

Abstract: The present invention discloses a semiconductor device and a manufacturing method therefor. Conventionally, platinum is deposited in a device substrate to suppress diffusion of nickel in nickel silicide. However, introducing platinum by means of deposition makes the platinum only stay on the surface but fails to effectively suppress the diffusion of nickel over a desirable depth. According to the present invention, a semiconductor device is formed by implanting platinum into a substrate and forming NiSi in a region of the substrate where platinum is implanted. With the present invention, platinum can be distributed over a desirable depth range so as to more effectively suppress nickel diffusion.

Abstract: A semiconductor device includes a semiconductor substrate including a DRAM portion and a logic portion thereon, an interlayer film covering the DRAM portion and logic portion of the semiconductor substrate, and plural contact plugs formed in the interlayer film in the DRAM portion and the logic portion, the plural contact plugs being in contact with a metal suicide layer on a highly-doped region of source and drain regions of first, second and third transistors in the DRAM portion and the logic portion, an interface between the plural contact plugs and the metal silicide layer being formed at a main surface in the DRAM portion and the logic portion.

Abstract: A semiconductor device equally turns on the parasitic bipolar transistors in the finger portions of the finger form source and drain electrodes when a surge voltage is applied, even with the P+ type contact layer surrounding the N+ type source layers and the N+ type drain layers connected to the finger form source and drain electrodes. A P+ type contact layer surrounds N+ type source layers and N+ type drain layers. Metal silicide layers are formed on the N+ type source layers, the N+ type drain layers, and a portion of the P+ type contact layer. Finger form source electrodes, finger form drain electrodes, and a P+ type contact electrode surrounding these finger form electrodes are formed, being connected to the metal silicide layers respectively through contact holes formed in an interlayer insulation film deposited on the metal silicide layers.

Abstract: A first insulating film is formed above a semiconductor substrate with a device isolation insulating film defining a device region, a gate electrode and source/drain region formed. The first insulating film is etched, leaving the first insulating film in a recess formed in an edge of the device isolation insulating film. A second insulating film applying a stress to the semiconductor substrate is formed after etching the first insulating film.

Abstract: A multi-wavelength semiconductor laser device includes a block having a rectangular groove with a bottom face and two side faces extending in a predetermined direction; and laser diodes with different light emission wavelengths mounted on the bottom face and the side faces of the groove in the block so that their laser beams are emitted in the predetermined direction.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device which includes a MISFET, includes: forming a gate insulating film on a semiconductor substrate; forming a gate electrode on the gate insulating film; implanting nitrogen equal to or more than 5.0e14 atoms/cm2 and equal to or less than 1.5e15 atoms/cm2 in the semiconductor substrate by tilted ion implantation in a direction from an outside to an inside with respect to side surfaces of the gate electrode; depositing a metal film including nickel on areas in which nitrogen atoms are implanted, the areas are in a semiconductor substrate on both sides of the gate electrode; and performing first heat processing of reacting the metal film and the semiconductor substrate and forming metal semiconductor compound layers, the shapes of the layers are controlled by the nitrogen profiles of the areas.

Abstract: A field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer.

Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a major surface; a first fin and a second fin extending upward from the substrate major surface to a first height; an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, whereby portions of the fins extend beyond the top surface of the insulation layer; each fin covered by a bulbous epitaxial layer defining an hourglass shaped cavity between adjacent fins, the cavity comprising upper and lower portions, wherein the epitaxial layer bordering the lower portion of the cavity is converted to silicide.

Abstract: There is provided a semiconductor device and a method of fabricating the same. The method of fabricating a semiconductor device according to the present invention comprises: forming a transistor structure including a gate, and source and drain regions on a semiconductor substrate; carrying out a first silicidation to form a first metal silicide layer on the source and drain regions; depositing a first dielectric layer on the substrate, the top of the first dielectric layer being flush with the top of the gate region; forming contact holes at the portions corresponding to the source and drain regions in the first dielectric layer; and carrying out a second silicidation to form a second metal silicide at the gate region and in the contact holes, wherein the first metal silicide layer is formed to prevent silicidation from occurring at the source and drain regions during the second silicidation.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes simultaneously shielding a shielded region of a semiconductor substrate and exposing a surface of the shielded region of the semiconductor substrate. An ion implantation is performed to form implant areas in a non-shielded region of the semiconductor substrate adjacent the shielded region. Also, the semiconductor substrate is silicided to form a silicided area in the shielded region of the semiconductor substrate.

Abstract: A device includes a metal-oxide-semiconductor (MOS) device, which includes a gate electrode and a source/drain region adjacent the gate electrode. A first and a second contact plug are formed directly over and electrically connected to two portions of a same MOS component, wherein the same MOS component is one of the gate electrode and the source/drain region. The same MOS component is configured to be used as a resistor that is connected between the first and the second contact plugs.

Abstract: A structure for a semiconductor device, according to an embodiment, includes: a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element.

Abstract: The present invention provides a method for manufacturing a semiconductor structure. The method can effectively reduce the contact resistance between source/drain regions and a contact layer by forming two contact layers of different thickness on the surfaces of the source/drain regions. Further, the present invention provides a semiconductor structure, which has reduced the contact resistance.

Abstract: A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure.

Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Abstract: Provided are a semiconductor device and a method of fabricating the same. According to the semiconductor device, a silicide layer is formed on at least a part of both sidewalls of a gate pattern on a device isolation layer, thereby reducing resistance of the gate pattern. This makes an operation speed of the device rapid. According to the method of the semiconductor device, a sidewall spacer pattern is formed on at least a part of both sidewalls of the gate pattern in following salicide process by entirely or partially removing remaining portions of the sidewall spacer except for portions which are used as an ion implantation mask to form source/drain regions. This can reduce resistance of the gate pattern, thereby fabricating a semiconductor device with a rapid operation speed.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.

Abstract: Current drive efficiency is deteriorated in the conventional FET. The FET 20 includes an electrode film 24a provided over the semiconductor substrate 10 and a stressor film 24b that is provided on the electrode film 24a and constitutes a gate electrode 24 together with the electrode film 24a. Each of the electrode film 24a and the stressor film 24b is composed of a metal, a metallic nitride or a metallic silicide. The stressor film 24b is capable of exhibiting a compressive stress over the semiconductor substrate 10.

Abstract: A method of manufacturing a semiconductor device includes: forming a recessed portion in a semiconductor substrate; forming an insulating film in the recessed portion; after forming the insulating film, forming a silicide layer on the semiconductor substrate in contact with the insulating film; and performing alignment between an electron beam exposure apparatus and the semiconductor substrate by using the insulating film and the silicide layer as an alignment mark.

Abstract: An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.