Abstract: A high-voltage device. A substrate has a first conductive type. A first well region with the first conductive type is located in the substrate. A second well region with the second conductive type is located in the substrate but is isolated from the first well region. Several field oxide layers are located on a surface of the second well region. A shallow trench isolation is located between the field oxide layers in the second well region. A first doped region with the second conductive type is located beneath the field oxide layers. A second doped region with the first conductive type is located beneath the shallow trench isolation in the second well region. A third well region with the first conductive type is located in the first well region and expands from a surface of the first well region into the first well region. A gate structure is positioned on the substrate between the first and the second well regions and covers a portion of the first, the third well regions and the field oxide layers.

Abstract: An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P+ buried layers 8601 and 8602 on opposite sides of N+ buried layer 8605. Analog devices are formed behind one diode moat; digital CMOS devices are formed behind the other moat.

Abstract: For fabricating a field effect transistor within an active device area of a semiconductor substrate, a gate dielectric is formed on the active device area of the semiconductor substrate, and a gate structure is formed on the gate dielectric with the gate structure being comprised of a first conductive material. A drain spacer comprised of a second conductive material is formed on a first sidewall of the gate structure, and a first liner dielectric is formed between the drain spacer and the first sidewall of the gate structure and between the drain spacer and the semiconductor substrate. A source spacer comprised of the second conductive material is formed on a second sidewall of the gate structure, and a second liner dielectric is formed between the source spacer and the second sidewall of the gate structure and between the source spacer and the semiconductor substrate.

Abstract: The first insulating film (81) and the second insulating film (82) are so layered in this order on a SOI layer (3) as to cover a gate electrode (6) and a side wall (5) and dry-etched with different etching selection ratio (the etching rate of the second insulating film (82) is larger). After that, an exposed portion of the first insulating film (81) is removed by wet etching. Through these steps, a silicide protection portion (8) is formed only on a flat surface (3S) of the SOI layer (3) and silicide layers (71 and 72) are formed in n+ layers (12 and 13). With this structure, it is possible to prevent etching of the SOI layer in formation of an SiO2 film for silicide protection.

Abstract: A method of forming a temporary overhang structure to shield the source/drain edges near the gate electrode from the deposition of silicidation metal is provided. The growth of silicide on the source/drain regions remains controlled, without the presence of silicidation metal on the gate electrode sidewalls near the source/drain edges. The resulting silicide layer does not have edge growths interfering with the source/drain junction areas. The overhang structure is formed by covering the gate electrode with two insulators having differing etch selectivities. The top insulator is anisotropically etched so that only the top insulator covering the gate electrode vertical sidewalls remains. The exposed bottom insulator is isotropically etched to form a gap between the top insulator and the source/drain region surfaces. When silicidation metal is deposited, the gap prevents the deposition of metal between the gate electrode and the source/drain region surfaces.

Abstract: A method and structure for preventing device leakage. The method and structure includes forming a blocking layer of preferably nitride over a junction between a source/drain region and a shallow trench isolation. A silicide is then formed over a landed area of the source/drain region but is blocked by the blocking layer from forming over the junction between the source/drain region and the shallow trench isolation. This prevents device leakage at this location.

Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.

Abstract: An MIS transistor fabricated in a manner that minimizes the occurrence of leak currents and that improves overall transistor performance by minimizing variation in location of the transistor source and drain during fabrication thereof. A gate electrode is first fabricated on a substrate. Next, a thermal oxide layer is formed on a side of the gate electrode. A masking process is then performed with the thermal oxide layer to form a source and a drain. A silicon oxide layer is then deposited over the gate electrode, the source and the drain. An etching process is performed on the silicon oxide to form a side wall oxide film over the thermal oxide layer on the side of the gate electrode and to expose surfaces of the gate electrode, the source and the drain. A metal film is then deposited over the gate electrode, the source and the drain and is heat treated to form a metal silicide film on the exposed surfaces of the gate electrode, the source and the drain.

Abstract: Conventionally, an insulating film for element isolation has had a uniformly large thickness either in a memory cell area and in a peripheral circuit area so that the total film thickness of the memory cell area having a floating gate electrode, a control gate electrode, and an erase gate electrode is extremely increased, resulting in a large height difference between the memory cell area and the peripheral circuit area. The insulating film for element isolation in the peripheral circuit area should be thick, while the insulating films for element isolation in the memory cell area need not be as thick as the insulating film for element isolation in the peripheral circuit area in terms of operation.

Abstract: An object of the present invention is to provide a semiconductor apparatus and a method of manufacturing the same, in which dispersion of a threshold voltage Vth of a transistor at every transistor is reduced to remove generation of fixed charges in a gate insulation film and a surface level to stabilize the operation of the semiconductor apparatus. A semiconductor apparatus having a MIS transistor (1), wherein a gate electrode (4) of said MIS transistor (1), which mainly contributes to the operation of a circuit, is continuously formed to a position above a bypass film (8) made of an insulation film through which a leak current is able to easily flow as compared with a gate insulation film (7) of said MIS transistor (1) under the same voltage.

Abstract: Self-aligned contacts to the source and drain regions of a MOS device are formed by selectively removing portions of sidewall spacers from polysilicon source and drain electrodes. Metal silicide layers are then formed in contact with the exposed polysilicon portions and extending over and in contact with respective source and drain regions formed in a semiconductor substrate surface.

Abstract: A high-voltage device. A first well region with a first conductive type is located in a substrate. A second well region with the second conductive type is located in the substrate but is isolated from the first well region. Several field oxide layers are located on a surface of the second well region. A shallow trench isolation is located between the field oxide layers in the second well region. A first doped region with the second conductive type is located beneath the field oxide layers. A second doped region with the first conductive type is located beneath the shallow trench isolation in the second well region. A third well region with the first conductive type is located in the first well region and expands from a surface of the first well region into the first well region. A gate structure is positioned on the substrate between the first and the second well regions and covers a portion of the first, the third well regions and the field oxide layers.

Abstract: This is a method of forming an SRAM transistor cell on a well in a doped semiconductor substrate. Form a gate oxide layer and a split gate layer with buried contact regions in the well and openings through the split gate layer and the gate oxide layer to the well. Form an intermediate conductor layer and a hard silicon oxide mask layer and define gate conductors. Form lightly doped source/drain regions, form spacers and source/drain regions in the well. Form a first inter-conductor dielectric layer on the cell. Define a self-aligned contact region in the cell above source/drain regions. Form a second conductor layer over the cell and patterning the second conductor layer to form a via in the self-aligned contact region. Form a second inter-conductor dielectric layer on the cell, a third conductor layer over the cell and patterning the third conductor layer to form a first resistor connected to the self-aligned contact region.

Abstract: An ESD protection circuit with buried diffusion and internal overlap coupling capacitance is used to lower trigger voltage and create a compact protection circuit area. This protection circuit can be applied to memory and logic products and can be employed in power bus, input, and output pins to protect against ESD. The manufacturing process of this high-performance protection circuit is compatible with non-volatile memory process without an additional mask layer step.

Abstract: A MOS transistor for high-speed operation includes a gate insulator formed over a semiconductor substrate and a gate formed over the gate insulator. An insulating layer is formed on both sides of the gate insulator at the edge of the gate and thicker than the gate insulator. The device is also formed with LDD regions which form an LDD structure in the semiconductor substrate at least partially under the gate. The LDD structure defines a channel region under the gate insulator between the LDD regions. In one embodiment, the insulating layer formed on both sides of the gate extends toward the channel region but not beyond the LDD regions. In another embodiment, the insulating layer does extend beyond the LDD region but for a distance of less than 10 nm.

Abstract: A thin film transistor for an antistatic circuit includes: wells formed on a silicon substrate; insulating layers for electrical isolation between electrodes formed within the wells; low density impurity diffused regions respectively interposed between the insulating layers; a first high-density impurity diffused region formed within one low-density impurity diffused region; a second high-density impurity diffused region formed within the other low-density impurity diffused region; interlevel insulating layers formed on the insulating layers and the low-density impurity diffused layers; and metal gate electrodes formed on the low-density impurity diffused layers and the interlevel insulating layers; at least one of the first high-density impurity diffused region and the second high-density impurity diffused region being arranged to overlap on active region, inward from outside edges of the active region.

Abstract: A bi-directional high-voltage RESURF EDMOS (REduced SURface Extended Drain MOS) transistor which can endure a high voltage at its source by providing drift regions at both sides, i.e., the source and drain of the conventional RESURF LDMOS (Lateral DMOS) transistor, and exchanging the drain and the source when an analog signal of high voltage is inputted. Further, the bi-directional high-voltage RESURF EDMOS transistor provides a high-voltage analog multiplexer circuit employing a RESURF EDMOS transistor which is capable of reducing the number of necessary high-voltage elements and performing a stable operation, by constructing a high-voltage analog multiplexer having at least three inputs and a multistage high-voltage multiplexer circuit of push-pull type, pass transistor type, and combined form of push-pull type and pass transistor type by using the bi-directional high-voltage RESURF EDMOS transistor.

Abstract: A process for making a MOS transistor. The transistor includes a source, a channel and drain formed on a portion of silicon film in a silicon-on-insulator type structure. A field insulation layer surrounds the film. A grid structure with insulated flanks is formed above the channel. Source and drain contacts are formed on the portion of the silicon film between the field insulation layer and the grid structure. The source and drain contacts are self-aligned on the grid structure and the field insulation layer is placed directly adjacent to the grid structure.

Abstract: A semiconductor device comprising:a silicon substrate having a primary plane;an insulation film formed on the primary plane of the silicon substrate by subjecting the silicon substrate to thermal oxidation in an atmosphere of a gas of N.sub.2 O or a mixing gas of N.sub.2 O and O.sub.2 ; andan electrode formed on the insulation film and having nitrogen and a p-type dopant added therein.

Abstract: A method of fabricating a semiconductor device includes the steps of providing a semiconductor chip (10) with a memory area (22) and a logic area (26). The memory area (22) and the logic area (26) each have gate structures (50) formed therein. The step of sequentially forming silicided junctions (44) in the logic area (26) and implanted junctions in the memory area (26) is also included.

Abstract: A structure of high voltage semiconductor devices having N-well 1 and N-well 2 formed with two different doping densities acting as a gradient doping of a drift region. This structure results in a lift in its current drive capability and as well as in its breakdown voltage. The structure further comprises a buried spacer oxide, serving as a point of exertion for the edges of the buried gate electrode. And finally, since the gate electrode is formed by a trenching method, not only is the channel length increased with the placement of both the channel and drift regions changes in the to vertical direction, all of those contribute to a great reduction in the occupied chip area.

Abstract: A method of manufacturing a thin film resistor layer. A first insulating layer is formed on a substrate, wherein the substrate has at least a device previously formed therein. A thin film resistor layer is formed on the first insulating layer. A second insulating layer is formed on the thin film resistor layer. The second insulating layer and the thin film resistor layer are patterned. A third insulating layer is formed on the first insulating layer and the patterned second insulating layer. An anisotropic etching step is performed to form a first opening penetrating through the third and the first insulating layers and to form a second and a third openings penetrating through the third insulating layer, simultaneously. A self-aligned etching step is performed to expose a portion of the thin film resistor layer through the second and the third openings. The second and the third openings are filled with a conductive material to form interconnects on the third insulating layer.

Abstract: A photoresist pattern is formed on a field oxide film and an element forming region across the field oxide film and the element forming region such that a portion of a surface of the field oxide film and a portion of a surface of a silicon epitaxial layer are continuously exposed. The photoresist pattern is used as a mask to inject boron ions into the silicon epitaxial layer and heat treatment is performed thereon to form an external base containing the relatively significant crystal defect present in the silicon epitaxial layer in the vicinity of the field oxide film. Thus, a semiconductor device can be obtained including a bipolar transistor which provides improved breakdown voltage between the collector and the base and contemplates reduction of current leakage.

Abstract: An ink replenishment kit and method for an inkjet printer includes a replaceable ink supply module providing replenishment of an inkjet printhead. The module includes a collapsible bag, an enclosure box, a connective tube, and an on/off valve. These four components are incorporated into a composite sealed system which remains intact during shipment, storage, installation and operation. A coupler is provided to securely attach a print cartridge inlet with the on/off valve to hold them together in an open position allowing ink to be replenished into the print cartridge from the collapsible bag.

Abstract: A structure and method for forming a metal oxide semiconductor field effect transistor structure comprises, a substrate having a gate-channel region and source and drain regions adjacent the gate-channel region, a gate insulator over the substrate, a central gate conductor positioned above the gate-channel region and over the gate insulator and outer gate conductors over the gate insulator and adjacent the central gate conductor, wherein the gate insulator has a first thickness under the central gate conductor and a second thickness greater than the first thickness under the outer gate conductors. The center and outer gate conductors may consist of different material types (i.e., different work functions). The polarity of the source-drain doping is independent of the polarity of the central or outer gate conductors.

Abstract: A MOSFET includes a semiconductor substrate of a first conductivity type including a field region and an active region; a gate insulating film on a portion of the active region, the gate insulating film having two edge parts and a mid-part, the two edge parts being thicker than the mid-part; a gate electrode on the gate insulating film; sidewall spacers on the sides of the gate electrode and the gate insulating film; heavily doped regions of a second conductivity type in the semiconductor substrate under the two edge parts of the gate insulating film; normally doped regions of the second conductivity type in the semiconductor substrate on both sides of the gate insulating film; lightly doped regions of the second conductivity type in the semiconductor substrate on the sides of the sidewall spacers; and doped regions of the first conductivity type below the normally doped region of the second conductivity type under the sidewall spacers.

Abstract: An integrated circuit and a method of making a transistor thereof are provided. The integrated circuit includes a substrate and a plurality of transistors positioned on a plurality of active areas. Each of the transistors has a gate dielectric layer with a V-shaped cross-section positioned on one of the plurality of active areas, a gate electrode positioned on the gate dielectric layer, a first source/drain region positioned in the substrate, and a second source/drain region positioned in the substrate in spaced-apart relation to the first source/drain region to define a channel region beneath the gate dielectric layer. The V-shaped gate dielectric layer requires less horizontal substrate area, enabling higher packing density for a given substrate.

Abstract: A semiconductor device (10) of the present invention has a gate (32) insulatively disposed above the substrate, source and drain regions (36, 38) disposed near the surface in the substrate adjacent opposite sides of the gate (32), and a field oxide region (26) disposed in the surface of the substrate surrounding the source and drain regions (36, 38) and defining an active moat region (20). The channel stop region (24) is disposed below the field oxide region (26) and is spaced from the active moat region (20) with a predetermined spacing.

Abstract: A method for forming a sub-quarter micron MOSFET having an LDD structure is described. An active area is provided in a semiconductor substrate separated from other active areas by isolation regions. Ions are implanted into the semiconductor substrate in the active area wherein a heavily doped region is formed adjacent to the surface of the semiconductor substrate and wherein a lightly doped region is formed underlying the heavily doped region. A first dielectric layer is deposited overlying the semiconductor substrate in the active area. The first dielectric layer is etched away to form an opening to the semiconductor substrate. The semiconductor substrate within the opening is etched through to form a partial trench in the semiconductor substrate. Spacers are formed on the sidewalls of the first dielectric layer within the opening. A layer of conducting material is deposited over the first dielectric layer and the spacers and within the opening.

Abstract: Field effect transistors having tapered gate electrodes include a body region of first conductivity type extending to a surface of a semiconductor substrate. Source and drain regions of second conductivity type are formed in the substrate and a gate electrode is formed on a portion of the surface extending opposite the body region and between the source and drain regions. A gate electrode insulating layer is also disposed between the gate electrode and the surface. To improve the transistor's withstand voltage capability by reducing field crowding, the gate electrode insulating layer is preferably formed to have a tapered thickness which increases in a direction from the source region to the drain region, and to reduce on-state resistance the drain region is formed in a self-aligned manner to the gate electrode.

Abstract: A shallow junction MOS transistor comprising a semiconductor substrate having an upper region that includes a first and a second lightly doped region laterally displaced on either side of the channel region. The first and second lightly doped regions extend to a junction depth below the upper surface of the semiconductor substrate. A first and a second lightly doped impurity distribution are located within the first and second source/drain regions of the semiconductor substrate. The shallow junction transistor further includes a gate dielectric formed on an upper surface of the channel region of the semiconductor substrate. A conductive gate that includes a first and a second sidewall is formed on the gate dielectric. A gate insulator is formed in contact with the first and second sidewalls of the conductive gate. First and second source/drain structures are formed above the upper surface of the semiconductor substrate.

Abstract: A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate is provided. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure, preferably through the use of an ion implantation into a tilted or inclined substrate. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. The presence of the oxygen bearing species in the proximal portions of the semiconductor substrate increases the oxidation rate of the proximal portions relative to the oxidation rate of portions of the substrate that are distal to the isolation structures. In this manner, a first thickness of the gate dielectric over the proximal portions of the semiconductor substrate is greater than a second thickness of the gate oxide layer over remaining portions of the semiconductor substrate.

Abstract: Arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates by advantageously reducing the height of the floating gates in particular locations. The reduced height floating gate's topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.

Abstract: A semiconductor apparatus formed on a semiconductor substrate includes a first active region in the substrate, and a second active region adjacent to the surface of the substrate separated from the first active region by a channel region. A gate oxide region may overlie at least a portion of the first and second active regions. The apparatus further includes a gate positioned over the channel region and having a first end and a second end respectively associated with the first and second active regions. The gate includes a first low conductive region and a second low conduction region at said first and second ends, respectively.A method for making the transistor structure of the present invention is also provided.

Abstract: A resurf structure is provided which includes an n type diffusion region surrounded by a n- diffusion region, in which a part of the joined combination of the n type diffusion region and the n- diffusion region is separated by a narrow p- substrate region in between. An aluminum lead is provided between the separated n- diffusion regions, and a signal is level shifted. A high voltage semiconductor device which includes a small area high voltage isolation region is obtained without process cost increase.

Abstract: CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a single step. Further, gates for both NMOS and PMOS devices are doped with n-type dopant and NMOS gates are self-aligned.

Abstract: A MIS type field effect transistor has a source/drain region overlain by a titanium silicide layer contiguous to an upper silicon nitride layer of a buried isolating structure embedded into a silicon substrate, and a contact hole is formed in an inter-level insulating layer of silicon oxide exposing a part of the upper silicon nitride layer and a part of the titanium silicide layer into the contact hole; while the inter-level insulating layer is being selectively etched so as to form the contact hole, the upper silicon nitride layer serves as an etching stopper, and the contact hole never reaches the silicon substrate beneath the buried isolating structure.

Abstract: A MOS transistor array structure for an electro-static discharge protection circuit in a semiconductor integrated circuit device, having dispersed parallel discharge paths. The MOS transistor array includes an n-well formed in a silicon substrate of the fabricated semiconductor device. A first dispersed drain region is formed in the n-well, and a source region is formed in the silicon substrate. A second dispersed drain region is formed in both the silicon substrate and the n-well. A gate of the transistor array is formed on the silicon substrate, and a first field oxide region is distributed at least partially in the dispersed drain region, so as to improve the even distribution of electric current in the event of an electro-static discharge. The transistor structure is compatible with a silicided process of device fabrication for fast device operation. Fabrication of the structure does not require additional procedural steps for achieving this compatibility.

Abstract: An MOS transistor comprises a semiconductor substrate having a field region; a gate electrode formed on the semiconductor substrate through the intermediatry of a gate insulating film; and source/drain regions formed in the semiconductor substrate; wherein the field region including at least a lower insulating film and an upper insulating film made of a material permitting the upper insulating film to be selectively etched with respect to the lower insulating film; the gate electrode being configured such that the gate length of a top surface thereof is greater than the gate length of a bottom surface thereof facing a channel region positioned between the source/drain regions; the gate electrode having a sidewall spacer formed of a sidewall insulating layer made of the lower insulating film and a material permitting the sidewall insulating layer to be selectively etched with respect to the upper insulating film, the sidewall spacer contacting a side wall of the gate electrode for covering an outer periphery o

Abstract: A power MOSFET having a groove for forming a channel improved for shortening the switching time and increasing the dielectric breakdown strength of the gate oxide film is disclosed. The power MOSFET includes a concave structure in which a gate oxide film at a groove bottom is thickened. Namely, since the gate oxide film between a gate electrode and a first conductivity type semiconductor layer is thick, the capacitance of the oxide film therebetween is reduced. Therefore, the input and output capacitance of the gate oxide film can be reduced, and switching loss can be also reduced since the switching time can be shortened. Further, greater dielectric breakdown strength of the gate oxide film can be obtained as a result of the thickened gate oxide film at the groove bottom.

Abstract: A thick oxide layer is formed over a drain region of an MOS transistor while a thin oxide layer is provided over the source and channel regions. As a result both improved current driving ability and reduced gate induced drain leakage current are achieved.

Abstract: MOSFET having a fine gate structure comprises a semiconductor substrate of a first conductivity type, source and drain regions of a second conductivity type formed in the semiconductor substrate to define a channel region therebetween, a first insulating film provided over the source region, a second insulating film formed over the first insulating film to provide a side wall, a gate insulating film provided on the semiconductor substrate to cover the channel region, and a gate electrode provided over the gate insulating film to extend to the second insulating film and to cover the side wall. In the structure, the gate electrode is provided to have a thickness for defining an effective channel length at the side wall of the second insulating film.

Abstract: A method for fabricating a gate-to-drain overlapped MOS transistor in which gate-to-drain capacitance is lower and a structure thereby. A pad oxide layer is formed over a substrate having a first conductive layer with a first pattern formed on a first gate oxide layer, and etchback process is performed until surface part and a predetermined upper parts of the both side walls of the first conductive layer is exposed. As a result, a second conductive layers with a second pattern is formed and a second gate oxide layer thicker than the first gate oxide layer is formed.

Abstract: A high voltage PMOS or NMOS transistor 7 has improved on-resistance by truncating gate field oxide 43 so that drain region 42 may be implanted closer to channel region 49 than possible otherwise. By shortening the physical distance d2 between drain 42 and channel region 49, the drain to source on-resistance of the high voltage device is reduced and the performance of high voltage device 7 is thereby improved.

Abstract: A high voltage PMOS or NMOS transistor 7 has improved on-resistance by truncating gate field oxide 43 so that drain region 42 may be implanted closer to channel region 49 than possible otherwise. By shortening the physical distance d2 between drain 42 and channel region 49, the drain to source on-resistance of the high voltage device is reduced and the performance of high voltage device 7 is thereby improved.

Abstract: Region forming steps or interconnect-forming steps through which low voltage CMOS devices are formed in a semiconductor wafer are also employed to simultaneously form one or more regions or layers at selected sites of a substrate where high voltage devices are to be formed. Such selective modification of an already existing mask set designed for low voltage CMOS typography allows additional doping of the substrate or provision of further overlay material to accommodate the effects of high voltage operation of selected areas of the wafer and thereby effectively performs precursor tailoring or modification of those portions of the wafer where a high voltage condition will be encountered.

Abstract: A semiconductor integrated circuit device comprises a complementary inverter implemented by a series combination of a p-channel enhancement type switching transistor and an n-channel enhancement type switching transistor, and a multi-level wiring structure coupled between the drain nodes of the two switching transistors and a capacitive load, wherein the multi-level wiring structure comprises a lower level wiring strip coupled at both ends thereof with the drain nodes through two sets of contact holes, and an upper level wiring strip coupled at both ends thereof with the lower level wiring strip through two contact holes so that both charge and discharge currents bi-directionally flow the upper and lower wiring strips, thereby enhancing the resistance against electro-migration.

Abstract: An insulated gate semiconductor device (10) having a pseudo-stepped channel region (20B) between two P-N junctions (21B and 22B). The pseudo-stepped channel region (20B) is comprised of an enhancement mode portion (26B) and a depletion mode portion (28B), the enhancement mode portion (26B) being more heavily doped than the depletion mode portion (28B). One P-N junction (21B) is formed at an interface between a source region (18B) and the enhancement mode portion (26B). The enhancement mode portion (26B) has a substantially constant doping profile, thus slight variations in the placement of the source region (18B) within the enhancement region (26B) do not result in significant variations in the threshold voltage of the insulated gate semiconductor device (10). The insulated gate semiconductor device (10) is well suited for the design of low voltage circuits because of the small variations of the threshold voltage.

Abstract: A CMOS memory cell array and a method of forming it, which avoids problems caused by field oxide corner-rounding. A moat pattern defines alternating columns of active areas and field oxide regions. A source line pattern defines rows of source lines. Silicon dopant is implanted in areas not covered by the source line pattern to form buried n+ source lines. The field oxide regions are formed in areas not covered by the moat pattern. Subsequent fabrication steps may be in accordance with conventional CMOS fabrication techniques.

Abstract: Ions of dopant are implanted into predetermined locations in a doped semiconductor substrate in sufficient concentration to form a buried conductor regions. A thick dielectriv layer overlies the surface of the doped substrate. A first polysilicon layer is formed and patterned on the silicon dioxide layer by a mask and etching to form conductor lines, covered by a dielectric. A second polysilicon layer is formed on the second dielectric layer and patterned to form a first capacitor plate. A third dielectric layer is formed on the surface of the second polysilicon layer. A third polysilicon layer is formed on the third dielectric layer and patterned to form a top capacitor plate. A layer of BPSG is deposited upon the third layer of polysilicon.