With Means To Reduce Parasitic Capacitance Patents (Class 257/386)
  • Patent number: 11158669
    Abstract: In one approach, an LED array uses a combination of a half cavity and straight reflective sidewalls to improve the power distribution so that more light falls within the collection angle of the projection optics. From the bottom upwards, the LEDs in the array include a reflector, a thinner p-layer and a thicker n-layer. An active region (such as quantum wells) between the p-layer and the p-layer generates light. Without additional structures, the generated light would have an isotropic distribution and not much of the light would fall within the collection angle of the projection optics. However, the bottom reflector and p-layer form a half cavity for the light emitted from the active region. This alters the angular power distribution. Straight reflective sidewalls extending from the active region upwards into the n-layer further reflect light from the altered power distribution into the collection angle of the projection optics.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: October 26, 2021
    Assignee: Tectus Corporation
    Inventors: Kwong-Hin Henry Choy, Ewelina Natalia Lucow, Paul Scott Martin
  • Patent number: 10854660
    Abstract: The present disclosure relates to a solid-state image capturing element capable of suppressing a dark current, a manufacturing method thereof, and an electronic device. Provided is a solid-state image capturing element including: a photoelectric conversion unit formed outside a semiconductor substrate; and a charge retention section that is formed in the semiconductor substrate and retains charges generated in the photoelectric conversion unit. Among surfaces of the charge retention section, a bottom surface on a side opposite to a surface of a gate side of a transistor formed in the semiconductor substrate is covered by an insulation film. The present disclosure can be applied to, for example, solid-state image capturing elements and the like.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: December 1, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Hideaki Togashi
  • Patent number: 10825721
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure laterally adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering the upper surface of the gate stack, a second insulating capping feature covering the upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from the material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: November 3, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Jyh-Huei Chen
  • Patent number: 10781534
    Abstract: The method for growing an elongate element (5), notably a wire of nanowire or microwire type, includes forming a nucleation surface (3) having at least one germination site adopting the form of a germination hollow (7) and delimited at least partly by a mask (2), the at least one germination hollow (7) being situated at a distance from the mask (2), performing nucleation of a seed (4) intended to participate in the growth of the elongate element (5) on the at least one germination hollow (7), and growing the elongate element (5) from the seed (4).
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: September 22, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Bérangère Hyot
  • Patent number: 10777650
    Abstract: The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: September 15, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Shiyu Sun, Nam Sung Kim, Bingxi Sun Wood, Naomi Yoshida, Sheng-Chin Kung, Miao Jin
  • Patent number: 10685888
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A disposable gate contacts the at least one semiconductor fin. A spacer is disposed on the at least one semiconductor fin and in contact with the disposable gate. Epitaxially grown source and drain regions are disposed at least partially within the at least one semiconductor fin. A first one of silicide and germanide is disposed on and in contact with the source region. A second one of one of silicide and germanide is disposed on and in contact with the drain region. The method includes epitaxially growing source/drain regions within a semiconductor fin. A contact metal layer contacts the source/drain regions. One of a silicide and a germanide is formed on the source/drain regions from the contact metal layer prior to removing the disposable gate.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: June 16, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Hemanth Jagannathan, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 10622245
    Abstract: A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.
    Type: Grant
    Filed: June 16, 2019
    Date of Patent: April 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Ying Hsieh, Chih-Jung Chen, Chien-Hung Chen, Chih-Yueh Li, Cheng-Pu Chiu, Shih-Min Lu, Yung-Sung Lin
  • Patent number: 10582580
    Abstract: A switch comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region, the gate electrode being configured to control a conductivity of a channel formed in the body region. The gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction. The body region is adjacent to the source region and the drain region. The switch further comprises a source contact and a body contact portion, the source contact being electrically connected to a source terminal. The body contact portion is in contact with the source contact and is electrically connected to the body region.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: March 3, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 10535771
    Abstract: A method of forming transistor devices with an air gap in the replacement gate structure is disclosed including forming a placeholder gate structure above a semiconductor material region, forming a sidewall spacer adjacent the placeholder gate structure, removing the placeholder gate structure to define a gate cavity bounded by the sidewall spacer, forming a gate insulation layer in the gate cavity, the gate insulation layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, forming a gate electrode in the gate cavity above the gate insulation layer, removing at least a portion of the second portion of the gate insulation layer to define an air gap cavity adjacent the gate electrode, and forming a first gate cap layer above the gate electrode, wherein the first gate cap layer seals an upper end of the air gap cavity.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: January 14, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Laertis Economikos, Shesh Mani Pandey, Hui Zang, Haiting Wang, Jinping Liu
  • Patent number: 10505009
    Abstract: A semiconductor device includes a field insulating film including a first region and a second region on a substrate, a recess in the first region of the field insulating film, a gate electrode on the second region of the field insulating film, and a gate spacer along a sidewall of the gate electrode and a sidewall of the recess.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: December 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Kwan Yu, Kyung Ho Kim, Dong Suk Shin
  • Patent number: 10483375
    Abstract: A method for fabricating a semiconductor device including a vertical transistor includes forming a fin structure from a substrate. The fin structure includes a fin. The method further includes forming a bottom source/drain region on the substrate adjacent to the fin, etching a longitudinal end portion of the fin to create a gap exposing the substrate, forming a gate and a top source/drain region, and forming a contact wrapping around a horizontal portion and a vertical portion of the bottom source/drain region in a region including a location where the longitudinal end portion of the fin was removed by the etching.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Coporation
    Inventors: Wenyu Xu, Chen Zhang, Kangguo Cheng, Xin Miao
  • Patent number: 10388770
    Abstract: One illustrative IC product disclosed herein includes a transistor device including a gate structure positioned above an active region, first and second conductive source/drain structures positioned adjacent opposite sidewalls of the gate structure and an insulating material positioned laterally between the gate structure and each of the first and second conductive source/drain structures. The product also includes first and second air gaps positioned adjacent opposite sidewalls of the gate structure, a gate contact structure that is positioned entirely above the active region and conductively coupled to the gate structure and a source/drain contact structure that is positioned entirely above the active region and conductively coupled to at least one of the first and second conductive source/drain structures.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Chanro Park, Christopher M. Prindle
  • Patent number: 10283603
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a first semiconductor fin that extends from a substrate. The first semiconductor fin has source and drain regions, which are separated from one another by a channel region in the first semiconductor fin. A gate overlies an upper surface and sidewalls of the channel region. A contact is coupled to the source or drain region of the first semiconductor fin, where the source or drain region includes a layer of epitaxial material with a substantially diamond-shaped cross-section. The contact surrounds the source or drain region on top and bottom surfaces of the substantially diamond-shaped cross-section. A first capping material is arranged along outer sidewalls of the first semiconductor fin under the contact. The first capping material has an uppermost surface that is spaced below a lowermost surface of the contact by a non-zero distance.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chan Syun David Yang
  • Patent number: 10269968
    Abstract: A method of manufacturing a semiconductor Fin FET includes forming a fin structure over a substrate. The fin structure includes an upper layer, part of which is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. A source and a drain are formed. The dummy gate electrode is removed so that the upper layer covered by the dummy gate dielectric layer is exposed. The upper layer of the fin structure is removed to make a recess formed by the dummy gate dielectric layer. Part of the upper layer remains at a bottom of the recess. A channel layer is formed in the recess. The dummy gate dielectric layer is removed. A gate structure is formed over the channel layer.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jen Chen, Chia-Chun Liao, Chun-Sheng Liang, Shih-Hsun Chang, Jen-Hsiang Lu
  • Patent number: 10246770
    Abstract: The present invention relates to a silicide alloy film that is formed on a substrate containing Si, the silicide alloy film including a metal M1 having a work function of 4.6 eV or more and 5.7 eV or less, a metal M2 having a work function of 2.5 eV or less and 4.0 eV or more, and Si, the silicide alloy film having a work function of 4.3 eV or more and 4.9 eV or less. Here, the metal M1 is preferably Pt, Pd, Mo, Ir, W or Ru, and the metal M2 is preferably Hf, La, Er, Ho, Er, Eu, Pr or Sm. The silicide alloy film according to the present invention is a thin-film which has excellent heat-resistance and favorable electrical property.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: April 2, 2019
    Assignees: TANAKA KIKINZOKU KOGYO K.K., TOKYO INSTITUTE OF TECHNOLOGY
    Inventors: Shunichiro Ohmi, Yasushi Masahiro
  • Patent number: 10109715
    Abstract: A semiconductor device according to an embodiment includes: a substrate having a first plane and a second plane provided on the opposite side of the first plane; a first nitride semiconductor layer provided on the first plane; source electrodes provided on the first nitride semiconductor layer; drain electrodes provided on the first nitride semiconductor layer, each of the drain electrodes provided between the source electrodes; gate electrodes provided on the first nitride semiconductor layer, each of the gate electrodes provided between each of the source electrodes and each of the drain electrodes; a first wire provided on the second plane and electrically connected to the source electrodes; a second wire electrically connected to the drain electrodes; a third wire provided on the second plane and electrically connected to the gate electrodes; and an insulating interlayer provided between the first nitride semiconductor layer and the second wire.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 23, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Kajiwara, Kentaro Ikeda, Hisashi Saito, Masahiko Kuraguchi
  • Patent number: 10014300
    Abstract: An integrated circuit device as provided herein may include a device region and an inter-device isolation region. Within the device region, a fin-type active region may protrude from a substrate, and opposite sidewalls of the fin-type active region may be covered by an inner isolation layer. An outer isolation layer may fill an outer deep trench in the inter-device isolation region. The inner isolation layer may extend away from the device region at an inner sidewall of the outer deep trench and into the inter-device isolation region. There may be multiple fin-type active regions, and trenches therebetween. The outer deep trench and the trenches between the plurality of fin-type active regions may be of different heights. The integrated circuit device and methods of manufacturing described herein may reduce a possibility that various defects or failures may occur due to an unnecessary fin-type active region remaining around the device region.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: July 3, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mirco Cantoro, Tae-yong Kwon, Jae-young Park, Dong-hoon Hwang, Han-ki Lee, So-ra You
  • Patent number: 9941352
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate stack disposed on a substrate. A gate contact is disposed in contact with an end portion of the gate stack. An air gap spacer is disposed in contact with a portion of the gate stack. The end portion of the gate stack is absent the air gap spacer. The method includes forming a gate contact in contact with a gate stack. A spacer surrounding at least a portion of the gate stack is removed after the gate contact has been formed. The removal of the spacer forms a trench surrounding the gate stack and stopping at the gate contact. An air gap spacer is formed within the trench.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 9905648
    Abstract: Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: February 27, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 9786765
    Abstract: One aspect of the disclosure provides for a method of forming a replacement gate structure. The method may include: removing a dummy gate from over a set of fins to form an opening in a dielectric layer exposing the set of fins, each fin in the set of fins being substantially separated from an adjacent fin in the set of fins via an dielectric; forming a protective cap layer within the opening over the exposed set of fins; removing a portion of the dielectric on each side of each fin in the set of fins; undercutting each fin by removing a portion of each fin in the set of fins to create a notch disposed under the protective cap layer; substantially filling each notch with an oxide; forming a gate dielectric over each fin in the set of fins; and forming a gate conductor over the gate dielectric, thereby forming the replacement gate structure.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: October 10, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Edward J. Nowak, Brent A. Anderson, Andreas Scholze
  • Patent number: 9768170
    Abstract: Fin field effect transistors (FinFETs) and method for fabricating the same are disclosed. One of the FinFETs includes a substrate, an insulator, a first gate, a second gate, an opening and a first dielectric layer. The substrate includes a first semiconductor fin, a second semiconductor fin and a trench between the first semiconductor fin and the second semiconductor fin. The insulator is disposed in the trench. The first gate is disposed on the first semiconductor fin. The second gate is disposed on the second semiconductor fin. The opening is disposed between the first gate and the second gate. The first dielectric layer is disposed in the opening to electrically insulate the first gate and the second gate, wherein the first dielectric layer includes an air gap therein.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 9640532
    Abstract: A device includes a first stacked capacitor comprising a first MOS capacitance and a first MOM capacitance, the first MOS capacitance coupled to a first node, the first node configured to receive a first bias voltage, and a second stacked capacitor comprising a second MOS capacitance and a second MOM capacitance, the second MOS capacitance coupled to the first node.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: May 2, 2017
    Assignee: Qualcomm Incorporated
    Inventor: Timothy Donald Gathman
  • Patent number: 9640441
    Abstract: An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: May 2, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ming Chen, Feng Yuan, Tsung-Lin Lee, Chih Chieh Yeh
  • Patent number: 9601575
    Abstract: A semiconductor device includes a substrate, an active fin protruding from the substrate, and an asymmetric diamond-shaped source/drain disposed on an upper surface of the active fin. The source/drain includes a first crystal growth portion and a second crystal growth portion sharing a plane with the first crystal growth portion and having a lower surface disposed at a lower level than a lower surface of the first crystal growth portion.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: March 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongki Jung, Myungil Kang, Yoonhae Kim, Kwanheum Lee
  • Patent number: 9548203
    Abstract: Provided is a semiconductor and method of manufacturing the same, and a method of forming even doping concentration of respective semiconductor device when manufacturing multiple semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable in example by using ion injected blocking pattern. Thus, the examples relate to a semiconductor and manufacture device with even doping, and high breakdown voltage obtainable as a result of such doping.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: January 17, 2017
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Young Bae Kim, Kwang Il Kim
  • Patent number: 9543190
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a buried layer in the semiconductor substrate; forming a deep well having a first conductivity type in the semiconductor substrate, wherein the deep well is disposed on the buried layer; forming a first trench structure in the deep well, wherein the first trench structure extends into the buried layer; and forming a second trench structure in the semiconductor substrate, wherein a depth of the second trench structure is larger than a depth of the buried layer.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: January 10, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Hung Kao
  • Patent number: 9514991
    Abstract: A FinFET device and a method for fabricating a FinFET device are disclosed. An exemplary method of fabricating a FINFET device includes providing a substrate including a fin structure including a plurality of fins and shallow trench isolation (STI) features between each fin of the fin structure. A first gate structure is formed over the fin structure. First gate spacers are formed on sidewalls of the first gate structure. The first gate spacers are removed while leaving portions of the first gate spacers within corners where the fin structure and the first gate structure meet. Second gate spacers are formed on sidewalls of the first gate structure. A dielectric layer is formed over the fin structure, the first gate structure, and the second gate spacers. The first gate structure and the portions of the first gate spacers are removed, thereby exposing sidewalls of the second gate spacers.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: December 6, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
  • Patent number: 9502407
    Abstract: One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: November 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 9383638
    Abstract: There is provided a method for generating a pattern. A pattern is generated by selecting a cell from a cell library including a plurality of cells, adding, to the interior of the selected cell, a second pattern different from a first pattern of the selected cell, performing a first optical proximity correction (OPC) onto the pattern of the selected cell including the first pattern and the second pattern, performing a second optical proximity correction onto a pattern of a plurality of cells in which the selected cell including first pattern and second pattern, which have been subjected to the first optical proximity correction, and another of the cells are proximately arranged and generating the pattern including the patterns of the plurality of cells which have been subjected to the second optical proximity correction.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: July 5, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroyuki Ishii
  • Patent number: 9318320
    Abstract: The present invention provides a method of manufacturing an active element substrate aimed at reducing the production costs of an interlayer insulating film made from a spin-on glass material, for example. In the method of manufacturing an active element substrate, an interlayer insulating film is formed using a printing method that employs a plate. The plate includes: a main pattern that overlaps with signal lines that enclose openings; and fine line patterns that reduce, in the widthwise direction of the signal lines, the inclination of the edges of the printed pattern printed by the main pattern.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: April 19, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Daisuke Fuse, Masaya Yamamoto, Naoki Takao
  • Patent number: 9202917
    Abstract: The present disclosure relates to a Fin field effect transistor (FinFET) device having a buried silicon germanium oxide structure configured to enhance performance of the FinFET device. In some embodiments, the FinFET device has a three-dimensional fin of semiconductor material protruding from a substrate at a position located between first and second isolation regions. A gate structure overlies the three-dimensional fin of semiconductor material. The gate structure controls the flow of charge carriers within the three-dimensional fin of semiconductor material. A buried silicon-germanium-oxide (SiGeOx) structure is disposed within the three-dimensional fin of semiconductor material at a position extending between the first and second isolation regions.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: December 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Zhiqiang Wu, Gwan Sin Chang
  • Patent number: 9054174
    Abstract: In a MOSFET using a SiC substrate, a source region having low resistance and high injection efficiency is formed without performing a high-temperature heat treatment. A vertical Schottky barrier transistor in which a source region SR on a SiC epitaxial substrate is constituted by a metal material is formed. The source region SR composed of a metal material can be brought into a low resistance state without performing a high-temperature activation treatment. Further, by segregating a conductive impurity DP at an interface between the source region SR composed of a metal material and the SiC epitaxial substrate, the Schottky barrier height can be reduced, and the carrier injection efficiency from the source region SR can be improved.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: June 9, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Digh Hisamoto, Naoki Tega, Kumiko Konishi, Hiroyuki Matsushima
  • Patent number: 9041123
    Abstract: A method and structures to achieve improved TFTs and high fill-factor pixel circuits are provided. This system relies on the fact that jet-printed lines have print accuracy, which means the location and the definition of the printed lines and dots is high. The edge of a printed line is well defined if the printing conditions are optimized. This technique utilizes the accurate definition and placement of the edges of printed lines of conductors and insulators to define small features and improved structures.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: May 26, 2015
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Jurgen H. Daniel, Ana Claudia Arias
  • Patent number: 8963240
    Abstract: This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: February 24, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Sik K. Lui
  • Patent number: 8933493
    Abstract: A semiconductor device may include a first transistor, a second transistor connected in series to the first transistor through a first junction, and a third transistor connected in series to the second transistor through a second junction. Here, a high voltage is supplied to one of the first and second junctions, and a turn-off voltage is supplied to a gate of the second transistor.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: January 13, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jae-Yong Cha
  • Patent number: 8921181
    Abstract: Methods for forming an electronic device having a fluorine-stabilized semiconductor substrate surface are disclosed. In an exemplary embodiment, a layer of a high-? dielectric material is formed together with a layer containing fluorine on a semiconductor substrate. Subsequent annealing causes the fluorine to migrate to the surface of the semiconductor (for example, silicon, germanium, or silicon-germanium). A thin interlayer of a semiconductor oxide may also be present at the semiconductor surface. The fluorine-containing layer can comprise F-containing WSix formed by ALD from WF6 and SiH4 precursor gases. A precise amount of F can be provided, sufficient to bind to substantially all of the dangling semiconductor atoms at the surface of the semiconductor substrate and sufficient to displace substantially all of the hydrogen atoms present at the surface of the semiconductor substrate.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 30, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Dipankar Pramanik
  • Patent number: 8896034
    Abstract: Radio frequency and microwave devices and methods of use are provided herein. According to some embodiments, the present technology may comprise an ohmic layer for use in a field effect transistor that includes a plurality of strips disposed on a substrate, the plurality of strips comprising alternating source strips and drain strips, with adjacent strips being spaced apart from one another to form a series of channels, a gate finger segment disposed in each of the series of channels, and a plurality of gate finger pads disposed in an alternating pattern around a periphery of the plurality of strips such that each gate finger segment is associated with two gate finger pads.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: November 25, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8889022
    Abstract: One illustrative method disclosed herein includes forming a structure above a semiconductor substrate, performing a conformal deposition process to form a layer of undoped spacer material above the structure, performing an angled ion implant process to form a region of doped spacer material in the layer of undoped spacer material while leaving other portions of the layer of undoped spacer material undoped, and, after performing the angled ion implant process, performing at least one etching process that removes the undoped portions of the layer of undoped spacer material and thereby results in a sidewall spacer comprised of the doped spacer material positioned adjacent at least one side, but not all sides, of the structure.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: November 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hans-Peter Moll, Joachim Patzer
  • Publication number: 20140332898
    Abstract: A fanout line structure of an array substrate includes a plurality of fanout lines arranged on a fanout area of the array substrate, where resistance value of the fanout line is dependent on length of the fanout line. Each of the fanout lines comprises a first conducting film. Resistance values of a first part of fanout lines are less than resistance values of a second part of the fanout lines, and the first part of fanout lines are covered by an additional conducting film. In the fanout lines covered by the additional conducting film, as the resistance value of the fanout line, increases, area of the additional conducting film covering the fanout line correspondingly decreases. An additional capacitor is generated between the additional conducting film and the first conducting film.
    Type: Application
    Filed: June 28, 2013
    Publication date: November 13, 2014
    Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD
    Inventor: Peng Du
  • Patent number: 8872274
    Abstract: An upside-down p-FET is provided on a donor substrate. The upside-down p-FET includes: self-terminating e-SiGe source and drain regions; a cap of self-aligning silicide/germanide over the e-SiGe source and drain regions; a silicon channel region connecting the e-SiGe source and drain regions; buried oxide above the silicon channel region; and a gate controlling current flow from the e-SiGe source region to the e-SiGe drain region.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Guy M Cohen, David J Frank, Isaac Lauer
  • Patent number: 8847401
    Abstract: Disclosed is a semiconductor structure incorporating a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure. The structure comprises a semiconductor device (e.g., a two-terminal device, such as a PN junction diode or Schottky diode, or a three-terminal device, such as a field effect transistor (FET), a bipolar junction transistor (BJT), etc.) and a dielectric layer that covers the semiconductor device. A contact extends vertically through the dielectric layer to a terminal of the semiconductor device (e.g., in the case of a FET, to a source/drain region of the FET). A contact sidewall spacer is positioned on the contact sidewall and incorporates an airgap. Since air has a lower dielectric constant than other typically used dielectric spacer or interlayer dielectric materials, the contact size can be increased for reduced parasitic resistance while minimizing corresponding increases in parasitic capacitance or the probability of shorts.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Fen Chen, Jeffrey P. Gambino, Zhong-Xiang He, Xin Wang, Yanfeng Wang
  • Patent number: 8828862
    Abstract: A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: David V. Horak, Elbert Huang, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Publication number: 20140246731
    Abstract: An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric.
    Type: Application
    Filed: May 12, 2014
    Publication date: September 4, 2014
    Inventors: Hung-Ming Chen, Feng Yuan, Tsung-Lin Lee, Chih Chieh Yeh
  • Patent number: 8815660
    Abstract: The present invention generally relates to a semiconductor structure and method, and more specifically, to a structure and method for reducing floating body effect of silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). An integrated circuit (IC) structure includes a SOI substrate and at least one MOSFET formed on the SOI substrate. Additionally, the IC structure includes an asymmetrical source-drain junction in the at least one MOSFET by damaging a pn junction to reduce floating body effects of the at least one MOSFET.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Qingqing Liang, Huilong Zhu, Zhijiong Luo, Haizhou Yin
  • Patent number: 8809962
    Abstract: Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO2 or low-k dielectric sidewall spacer. Embodiments include transistors comprising a trench silicide layer spaced apart from a replacement metal gate electrode, and a layer of SiO2 or low-k material on a side surface of the replacement metal gate electrode facing the trench silicide layer. Implementing methodologies may include forming an intermediate structure comprising a removable gate with nitride spacers, removing the removable gate, forming a layer of high-k material on the nitride spacers, forming a layer of metal nitride on the high-k material, filling the opening with insulating material and then removing a portion thereof to form a recess, removing the metal nitride layers and layers of high-k material, depositing a layer of SiO2 or low-k material, and forming a replacement metal gate in the remaining recess.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: August 19, 2014
    Assignees: GlobalFoundries Inc., GlobalFoundries Singapore Pte. Ltd., International Business Machines Corporation
    Inventors: Yanxiang Liu, Jinping Liu, Min Dai, Xiaodong Yang
  • Patent number: 8803240
    Abstract: The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: August 12, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Kunal R. Parekh
  • Patent number: 8796802
    Abstract: Semiconductor photodetectors are provided that may enable optimized usage of an active detector array. The semiconductor photodetectors may have a structure that can be produced and/or configured as simply as possible. A radiation detector system is also provided.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: August 5, 2014
    Assignee: First Sensor AG
    Inventors: Michael Pierschel, Frank Kudella
  • Patent number: 8772101
    Abstract: One method includes forming first sidewall spacers adjacent opposite sides of a sacrificial gate structure and a gate cap layer, removing the gate cap layer and a portion of the first sidewall spacers to define reduced-height first sidewall spacers, forming second sidewall spacers, removing the sacrificial gate structure to thereby define a gate cavity, whereby a portion of the gate cavity is laterally defined by the second sidewall spacers, and forming a replacement gate structure in the gate cavity, wherein at least a first portion of the replacement gate structure is positioned between the second sidewall spacers. A device includes a gate structure positioned above the substrate between first and second spaced-apart portions of a layer of insulating material and a plurality of first sidewall spacers, each of which are positioned between the gate structure and on one of the first and second portions of the layer of insulating material.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: July 8, 2014
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ruilong Xie, Ponoth Shom, Cho Jin, Charan Veera Venkata Satya Surisetty
  • Publication number: 20140167178
    Abstract: A semiconductor device includes a non-conductive gate feature over a substrate and a spacer adjoining each sidewall of the non-conductive gate feature.
    Type: Application
    Filed: February 25, 2014
    Publication date: June 19, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Chieh TSAI, Yung-Che Albert SHIH, Jhy-Kang TING
  • Patent number: 8735999
    Abstract: In one embodiment, a semiconductor device includes a substrate, and a gate electrode provided on the substrate via a gate insulator. The device further includes a source region of a first conductivity type and a drain region of a second conductivity type provided in the substrate to sandwich the gate electrode, and a channel region provided between the source and drain regions in the substrate. The gate insulator includes a first insulator portion having a first edge which is positioned on the source region and is parallel to a channel-width direction, and a second edge which is positioned on the channel or source region and is parallel to the channel-width direction, and having a first thickness. The gate insulator further includes a second insulator portion positioned on a drain region side with respect to the first insulator portion, and having a second thickness greater than the first thickness.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: May 27, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuya Ohguro