Abstract: In a fabrication method of a semiconductor device including a plurality of silicon-based transistors or capacitors, there exist hydrogen at least in a part of a silicon surface in advance, and the hydrogen is removed by exposing the silicon surface to a first inert gas plasma. Thereafter, plasma is generated by a mixed gas of a second inert gas and one or more gaseous molecules, and a silicon compound layer containing at least a part of the elements constituting the gaseous molecules is formed on the surface of the silicon gas.

Abstract: A cellularly constructed semiconductor component has a connection electrode, which contact-connects some of the cells, and a connection line, which contact-connects the connection electrode. In which case, in a region at a distance from a connection contact between the connection line and the connection electrode, at least some of the cells are not connected to the connection electrode.

Abstract: There is provided a semiconductor device of low power consumption and high reliability having DTMOS' and substrate-bias variable transistors, and portable electronic equipment using the semiconductor device. On a semiconductor substrate (11), trilayer well regions (12, 14, 16; 13, 15, 16) are formed, and DTMOS' (29, 30) and substrate-bias variable transistors (27, 28) are provided in the shallow well regions (16, 17). Large-width device isolation regions (181, 182, 183) are provided at boundaries forming PNP, NPN or NPNP structures, where a small-width device isolation region (18) is provided on condition that well regions on both sides are of an identical conductive type. Thus, a plurality of well regions of individual conductive types where substrate-bias variable transistors (27, 28) of individual conductive types are provided can be made electrically independent of one another, allowing the power consumption to be reduced. Besides, the latch-up phenomenon can be suppressed.

Abstract: A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shifts in FETs formed in the n-well adjacent the nwell-pwell interface. The thinned mask is then removed, a p-well mask is put in place, and the remainder of the p-well implants are carried out.

Abstract: Multi-terminal electronic switching devices comprising a chalcogenide material switchable between a resistive state and a conductive state. The devices include a first terminal, a second terminal and a control terminal. Application of a control signal to the control terminal modulates the conductivity of the chalcogenide material between the first and second terminals and/or the threshold voltage required to switch the chalcogenide material between the first and second terminals from a resistive state to a conductive state. The devices may be used as interconnection devices or signal providing devices in circuits and networks.

Abstract: Gates of pMISFETs which need high current driving capability are high-driving-capability gates placed in discontinuous active regions or high-driving-capability gates disposed in two-input active regions. Gate of pMISFETs which do not need high current driving capability are normal gates arranged in continuous active regions. Since the high-driving-capability gates are provided in the discontinuous active regions or the two-input active regions, pMISFETs with high driving capability is achieved by utilizing light holes created due to a lattice distortion.

Abstract: In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same substrate, the manufacturing process is complicated in order to set the circuits to the optimum values. As a result, in association with deterioration in the yield and increase in the number of manufacturing days, the manufacturing cost increases. In order to solve the problems, according to the invention, transistors of high and low thresholds are used in a logic circuit, a memory cell uses a transistor of the same high threshold voltage and a low threshold voltage transistor, and an input/output circuit uses a transistor having the same high threshold voltage and the same concentration in a channel, and a thicker gate oxide film.

Abstract: A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, and a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the the source/drain diffusion layer regions of which is connected to the memory cell unit. The shape of the source diffusion layer region of the selection gate transistor is asymmetical to the shape of the drain diffusion layer region thereof below the selection gate transistor.

Abstract: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

Abstract: A semiconductor device has a first semiconductor element and a second semiconductor element formed on a semiconductor substrate. The second semiconductor element is operated with a first voltage. The first semiconductor element is operated with a second voltage that is higher than the first voltage. The pairs of impurity regions of the first and second semiconductor elements respectively have first impurity areas and second impurity areas. Each of the first impurity areas have a predetermined impurity concentration and a conductivity type opposite to a conductivity type of the semiconductor substrate. The second impurity areas extend toward their corresponding gates from the first impurity areas. The second impurity areas have a same conductivity type as the first impurity areas and an impurity concentration lower than the concentration of the first impurity area.

Abstract: Gate structures, comprising a first insulation film, a first gate material and a gate oxide film, are formed. A second insulation film is formed on side surfaces of the gate structures in the peripheral region. Trenches are formed at a surface of the semiconductor substrate by etching the semiconductor substrate with the first and the second insulation films used as masks. The second insulation film formed on side surface of the gate structures is removed, exposing the surface of the semiconductor substrate in the vicinity of the gate structures on both sides of the trenches. Element-isolating insulation films are formed in the trenches and on the exposed substrate. The gate structures in the peripheral region are removed. Gate structures of peripheral transistors are formed between the element-isolating insulation films in the peripheral region.

Abstract: In the semiconductor storage device, a dummy P+ diffusion region which does not contribute to a storage operation is formed in the vicinity of two P+ diffusion regions constituting a storage node. Moreover, a dummy N+ diffusion region which does not contribute to the storage operation is formed in the vicinity of N+ diffusion regions FL210 and FL220 constituting a storage node. Consequently, a part of electrons generated in a P well region PW by irradiation of ? rays or neutron rays can be collected into the dummy N+ diffusion region FL250, and a part of holes generated in an N well region NW by the irradiation of the ? rays or the neutron rays can be collected into the dummy P+ diffusion region FL150.

Abstract: A method for predetermining the initial state of the memory cells of a static random access memory such that when the memory is powered up the predetermined initial states are attained. The initial states can be predetermined by modifying one or more physical or operational parameters of the MOSFETS comprising the memory cells.

Abstract: A static random access memory (SRAM) cell is given increased stability and latch-up immunity by fabricating the PMOS load transistors of the SRAM cell to have a very low drain/source dopant concentration. The drain/source regions of the PMOS load transistors are formed entirely by a P?? blanket implant. The PMOS load transistors are masked during subsequent implant steps, such that the drain/source regions of the PMOS load transistors do not receive additional P-type (or N-type) dopant. The P?? blanket implant results in PMOS load transistors having drain/source regions with dopant concentrations of 1e17 atoms/cm3 or less. The dopant concentration of the drain/source regions of the PMOS load transistors is significantly lower than the dopant concentration of lightly doped drain/source regions in PMOS transistors used in peripheral circuitry.

Abstract: The semiconductor device includes a plurality of transistors, wherein one of the transistors that has the thinnest gate dielectric layer is selected to serve as a power source protection element, among a plurality of transistors, each having a gate dielectric layer of an independently set film thickness, disposed on a same substrate to be operated by a voltage from a same power source. Also, a threshold voltage of the transistor selected as the power source protection element is set higher than other transistor that also has the thinnest gate dielectric layer.

Abstract: An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a second high threshold voltage PMOS transistor and a second high threshold voltage NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node; wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node; a first low threshold voltage access transistor including a first S/D coupled to the first data node and to the gate of the second PMOS transistor and to the gate of the second NMOS transistor and including a second S/D coupled to a first data access node and including a gate c

Abstract: A semiconductor device has at least one high-voltage and low-voltage transistor on a single substrate. The reliability of the high-voltage transistor is enhanced by performing a LDD implantation in only the high-voltage transistor prior to conducting an oxidation process to protect the substrate and gate electrode. After the oxidation process is performed, the low-voltage transistor is subjected to an LDD implantation process. The resultant semiconductor device provides a high-voltage transistor having a deeper LDD region junction depth than the low-voltage transistor, ensuring reliability and performance.

Abstract: A high-voltage device with improved punch through voltage. A semiconductor silicon substrate has a high-voltage device region on which a gate structure is patterned. A lightly doped region is formed in the substrate and lateral to the gate structure. A spacer is formed on the sidewall of the gate structure. A heavily doped region is formed in the lightly doped region and lateral to the spacer. A lateral distance is kept between the spacer and the heavily doped region.

Abstract: An integrated circuit device is described which includes a voltage reduction circuit to reduce an externally supplied voltage using a transistor threshold drop. The transistor is fabricated in a well to isolate the transistor from the integrated circuit substrate. The transistor can be fabricated with a lower breakdown voltage level and still reduce a high voltage. The transistor can also be fabricated in the same manner as other transistors in the integrated circuit. A voltage regulator circuit is also described which incorporates the reduction circuit to allow the use of transistors which are not designed to handle an external voltage Vpp.

Abstract: Provided is a substrate identification circuit that generates a numeric value, whose duplication is difficult and which is proper to a substrate, at low cost and a semiconductor device having such a substrate identification circuit. A substrate identification circuit 304 is produced by utilizing variations in characteristics among TFTs formed on a substrate having an insulating surface. The substrate identification circuit 304 includes a plurality of proper bit generating circuits, each of which is constructed from a plurality of TFTs and outputs a one-bit random number based on variations in characteristics among the plurality of TFTs. The substrate identification circuit generates a numeric value proper to the substrate using the one-bit random number. The substrate identification circuit may include a circuit that makes a judgment by comparing the numeric value proper to the substrate with an identification number inputted from the outside.

Abstract: A source electrode Vdd is formed in a region between a field PMOS 1 and a field PMOS 2 as high side switches of a latch circuit. This latch circuit is utilized in the state where a lower side of one of the two high side switches is completely depleted. Field PMOS 1 and field PMOS 2 share a P+-type impurity diffusion region, an N+-type impurity diffusion region and a P+-type impurity diffusion region, which are connected to source electrode Vdd. It is therefore possible to provide a semiconductor device capable of reducing the area thereof in the direction parallel to the main surface of a semiconductor substrate.

Abstract: A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1 has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power supply voltage.

Abstract: A semiconductor device including a gate oxide of multiple thicknesses for multiple transistors where the gate oxide thicknesses are altered through the growth process of implanted oxygen ions into selected regions of a substrate. The implanted oxygen ions accelerate the growth of the oxide which also allow superior quality and reliability of the oxide layer, where the quality is especially important, compared to inter-metal dielectric layers. A technique has been used to vary the thickness of an oxide layer grown on a silicon wafer during oxidation growth process by implanting nitrogen into selected regions of the substrate, which the nitrogen ions retard the growth of the silicon oxide resulting in a diminished oxide quality. Therefore it is desirable to fabricate a semiconductor device with multiple thicknesses of gate oxide by the implanted oxygen ion technique.

Abstract: A semiconductor device and a manufacturing method thereof permitting the quality of gate insulating films to be prevented from deteriorating and thereby permitting electrical characteristics of the device to be prevented from deteriorating are provided. In a semiconductor device including a plurality of field effect transistors, an oxidation protection film 21 is formed on a side of one gate electrode 19.

Abstract: The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset d2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.

Abstract: Examples including non-volatile semiconductor memory devices in which digitized image data and voice data can be more efficiently written and read, and methods for manufacturing the same, are described. In one example, a non-volatile semiconductor memory device 300 may include a first memory element 100 and a second memory element 200 formed in a wafer 11 and mutually isolated by an element isolation region 38, a first impurity diffusion layer 16 and a second impurity diffusion layer 14. The first and second memory elements 100 and 200 include gate dielectric layers 20 and 120, floating gates 22 and 122, selective oxide dielectric layers 24 and 124 and third impurity diffusion layers 15 and 25, respectively, and also include a common intermediate dielectric layer 26 and a common control gate 28, and connected to the first and second impurity diffusion layers 16 and 14 that are commonly shared.

Abstract: MOS transistor cells 1 and MOS transistor cells 2 having different gate threshold voltages are formed on a chip 8. The MOS transistor cells 1, 2 having the different gate threshold voltages are connected in parallel.

Abstract: A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, and a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the the source/drain diffusion layer regions of which is connected to the memory cell unit. The shape of the source diffusion layer region of the selection gate transistor is asymmetrical to the shape of the drain diffusion layer region thereof below the selection gate transistor.

Abstract: A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects.

Abstract: In some embodiments, the invention involves a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage. Various configurations may be used including: n+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and n+ source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.

Abstract: A conductor film and a cap insulating film are sequentially formed, and a laminated film constituted of the cap insulating film and the conductor film is patterned, and then a gate electrode is formed. Next, source and drain diffusion regions are formed, and a first silicon nitride film is formed on a sidewall of the laminated film, and then a second silicon nitride film is formed on an entire surface, and further a silicon oxide film is deposited. Next, the silicon oxide film is left between the gate electrodes, and the second silicon nitride film on the laminated film is removed, and the cap insulating film left above the gate electrode is removed, and a metal silicide film is formed on a surface of the gate electrode, and then a third silicon nitride film is left on the gate electrode.

Abstract: A semiconductor element suitable for use in the display region of a liquid crystal display or for use in the drive circuit region for driving the display region is comprised of first, second, third and fourth electrodes; a pair of first conductivity type semiconductor layers separated from each other and connected to the second and the third electrodes, respectively; an intrinsic semiconductor layer connected to the pair of the first conductivity type semiconductor layers; and a second conductivity type semiconductor layer formed on the intrinsic semiconductor layer, wherein an insulating film is interposed between the first electrode and the intrinsic semiconductor layer, and the fourth electrode is formed on the second conductivity type semiconductor layer formed on the intrinsic semiconductor layer.

Abstract: Growth of multiple gate oxides. By implanting different sites of a wafer with different doses of an oxide growth retardant, the entire wafer can grow oxides of different thicknesses even after being exposed to the same oxidation environment. The process is modular insofar as the implantation of one site has no effect on rate of growth of other sites.

Abstract: A simiconductor device includes a simiconductor substrate, an insulating layer, a silicon layer, full depletion type transistors, and partial deletion type transistors. The insulating layer is formed on the simiconductor substrate. The silicon layer has a first region and a second region. The silicon layer is formed on the insulating layer. The full depletion type transistors are used for a logical circuit and are formed on the silicon layer at the first region. The partial depletion type transistors are used for a memory cell circuit and are formed on the silicon layer at the second region. The second region of the silicon layer is maintained at a fixed potential.

Abstract: The present invention includes a technique for making a dual voltage integrated circuit device. A gate dielectric layer is formed on a semiconductor substrate and a gate material layer is formed on the dielectric layer. A first region of the gate material layer is doped to a first nonzero level and a second region of the gate material level is doped to a second nonzero level greater than the first level. A first field effect transistor is defined that has a first gate formed from the first region. Also, a second field effect transistor is defined that has a second gate formed from the second region. The first transistor is operable at a gate threshold voltage greater than the second transistor in accordance with a difference between the first level and the second level.

Abstract: There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.

Abstract: First to third logic circuits and first to third static random access memories (SRAMs) are formed on one chip. Power to the first and third logic circuits and their SRAMs is shut off as required, while power to the second logic circuit and its SRAM is kept supplied. The third SRAM has the largest memory capacity. The average channel width of the first to third SRAM cell arrays is set at a half or less of that of the other circuit blocks, and the channel impurity concentration of the second and third SRAM cell arrays, which operate at low speed, is set higher than that of the first SRAM cell array, which operates at high speed, by additional ion implantation. By these settings, MOS transistors of low threshold voltage (Vt) are provided for the first SRAM cell array, while MOS transistors of high Vt are provided for the second and third SRAM cell arrays for leakage reduction.

Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

Abstract: High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.

Abstract: A method of manufacturing an integrated semiconductor device having at least one non-volatile floating gate memory cell and at least one logic transistor. The method includes growing a first gate oxide layer over a silicon substrate, depositing a first polysilicon layer over the first gate oxide layer, selectively etching and removing the first polysilicon layer in order to define the floating gate of the memory cell, introducing dopant in order to obtain source and drain regions of the memory cell, depositing a dielectric layer, selectively etching and removing the dielectric layer and the first polysilicon layer in a region wherein the logic transistor will be formed, depositing a second polysilicon layer, selectively etching and removing the second polysilicon layer in order to define the gate of the logic transistor and the control gate of the memory cell.

Abstract: A method for fabricating buried channel NMOS devices and the devices themselves are disclosed. These buried channel NMOS devices are fabricated with a p-type substrate, an n-type implant in the top portion (approximately 400 to 1000 Å deep) of the substrate, and an insulating gate dielectric above the n-type implant. An n-type or p-type doped polysilicon gate electrode is formed on top of the insulating gate dielectric. The n-type implant region is doped in such a way that it is depleted of charge carriers when the device's gate electrode is at the same potential as the well (zero bias). When the gate electrode is biased +Ve with respect to the device's well substrate a conducting channel of mobile electrons is formed in a portion of the buried layer. This type of biasing is known as inversion bias since the charge carriers are of the opposite type than the p-well.

Abstract: Systems and methods are provided for static pass transistor logic having transistors with multiple vertical gates. The multiple vertical gates are edge defined such that only a single transistor is required for multiple logic inputs. Thus a minimal surface area is required for each logic input. The novel static pass transistor of the present invention includes a transistor which has a horizontal depletion mode channel region between a single source and drain region. A number of vertical gates are located above different portions of the depletion mode channel region. At least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material. At least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material.

Abstract: The present invention includes a technique for making a dual voltage integrated circuit device. A gate dielectric layer is formed on a semiconductor substrate and a gate material layer is formed on the dielectric layer. A first region of the gate material layer is doped to a first nonzero level and a second region of the gate material level is doped to a second nonzero level greater than the first level. A first field effect transistor is defined that has a first gate formed from the first region. Also, a second field effect transistor is defined that has a second gate formed from the second region. The first transistor is operable at a gate threshold voltage greater than the second transistor in accordance with a difference between the first level and the second level.

Abstract: A semiconductor device suppressing the lateral diffusion of impurities doped in a PMOS and NMOS and shortening the distance between the PMOS and NMOS to reduce the size of the semiconductor device, including PMOS and NMOS formation regions isolated by an element isolation region; a p-type gate electrode arranged on the PMOS formation region; an n-type gate electrode arranged on the NMOS formation region; and first and second impurity storage regions arranged in a direction different from that of the arrangement of the p-type and n-type gate electrodes. An end of the first impurity storage region is connected to the p-type gate electrode, an end of the second impurity storage region is connected to the n-type gate electrode, and the other ends of the first and second impurity storage regions are electrically connected.

Abstract: Structures and methods involving non volatile depletion mode p-channel memory cells with an ultrathin tunnel oxide thicknesses, e.g. less than 50 Å, have been provided. Both the write and erase operations are performed by tunneling and method embodiments are included with the present invention. The floating gate of the depletion mode p-channel memory cell is adapted to hold a fixed charge over a limited range of floating gate potentials or electron energies. For the present invention, there is a range potentials applied to the floating gate for which there are no final nor initial states in the silicon substrate or p+ source region. In this range of potentials there can be no charge leakage, neither a gain nor a charge loss from the floating gate by tunneling or thermally assisted tunneling. In other words the potential of the floating gate can have different states and there will be no change in the charge state, due to leakage currents.

Abstract: An apparatus including a MOSFET circuit having dual threshold voltage NMOS and PMOS transistors wherein the threshold voltage of a low threshold NMOS transistor is set with a first halo implant, a threshold voltage of a high threshold voltage PMOS transistor is set with a second halo implant, and, a threshold voltage of a high threshold voltage NMOS transistor is enhanced while, a threshold voltage of a low threshold voltage PMOS transistor is compensated with a third halo implant.

Abstract: A semiconductor integrated contains a first MOS transistor of a first conductivity type formed on a surface of a semiconductor substrate, and a second MOS transistor of the first conductivity type having a drain-source breakdown voltage lower than that of the first MOS transistor. The second MOS transistor is used as an anti-fuse, which can be changed to a conductive state with a low writing voltage that does not damage the first MOS transistor. The second MOS transistor is fabricated such that a concentration of a second conductivity type impurity in at least a portion of the channel region adjacent to the drain region is higher than that in a corresponding portion of the first MOS transistor.

Abstract: A semiconductor device may be formed with a floating body positioned over an insulator in a semiconductor structure. A gate may be formed over the floating body but spaced therefrom. The semiconductor structure may include doped regions surrounding the floating body The floating body provides a distributed capacitance and resistance along its length to form an integrated RC circuit. The extent of the resistance is a function of the cross-sectional area of the floating body along the source and drain regions and its capacitance is a function of the spacing between the doped regions and the body and between the gate and the body. In some embodiments of the present invention, compensation for input voltage variations may be achieved.

Abstract: In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.