Abstract: In a high-voltage NMOS transistor with low threshold voltage, it is proposed to realize the body doping that defines the channel region in the form of a deep p-well, and to arrange an additional shallow p-doping as a channel stopper on the transistor head, wherein this additional shallow p-doping is produced in the semiconductor substrate at the end of the deep p-well that faces away from the channel region, and extends up to a location underneath a field oxide region that encloses the active window. The leakage current of the parasitic transistor at the transistor head is suppressed with the channel stopper.

Abstract: A silicon-germanium non-formation region not formed with a silicon germanium layer and a silicon-germanium formation region formed with a silicon germanium layer are provided in a silicon chip, an internal circuit and an input/output buffer are arranged in the silicon-germanium formation region, and a pad electrode and an electrostatic protection element are arranged in the silicon-germanium non-formation region.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate comprising first and second transistor regions that are isolated by an element isolation region; a first impurity diffusion suppression layer formed on the semiconductor substrate in the first transistor region; a second impurity diffusion suppression layer formed on the semiconductor substrate in the second transistor region, and having a thickness larger than that of the first impurity diffusion suppression layer; a first crystal layer formed on the first impurity diffusion suppression layer; a second crystal layer formed on the second impurity diffusion suppression layer; a first gate electrode formed on the first crystal layer via a first gate insulating film; a second gate electrode formed on the second crystal layer via a second gate insulating film; a first channel region formed in a region in the semiconductor substrate, the first impurity diffusion suppression layer and the first crystal layer below the first gate

Abstract: A semiconductor integrated circuit device with higher integration density and a method of fabricating the same are provided. The semiconductor integrated circuit device may include trench isolation regions in a semiconductor substrate that define an active region and a gate pattern that is used for a higher voltage and formed on the active region of the semiconductor substrate. Trench insulating layers may be formed in the semiconductor substrate on and around edges of the gate pattern so as to be able to relieve an electrical field from the gate pattern. The depths of each of the trench insulating layers may be defined according to an operating voltage. Source and drain regions enclose the trench insulating layers and may be formed in the semiconductor substrate on both sides of the gate pattern. Therefore, the semiconductor integrated circuit device may have a higher integration density and may relieve an electrical field from the gate pattern.

Abstract: Dual thickness devices and circuits using dual gate thickness devices. The devices include: one or more FETs of a first polarity and one or more FETs of a second and opposite polarity, the one or more FETs of the first polarity electrically connected to the one or more FETs of the second polarity in a same circuit, at least one of the one or more FETs of the first polarity having a gate dielectric consisting of a single layer of thermal silicon oxide and having a thickness different from a thickness of a gate dielectric consisting of a single layer of thermal silicon oxide of at least one of the one or more FETs of the second polarity.

Abstract: A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness, such that when a pass voltage is applied to the gate electrode of the access device, the access device and the memory device remains isolated, such that the charge stored in the memory device is unaffected by the pass voltage. The pass voltage is determined from a range of voltages, when applied to the access device, has no effect on the threshold voltage of the memory device. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings.

Abstract: A liquid crystal display is provided. A liquid crystal display includes a first substrate having color filters therewith; a second substrate having plural first signal lines and plural second signal lines thereon; plural first openings located at intersections of said first signal lines and plural of second signal lines; and plural supports located at said plural first openings and between said first substrate and said second substrate, and separating said first substrate from said second substrate.

Abstract: A semiconductor device includes a fin field effect transistor configured to include at least a first fin and a second fin. Threshold voltage of the first fin and threshold voltage of the second fin are different from each other in the fin field effect transistor.

Abstract: A dual workfunction semiconductor device and a device made thereof is disclosed. In one aspect, the device includes a first gate stack in a first region and a second gate stack in a second region. The first gate stack has a first effective workfunction, and the second gate stack has a second effective workfunction different from the first effective workfunction. The first gate stack includes a first gate dielectric capping layer, a gate dielectric host layer, a first metal gate electrode layer, a barrier metal gate electrode, a second gate dielectric capping layer, and a second metal gate electrode. The second gate stack includes a gate dielectric host layer, a first metal gate electrode, a second gate dielectric capping layer, and a second metal gate electrode.

Abstract: This invention discloses an one time programmable (OTP) memory. The OTP memory includes a first and a second metal oxide semiconductor (MOS) transistors connected in parallel and controlled by a single polysilicon stripe functioning as a gate wherein the OTP memory further includes a drift region for counter doping a lightly dope drain (LDD) encompassing and surrounding a drain and a source of the first MOS transistor having a different threshold voltage than the second MOS transistor not reached by the drift region. In a preferred embodiment, the first and second MOS transistors are N-MOS transistors disposed in a common P-well and the drift region of the first MOS transistor further comprising a P-drift region.

Abstract: A voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold voltages for each of the two otherwise substantially identical P-MOS transistors. The difference between these two threshold voltages is then used to create the voltage reference equal to the difference. The two P-MOS transistors are configured as a differential pair in the operational amplifier circuit and the output of the operational amplifier is used as the voltage reference.

Abstract: A second semiconductor layer of a second nitride-based compound semiconductor with a wider bandgap formed on a first semiconductor layer of a first nitride-based compound semiconductor with a smaller bandgap includes an opening, on which a gate insulating layer is formed at a portion exposed through the opening. A first source electrode and a first drain electrode formed across a first gate electrode make an ohmic contact to the second semiconductor layer. A second source electrode and a second drain electrode formed across a second gate electrode that makes a Schottky contact to the second semiconductor layer make an ohmic contact to the second semiconductor layer.

Abstract: A semiconductor memory device according to the present invention includes: a first transistor formed on a semiconductor substrate 11, the first transistor including a first gate-insulating film 14a that is oxynitrided; and a second transistor including a second gate-insulating film 14b formed on the semiconductor substrate 11 and a barrier film 20 formed at least partially on the second gate-insulating film 14b, the second gate-insulating film having a lower nitrogen atom concentration than the first gate-insulating film.

Abstract: A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and a second n-type MIS transistor including a second n-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section. A first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode.

Abstract: In accordance with the principles of the invention, a semiconductor substrate is provided that has a first cell formed thereon. The first cell has first and second terminals or nodes and a control terminal or node and has a characteristic breakdown voltage across the first and second terminals. A voltage sensing transistor is coupled across the power transistor first and second terminals. The voltage sensing transistor has a second element characteristic breakdown voltage that is less than the first cell characteristic breakdown voltage. The voltage sensing transistor provides a control signal to the terminal when the voltage across the first and second terminals exceeds the second element characteristic breakdown voltage.

Abstract: A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.

Abstract: A semiconductor device includes a plurality of transistors disposed on a semiconductor substrate, a device isolation layer disposed around the transistors, a guard ring disposed to surround the device isolation layer and the transistors, and a guard region disposed between adjacent transistors.

Abstract: A semiconductor device in which an E-FET and a D-FET are integrated on the same substrate, wherein an epitaxial layer includes, in the following order from the semiconductor substrate: a first threshold adjustment layer that adjusts a threshold voltage of a gate of the E-FET and a threshold voltage of a gate of the D-FET; a first etching-stopper layer that stops etching performed from an uppermost layer to a layer abutting on the first etching-stopper layer; a second threshold adjustment layer that adjusts the threshold voltage of the gate of the D-FET; and a second etching-stopper layer that stops the etching performed from the uppermost layer to a layer abutting on the second etching-stopper layer, and at least one of the first etching-stopper layer and the second threshold adjustment layer includes an n-type doped region.

Abstract: A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.

Abstract: An n-type embedded layer is formed in an N-LV region of a SRAM cell region after an element isolation insulating film is formed on a p-type Si substrate. Thereafter, a p-well and an n-well are formed. In formation of a channel-doped layer, ion implantation is also performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-LV of a logic circuit region. Ion-implantation is further performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-MV of an I/O region.

Abstract: A semiconductor device facilitates securing a high breakdown voltage and reducing a chip area thereof includes a low-potential gate driver circuit disposed on a semiconductor substrate, a high-breakdown-voltage junction edge-termination structure disposed in a peripheral portion of a high-potential gate driver circuit, disposed on the semiconductor substrate, for separating the low-potential gate driver circuit and the high-potential gate driver circuit from each other. A trench is disposed in the edge termination structure and between an n+-type source layer and an n+-type drain layer in a level shift circuit in the high-potential gate driver circuit, and an oxide film fills the trench to form a dielectric region in trench.

Abstract: A semiconductor device includes a substrate including a semiconductor layer at a surface, a gate insulating film disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating film. The gate electrode includes a conductive layer consisting of a nitride of a predetermined metal in contact with the gate insulating film. The conductive layer is formed by stacking a first film consisting of a nitride of the predetermined metal and a second film consisting of the predetermined metal, and diffusing nitrogen from the first film to the second film by solid-phase diffusion.

Abstract: A semiconductor integrated circuit has a first substrate of a first polarity to which a first substrate potential is given, a second substrate of the first polarity to which a second substrate potential different from the first substrate potential is given, and a third substrate of a second polarity different from the first polarity. The first substrate is insulated from a power source or ground to which a source of a MOSFET formed on the substrate is connected. The third substrate is disposed between the first and second substrates in adjacent relation to the first and second substrates. A circuit element is formed on the third substrate.

Abstract: An N doped area neighboring to a P doped area on a semiconductor material, function respectively as a first gate and a second gate for transistors. A dielectric layer is made under the gates. A source and a drain are made under and near two sides of the dielectric layer, electrically coupled to the gate to form continuous multigate transistors.

Abstract: A semiconductor device includes a first MISFET and a second MISFET which are formed over a semiconductor substrate and have the same conductive type. The first MISFET has a first gate insulating film arranged over the semiconductor substrate, a first gate electrode arranged over the first gate insulating film, and a first source region and a first drain region. The second MISFET has a second gate insulating film arranged over the semiconductor substrate, a second gate electrode arranged over the second gate insulating film, and a second source region and a second drain region. The first and the second gate electrode are electrically coupled, the first and the second source region are electrically coupled, and the first and the second drain region are electrically coupled. Accordingly, the first and the second MISFET are coupled in parallel. In addition, threshold voltages are different between the first and the second MISFET.

Abstract: A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.

Abstract: Logic LSI includes first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4. The thick-film power switches are formed by thick-film power transistors manufactured in a process common to external input/output circuits I/O. The first power domains include second power domains SPD11 to SPD42 including logic blocks, control circuit blocks SCB1 to SCB4, and thin-film power switches SWN11 to SWN42 that are connected to the thick-film power switches via virtual ground lines VSSM1 to VSSM4, and formed by thin-film power transistors manufactured in a process common to the logic blocks. In this way, power switches having different thickness of gate insulating films from one another are vertically stacked so as to be in a hierarchical structure, and each power switch is individually controlled by a power switch controller and a control circuit block correspondingly to each mode.

Abstract: A semiconductor device according to an example of the present invention includes a first semiconductor region of a first conductivity type, a first MIS transistor of a second conductivity type formed in the first semiconductor region, a second semiconductor region of a second conductivity type, and a second MIS transistor of a first conductivity type formed in the second semiconductor region. A first gate insulating layer of the first MIS transistor is thicker than a second gate insulating layer of the second MIS transistor, and a profile of impurities of the first conductivity type in a channel region of the second MIS transistor has peaks.

Abstract: A mixed voltage circuit is formed by providing a substrate (12) having a first region (20) for forming a first device (106), a second region (22) for forming a second device (108) complementary to the first device (106), and a third region (24) for forming a third device (110) that operates at a different voltage than the first device (106). A gate layer (50) is formed outwardly of the first, second, and third regions (20, 22, 24). While maintaining a substantially uniform concentration of a dopant type (51) in the gate layer (50), a first gate electrode (56) is formed in the first region (20), a second gate electrode (58) is formed in the second region (22), and a third gate electrode (60) is formed in the third region (24). The third region (24) is protected while implanting dopants (72) into the first region (20) to form source and drain features (74) for the first device (106).

Abstract: The semiconductor device includes the concentration of the impurity of the first conductivity type in a doped channel layer of a first conductivity type in the pass transistor is set at a relatively low value, and pocket regions of the first conductivity type in a pass transistor are formed so as to be relatively shallow with a relatively high impurity concentration.

Abstract: A first semiconductor region has a smaller width along a gate length direction than a second semiconductor region. In this case, the first semiconductor region has a larger width along a gate width direction than the second semiconductor region.

Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.

Abstract: Embodiments relate to a multi device that may include a first MOS transistor having a first gate oxide film, and a second MOS transistor having a second gate oxide film thicker than the first gate oxide film. According to embodiments, a LDD structure of the first MOS transistor may be a two-layered structure in which a first LDD region and a second LDD region are disposed vertically downward from the surface of a wafer, and the second LDD region is substantially the same as an LDD structure in the second MOS transistor in doping concentration.

Abstract: The invention describes in detail the structure of a CMOS image sensor pixel that senses color of impinging light without having absorbing filters placed on its surface. The color sensing is accomplished by having a vertical stack of three-charge detection nodes placed in the silicon bulk, which collect electrons depending on the depth of their generation. The small charge detection node capacitance and thus high sensitivity with low noise is achieved by using fully depleted, potential well forming, buried layers instead of undepleted junction electrodes. Two embodiments of contacting the buried layers without substantially increasing the node capacitances are presented.

Abstract: A first MIS transistor is formed in a low voltage transistor formation region and includes a gate insulating film and a first gate electrode composed of a metal film and a polycrystalline silicon film. A second MIS transistor is formed in a high voltage transistor formation region and includes a gate insulating film and a second gate electrode composed of a polycrystalline silicon film. An equivalent oxide thickness of the gate insulating film formed in the low voltage transistor formation region is thinner than an equivalent oxide thickness of the gate insulating film formed in the high voltage transistor formation region. A level of the surface of a semiconductor substrate in the low voltage transistor formation region is higher than a level of the surface of a semiconductor substrate in the high voltage transistor formation region.

Abstract: A gate conductor is provided for a transistor pair including an n-type field effect transistor (“NFET”) having an NFET active semiconductor region and a p-type field effect transistor (“PFET”) having a PFET active semiconductor region, where the NFET and PFET active semiconductor regions are separated by an isolation region. An NFET gate extends in a first direction over the NFET active semiconductor region. A PFET gate extends in the first direction over the PFET active semiconductor region. A diffusion barrier is sandwiched between the NFET gate and the PFET gate. A continuous layer extends continuously in the first direction over the NFET gate and the PFET gate. The continuous layer contacts top surfaces of the NFET gate and the PFET gate and the continuous layer includes at least one of a semiconductor, a metal or a conductive compound including a metal.

Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

Abstract: A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a different high-k metal gate stack to the planar pass gate NFET than to the planar pull-down NFET. Particularly, a threshold voltage adjustment dielectric layer, which is formed over a high-k dielectric layer, is preserved in the planar pass gate NFET and removed in the planar pull-down NFET. The combined NFET active area for the planar pass gate NFET and the planar pull-down NFET is substantially rectangular, which enables a high fidelity printing of the image of the combined NFET active area by lithographic means.

Abstract: Hybrid SRAM circuit, hybrid SRAM structures and method of fabricating hybrid SRAMs. The SRAM structures include first and second cross-coupled inverters coupled to first and second pass gate devices. The pull-down devices of the inverters are FinFETs while the pull-up devices of the inverters and the pass gate devices are planar FETs or pull-down and pull-up devices of the inverters are FinFETs while the pass gate devices are planar FETs.

Abstract: An n-type embedded layer is formed in an N-LV region of a SRAM cell region after an element isolation insulating film is formed on a p-type Si substrate. Thereafter, a p-well and an n-well are formed. In formation of a channel-doped layer, ion implantation is also performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-LV of a logic circuit region. Ion-implantation is further performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-MV of an I/O region.

Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

Abstract: A high-voltage transistor and a peripheral circuit including a second conductivity type MOSFET are provided together on a first conductivity type semiconductor substrate. The high-voltage transistor includes: a low concentration drain region of a second conductivity type formed in the semiconductor substrate; a low concentration source region of a second conductivity type formed in the semiconductor substrate and spaced apart from the low concentration drain region; and a high concentration source region of a second conductivity type having a diffusion depth deeper than that of the low concentration source region. A diffusion depth of the low concentration source region is equal to that of source/drain regions of the MOSFET.

Abstract: A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.

Abstract: The channels of first and second CMOS transistors can be selectively stressed. A gate structure of the first transistor includes a stressor that produces stress in the channel of the first transistor. A gate structure of the second transistor is disposed in contact with a layer of material that produces stress in the channel of the second transistor.

Abstract: A semiconductor device can output a reference voltage for an arbitrary potential and can detect the voltage of each cell in a battery including multiple cells very precisely. The device includes a depletion-type MOSFET 21 and an enhancement type MOSFET 22, and has a floating structure that isolates depletion-type MOSFET 21 and enhancement type MOSFET 22 from a ground terminal. The depletion-type MOSFET 21 and enhancement type MOSFET 22 are connected in series to each other, wherein the depletion-type MOSFET 21 is connected to high-potential-side terminal and the enhancement type MOSFET 22 is connected to low-potential-side terminal. The semiconductor device having the configuration described above is disposed in a voltage detecting circuit section in a control IC for a battery including multiple cells.

Abstract: In a nonvolatile semiconductor memory device which has a nonvolatile memory cell portion, a low-voltage operating circuit portion of a peripheral circuit region and a high-voltage operating circuit portion of the peripheral circuit region formed on a substrate and in which elements of the above portions are isolated from one another by filling insulating films, the upper surface of the filling insulating films in the high-voltage operating circuit portion lies above the surface of the substrate and the upper surface of at least part of the filling insulating films in the low-voltage operating circuit portion is pulled back to a portion lower than the surface of the substrate.

Abstract: A circuit includes an input drain, source and gate nodes. The circuit also includes a group III nitride depletion mode FET having a source, drain and gate, wherein the gate of the depletion mode FET is coupled to a potential that maintains the depletion mode FET in its on-state. In addition, the circuit further includes an enhancement mode FET having a source, drain and gate. The source of the depletion mode FET is serially coupled to the drain of the enhancement mode FET. The drain of the depletion mode FET serves as the input drain node, the source of the enhancement mode FET serves as the input source node and the gate of the enhancement mode FET serves as the input gate node.

Abstract: An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.

Abstract: A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a semiconductor substrate having a first area implanted with first conductive type impurities; an isolating film defining a first active area and a second active area in the first area; first LDD areas spaced from each other on the first active area at a first interval and implanted with second conductive type impurities; and second LDD areas spaced from each other on the second active area at a second interval narrower than the first interval and implanted with the second conductive type impurities.

Abstract: A semiconductor device having a semiconductor substrate, a first impurity region including a first conductive impurity formed in the semiconductor substrate, a first transistor and a second transistor formed in the first impurity region, a first stress film and a second stress having a first stress over the first transistor a and the second transistor, and a third stress film having a second stress different from the first stress provided in the first impurity region between the first stress film and the second stress film.