Insulated Gate Field Effect Transistor Adapted To Function As Load Element For Switching Insulated Gate Field Effect Transistor Patents (Class 257/393)
  • Patent number: 10770349
    Abstract: Processing methods to create self-aligned contacts are described. A conformal liner can be deposited in a feature in a substrate surface leaving a gap between the walls of the liner. A tungsten film can be deposited in the gap of the liner and volumetrically expanded. The expanded film can be removed and replaced with a contact material to a make a contact. In some embodiments, a conformal tungsten film can be formed in the feature leaving a gap between the walls. A dielectric can be deposited in the gap and the conformal tungsten film can be volumetrically expanded to grow two pillars. The pillars can be removed and replaced with a contact material to make two contacts.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: September 8, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Abhijit Basu Mallick, Ziqing Duan
  • Patent number: 10755978
    Abstract: A butted contact structure is provided. In one embodiment, a structure includes a first transistor on a substrate, the first transistor comprising a first source or drain region, a first gate, and a first gate spacer being disposed between the first gate and the first source or drain region. The structure includes a second transistor on the substrate, the second transistor comprising a second source or drain region, a second gate, and a second gate spacer being disposed between the second gate and the second source or drain region. The structure includes a butted contact disposed above and extending from the first source or drain region to at least one of the first or second gate, a portion of the first gate spacer extending a distance into the butted contact to separate a first bottom surface of the butted contact from a second bottom surface of the butted contact.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Leo Hsu, Sheng-Liang Pan
  • Patent number: 10749520
    Abstract: The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: August 18, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Hirotaka Otake, Tatsuya Yanagi, Yusuke Nakakohara
  • Patent number: 10742218
    Abstract: A semiconductor structure includes a vertical transport logic circuit cell. The vertical transport logic cell includes a first logic gate and at least a second logic gate. The first logic gate includes at least one input terminal and at least one output terminal. The second logic gate includes at least one input terminal and at least one output terminal. One of the input terminal and the output terminal of the first logic gate shares a pitch of the vertical transport logic circuit cell with one of the input terminal and the output terminal of the second logic gate. The first and second logic gates can include the same type or different types of logic functions.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corpoartion
    Inventors: Brent A. Anderson, Albert Chu
  • Patent number: 10727238
    Abstract: A method of manufacturing an integrated circuit chip includes doping a substrate with a p-type dopant to form a first p-well region in a first memory cell and a second p-well region in a second memory cell; forming first and second semiconductor fins over the first and second p-well regions, respectively; forming a first work function layer over the first semiconductor fin; forming a second work function layer over the second semiconductor fin and having a thickness different from a thickness of the first work function layer; and forming a metal fill layer over the first and second work function layers.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10522634
    Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jyun Huang, Tung-Heng Hsieh, Bao-Ru Young
  • Patent number: 10509279
    Abstract: A thin film transistor, a TFT substrate, and a display panel are provided. The TFT includes a gate, a source, and a drain. The source is a first bending structure. The drain is a second bending structure. The gate is a third bending structure. The first bending structure of the source and the second bending structure of the drain are arranged opposite. The third bending structure of the gate is arranged between the first bending structure of the source and the second bending structure of the drain. The present disclosure facilitates fabrication of a narrow bezel of a display panel.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: December 17, 2019
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd
    Inventors: Longqiang Shi, Shu-Jhih Chen
  • Patent number: 10497402
    Abstract: An apparatus comprises a plurality of memory cells in rows and columns, a first word line electrically coupled to a first group of memory cells through a first word line strap structure comprising a first gate contact, a first-level via, a first metal line and a second-level via and a second word line electrically coupled to a second group of memory cells through a second word line strap structure, wherein the second word line strap structure and the first word line strap structure are separated by at least two memory cells.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10431541
    Abstract: A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: October 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Hsin-Chun Chang, Hui Lee, Yung-Sheng Huang, Yung-Huei Lee
  • Patent number: 10403543
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: September 3, 2019
    Assignee: SOCIONEXT INC.
    Inventor: Kenichi Watanabe
  • Patent number: 10396139
    Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a substrate and an active pattern formed over the substrate. The OLED display also includes first and second gate electrodes formed over the active pattern. The first gate electrode defines a first transistor together with the active pattern. The second gate electrode defines a second transistor and a third transistor together with the active pattern. The OLED display further includes a first conductive pattern formed over the first and second gate electrodes. The first conductive pattern overlaps at least a portion of the second and/or third transistors so as to define a parasitic capacitor.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: August 27, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ju-Won Yoon, Jung-Hwa Kim, Min-Woo Woo, Il-Jeong Lee, Jeong-Soo Lee
  • Patent number: 10388659
    Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: August 20, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 10297781
    Abstract: An organic light emitting display device includes a plurality of pixels each having a pixel driving circuit. Each of the pixels includes an organic light emitting diode and a driving TFT that controls driving of the organic light emitting diode and includes an active layer of low temperature poly-silicon, a gate node, a source node, and a drain node. The pixels include first to fifth switching TFTs electrically connected to the driving TFT and each including an active layer of an oxide semiconductor, a gate node, a source node, and a drain node. Further, the pixels include a storage capacitor connected between the gate node of the driving TFT and the source node of the fifth switching TFT and a coupling capacitor electrically connected in series to the storage capacitor and configured to cause capacitive coupling to supply a bootstrapped voltage to the gate node of the driving TFT.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: May 21, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Siu Yoon, Seung Chan Choi, Jun Ho Lee, Sung Bin Ryu, Ki Tae Kim
  • Patent number: 10297603
    Abstract: An SRAM includes a substrate containing a plurality of first substrate regions and a plurality of second substrate regions, a plurality of pull-down transistors formed in the first substrate regions with each pull-down transistor including a first gate structure, and a plurality of pass-gate transistors formed in the second substrate regions with each pass-gate transistor including a second gate structure. A portion of the first substrate region under each first gate structure is doped with first doping ions and a portion of the second substrate region under each second gate structure is doped with second doping ions. Moreover, the concentration of the first doping ions is less than the concentration of the second doping ions, and the work function of the first work function layer in the first gate structures is greater than the work function of the second work function layer in the second gate structures.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: May 21, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Xiao Lei Yang, Yong Li, Jian Hua Ju
  • Patent number: 10297592
    Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Kimin Jun, M. Clair Webb, Donald W. Nelson
  • Patent number: 10242732
    Abstract: An integrated circuit is provided that includes memory elements that exhibit immunity to soft error upset (SEU) events when subjected to high-energy atomic particle strikes. Each memory element may include at least two inverting circuits coupled in a feedback loop. Transistors in the memory element may be grouped in one contiguous region or divided into multiple separate regions. The memory element may include a long gate conductor that extends outside the boundary of the one contiguous region or the multiple separated regions. The long gate conductor may serve to provide parasitic resistance in the feedback loop to help mitigate SEU disturbances.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Weimin Zhang, Nelson Joseph Gaspard, Yanzhong Xu
  • Patent number: 10211225
    Abstract: A method including patterning a continuous fin having a first segment and a second segment in a semiconductor layer, the first segment is arranged at an angle relative to the second line segment, and forming a first gate and a second gate substantially parallel to each other, the first gate substantially covering sides and a top of a portion of the first segment of the continuous fin, the second gate substantially covering sides and a top of a portion of the second segment of the continuous fin.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Tenko Yamashita
  • Patent number: 10163880
    Abstract: A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue, Li-Chun Tien
  • Patent number: 10128342
    Abstract: Characteristics of a semiconductor device are improved. An active region including a MOS transistor is structured such that the active region includes, in a plan view, a first side extending in X direction, a second side opposing the first side, an extension part projecting from the first side, and a cut-away portion recessed from the second side. By forming the cut-away portion on the second side opposing the first side where the extension part is formed, the active-region area increase caused by a first rounded portion can be cancelled by the active-region area decrease caused by a second rounded portion. Therefore, even when a gate electrode is disposed near the extension part, gate width variation can be inhibited and characteristics of the MOS transistor can be improved. The distance between the extension part and the gate electrode can be reduced to facilitate miniaturization of the MOS transistor.
    Type: Grant
    Filed: October 22, 2017
    Date of Patent: November 13, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Kyoichi Tsubata
  • Patent number: 10079249
    Abstract: A method including patterning a continuous fin having a first segment and a second segment in a semiconductor layer, the first segment is arranged at an angle relative to the second segment, and forming a first gate and a second gate substantially parallel to each other, the first gate substantially covering sides and a top of a portion of the first segment of the continuous fin, the second gate substantially covering sides and a top of a portion of the second segment of the continuous fin.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Tenko Yamashita
  • Patent number: 10068922
    Abstract: A continuous fin having a first segment and a second segment in a semiconductor layer, the first segment is arranged at an angle relative to the second segment, and a first gate and a second gate substantially parallel to each other, the first gate substantially covering sides and a top of a portion of the first segment of the continuous fin, the second gate substantially covering sides and a top of a portion of the second segment of the continuous fin.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Tenko Yamashita
  • Patent number: 10062419
    Abstract: In accordance with some embodiments of the present disclosure, a circuit structure is provided. The circuit structure comprises a first transistor, a second transistor, a storage node and a word-line. Each of the two transistors comprises a gate, a source and a drain. The storage node is connected to the gate of the first transistor. The word-line is connected to the gate of the second transistor. The first and second transistors are serially connected. The first and second threshold voltages are respectively associated with the first and second transistors, and the first threshold voltage is lower than the second threshold voltage.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: August 28, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hidehiro Fujiwara, Chih-Yu Lin, Wei-Cheng Wu, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 10008500
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to segmented or cut finFET structures and methods of manufacture. The structure includes at least one logic finFET device having a fin of a first length, and at least one memory finFET device having a fin of a second length. The second length is shorter than the first length.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: June 26, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Carl J. Radens
  • Patent number: 9780249
    Abstract: A semiconductor light-receiving includes: a substrate; a semiconductor light-receiving element that is provided on the substrate and has a first conductivity region and a second conductivity region; a first electrode electrically coupled to the first conductivity region; a second electrode electrically coupled to the second conductivity region; an insulating layer located on the second conductivity region; and a wiring that is located on the insulating layer and is electrically coupled to the first electrode, the wiring being elongated from the first electrode to a peripheral region of the semiconductor light-receiving element, the wiring having a region of first width and a region of second width narrower than the first width, the region of second width of the wiring being located on the second conductivity region.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: October 3, 2017
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Yuji Koyama
  • Patent number: 9601351
    Abstract: The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as viewed in plan. Contacts are buried in the first interlayer dielectric film. Through the contacts, an n-type source layer of vertical MOS transistor is coupled with the first source wiring. Openings are made in the first source wiring.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: March 21, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuki Fukui, Hiroaki Katou
  • Patent number: 9324819
    Abstract: A semiconductor device includes an active layer, source electrodes, drain electrodes, gate electrodes, a first dielectric layer, source trace, first source vias, a second dielectric layer, a source pad, and second source vias. The first dielectric layer covers the source electrodes, the drain electrodes, and the gate electrodes. The source traces are disposed on the first dielectric layer, are electrically connected to the source electrodes, and are covered by the second dielectric layer. The source pad is disposed on the second dielectric layer, and includes a first source trunk, a first source branch, and a source sub-branch. The first source branch is protruded from the first source trunk and is electrically connected to one of the drain traces through the second source vias. The source sub-branch is protruded from the first source branch and is electrically connected one of the source electrodes through the third source vias.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: April 26, 2016
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Li-Fan Lin, Shih-Peng Chen
  • Patent number: 9240413
    Abstract: An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: January 19, 2016
    Assignee: Tela Innovations, Inc.
    Inventors: Michael C. Smayling, Scott T. Becker
  • Patent number: 9112030
    Abstract: An epitaxial structure for a non-planar transistor is provided. A substrate has a fin-shaped structure. A gate is disposed across the fin-shaped structure. A silicon germanium epitaxial structure is disposed on the fin-shaped structure beside the gate, wherein the silicon germanium epitaxial structure has 4 <1,1,1> surfaces and its aspect ratio of width and thickness is at a range of 1:1˜1.3. A method for forming said epitaxial structure is also provided.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: August 18, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-I Liao, Chun-Yu Chen
  • Patent number: 9000535
    Abstract: A semiconductor device includes: a semiconductor substrate; a first transistor which is formed on the semiconductor substrate and includes a source/drain region and a gate electrode; an insulating film which covers the source/drain region and the gate electrode of the first transistor; and a first contact plug which is formed in the insulating film and is connected to the source/drain region or the gate electrode of the first transistor, wherein the first contact plug includes a first column section which extends in a thickness direction of the insulating film and is in contact with the source/drain region or the gate electrode of the first transistor, and a first flange section which juts out from an upper portion of the first column section in a direction parallel to a surface of the insulating film, and an upper surface of the first flange section is planarized.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: April 7, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masatoshi Fukuda
  • Patent number: 8994121
    Abstract: A transfer transistor includes a pair of first diffusion regions and a gate electrode layer. The pair of first diffusion regions are formed in a surface of a semiconductor substrate, and are each connected to a contact. The gate electrode layer is formed on the semiconductor substrate via a gate insulating layer and has a pair of openings each surrounding the contact.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kutsukake, Masato Endo
  • Patent number: 8969852
    Abstract: An electronic device including at least first and second transistors integrated together on a substrate and each including an organic semiconductor region, wherein the first and second transistors are either both n-type or both p-type but wherein one of the first and second transistors is a normally-ON transistor and the other of the first and second transistors is a normally-OFF transistor.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: March 3, 2015
    Assignee: Plastic Logic Limited
    Inventors: Paul A. Cain, Henning Sirringhaus, Nicholas J. Stone, Thomas M. Brown
  • Patent number: 8952446
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a channel body, a memory film, first and second insulating separation films, a first and a second inter-layer insulating films, a selection gate, a conductive layer, and resistance elements. The substrate includes a memory cell array region and a peripheral region. The stacked body includes electrode films and insulating films. The channel body extends in a stacking direction. The memory film includes a charge storage film. The first insulating separation films divide the stacked body. The first and the second inter-layer insulating films are on the stacked body and on the conductive layer, respectively. The selection gate is on the first inter-layer insulating film. The conductive layer is on the peripheral region. The resistance elements are on the second inter-layer insulating film. The second insulating separation films divide the conductive layer.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyasu Tanaka
  • Patent number: 8946821
    Abstract: SRAM integrated circuits are provided having pull up and pull down transistors of an SRAM cell fabricated in and on a silicon substrate. A layer of insulating material overlies the pull up and pull down transistors. Pass gate transistors of the SRAM cell are fabricated in a semiconducting layer overlying the layer of insulating material.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: February 3, 2015
    Assignee: Globalfoundries, Inc.
    Inventors: Matthias Goldbach, Peter Baars
  • Patent number: 8912575
    Abstract: The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; at least one first contact hole passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the at least one first contact hole to contact the first conductive layer; and at least one first contact plug connected to the second conductive layer in the first active area, wherein the at least one first contact plug is offset from the at least one first contact hole to overlap the dielectric layer.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 16, 2014
    Assignee: SK Hynix Inc.
    Inventor: Min Gyu Koo
  • Patent number: 8878307
    Abstract: In one aspect, the present invention provides electronic devices that comprise a doped semiconductor shared contact between (a) a gate conductor region of at least one transistor and (b) a source/drain diffusion region of at least one transistor. One specific example of such as shared contact, among many others, is a doped SiGe shared contact between (a) a gate conductor region shared by an N-channel MOSFET and a P-channel MOSFET and (b) a drain diffusion region of an N-channel MOSFET or of a P-channel MOSFET.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: November 4, 2014
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Koji Miyata
  • Patent number: 8878298
    Abstract: Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Leland Chang, Renee T. Mo, Vijay Narayanan, Jeffrey W. Sleight
  • Patent number: 8853792
    Abstract: Embodiments of transistors comprise a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer overlying the oxygen-diffusion barrier layer, and a conductive material (e.g., an oxygen-gettering conductive material) overlying the high-k dielectric layer. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: October 7, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Murshed M. Chowdhury, James K. Schaeffer
  • Patent number: 8829582
    Abstract: A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Noguchi, Kenji Gomikawa
  • Patent number: 8816359
    Abstract: A display device in which not only a variation in a current value due to a threshold voltage but also a variation in a current value due to mobility are prevented from influencing luminance with respect to all the levels of grayscale to be displayed. After applying an initial potential for correction to a gate and a drain of a driving transistor, the gate and the drain of the driving transistor is kept connected in a floating state, and a voltage is held in a capacitor before a voltage between the gate and a source of the driving transistor becomes equal to a threshold voltage. When a voltage obtained by subtracting the voltage held in the capacitor from a voltage of a video signal is applied to the gate and the source of the driving transistor, a current is supplied to a light-emitting element. A value of an initial voltage for correction differs in accordance with the voltage of the video signal.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: August 26, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiroyuki Miyake
  • Patent number: 8779528
    Abstract: A Static Random Access Memory (SRAM) cell includes a first pull-up Fin Field-Effect Transistor (FinFET) and a second pull-up FinFET, and a first pull-down FinFET and a second pull-down FinFET forming cross-latched inverters with the first pull-up FinFET and the second pull-up FinFET. A first pass-gate FinFET is connected to drains of the first pull-up FinFET and the first pull-down FinFET. A second pass-gate FinFET is connected to drains of the second pull-up FinFET and the second pull-down FinFET, wherein the first and the second pass-gate FinFETs are p-type FinFETs. A p-well region is in a center region of the SRAM cell and underlying the first and the second pull-down FinFETs. A first and a second n-well region are on opposite sides of the p-well region.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 8748960
    Abstract: A multi-layer integrated circuit package includes a switched-mode power supply circuit including a plurality of transistors which form part of a main current loop of the switched-mode power supply circuit. The plurality of transistors are arranged in one or more layers of the integrated circuit package. The package further includes a conductive plate arranged in a different layer of the integrated circuit package than the plurality of transistors. The conductive plate is in close enough proximity to at least part of the main current loop so that a current can be electromagnetically induced in the conductive plate responsive to a change in current in the main current loop.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 10, 2014
    Assignee: Infineon Technologies AG
    Inventor: Jens Ejury
  • Publication number: 20140110731
    Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.
    Type: Application
    Filed: December 30, 2013
    Publication date: April 24, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 8697557
    Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming a gate electrode structure above a semiconducting substrate, wherein the gate electrode structure includes a gate insulation layer, a gate electrode, a first sidewall spacer positioned proximate the gate electrode, and a gate cap layer, and forming an etch stop layer above the gate cap layer and above the substrate proximate the gate electrode structure. The method further includes forming a layer of spacer material above the etch stop layer, and performing at least one first planarization process to remove the portion of said layer of spacer material positioned above the gate electrode, the portion of the etch stop layer positioned above the gate electrode and the gate cap layer.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: April 15, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Till Schloesser, Frank Jakubowski
  • Patent number: 8653578
    Abstract: A semiconductor device having a string gate structure and a method of manufacturing the same suppress leakage current. The semiconductor device includes a selection gate and a memory gate. The channel region of the selection gate has a higher impurity concentration than that of the memory gate. Impurities may be implanted at different angles to form the channel regions having different impurity concentrations.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changhyun Lee, Jungal Choi
  • Patent number: 8637931
    Abstract: A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Andres Bryant, Huiming Bu, Wilfried Haensch, Effendi Leobandung, Chung-Hsun Lin, Theodorus E. Standaert, Tenko Yamashita, Chun-chen Yeh
  • Patent number: 8546890
    Abstract: An inverter structure is disclosed. The inverter structure includes an NMOS transistor and a PMOS transistor. Preferably, the NMOS transistor includes an n-type gate electrode and an n-type source/drain region, and the PMOS transistor includes a p-type gate electrode and a p-type source/drain region. Specifically, the n-type gate electrode and the p-type gate electrode are physically separated and electrically connected by a conductive contact.
    Type: Grant
    Filed: November 27, 2008
    Date of Patent: October 1, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Li Kuo, Chia-Chun Sun, Chuan-Hsien Fu, Chun-Liang Hou, Yun-San Huang
  • Patent number: 8519485
    Abstract: A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: August 27, 2013
    Assignee: Crossbar, Inc.
    Inventor: Scott Brad Herner
  • Patent number: 8507953
    Abstract: By providing a body controlled double channel transistor, increased functionality in combination with enhanced stability may be accomplished. For instance, flip flop circuits usable for static RAM cells may be formed on the basis of the body controlled double channel transistor, thereby reducing the number of transistors required per cell, which may result in increased information density.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: August 13, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Frank Wirbeleit
  • Patent number: 8487349
    Abstract: The invention describes in detail the structure of a CMOS image sensor pixel that senses color of impinging light without having absorbing filters placed on its surface. The color sensing is accomplished by having a vertical stack of three-charge detection nodes placed in the silicon bulk, which collect electrons depending on the depth of their generation. The small charge detection node capacitance and thus high sensitivity with low noise is achieved by using fully depleted, potential well forming, buried layers instead of undepleted junction electrodes. Two embodiments of contacting the buried layers without substantially increasing the node capacitances are presented.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: July 16, 2013
    Assignee: Foveon, Inc.
    Inventors: Jaroslav Hynecek, Richard B. Merrill, Russel A. Martin
  • Patent number: 8482083
    Abstract: Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: July 9, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Osada, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi