Abstract: The invention is directed to the provision of a two-input, four-output high frequency switch circuit that can prevent the occurrence of in-band ripples of insertion loss in an ON path. The high frequency switch circuit is constructed from six field effect transistors, and a signal is passed through a selected one of signal paths in the two-input, four-output high frequency signal switch having a total of six signal terminals, wherein four additional field effect transistors, each of which, when ON, provides a characteristic impedance matched to the characteristic impedance of an external circuit, are respectively connected between ground and the signal paths leading to the remaining four signal terminals to which the signal is not passed and which therefore become open ends.

Abstract: A semiconductor device is provided with an SRAM memory cell. The semiconductor device includes a first gate-gate electrode layer, a second gate-gate electrode layer, a first drain-drain wiring layer, a second drain-drain wiring layer, a first drain-gate wiring layer and a second drain-gate wiring layer. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively. The upper layer is provided above either an n-type well region or a p-type well region.

Abstract: A plurality of p wells and a plurality of n wells are formed in a p-type semiconductor substrate having a memory portion and a peripheral circuit portion. Next, a resist pattern is formed on the semiconductor substrate. The resist pattern has apertures which, as viewed from the direction normal to the plane of the semiconductor substrate, approximately coincide with the p wells, wherein the area of aperture openings on the top side of the resist pattern is different from the area of aperture openings on the bottom side of the resist pattern. By using the resist pattern as a mask, p-type ions are injected in a shape approximately the same as that of the aperture opening on the top side or bottom side, whichever has the smaller area.

Abstract: First and second gate electrode layers that are positioned in a first conductive layer, first and second drain-drain contact layers that are positioned in a second conductive layer, and first and second drain-gate contact layers that are positioned in a third conductive layer together form conductive layers for a flip-flop. A sub word line extends in the X-axis direction in the first conductive layer. A VDD wire is disposed extending in the X-axis direction in the second conductive layer. A main word line is disposed extending in the X-axis direction in the third conductive layer. A bit line, a bit line/, a VSS wire, and a VDD wire are disposed extending in the Y-axis direction in the fourth conductive layer.

Abstract: A push-pull transistor chip comprises a single/semiconductor die having first and second LDMOS transistors formed thereon and configured for push-pull operation, the first and second transistors sharing a common element current region. In a power transistor package, the push-pull transistor chip is attached to a mounting flange serving as a common element ground reference, wherein a conductor (e.g., one or more bond wires) electrically connects the shared common element current region to the mounting flange.

Abstract: Disclosed is a field-effect switch that uses an applied field to induce superconductivity in a normally insulative switch element. The switch element comprises an intercalated crystal of C60 together with a further species such as a methylene trihalide. Using such a switch element, we have obtained field-induced superconducting transitions at temperatures well above 77K.

Abstract: A method of forming conductive contacts to drain and source regions of a semiconductor device such as a field effect transistor (FET). A gate structure is formed over a portion of a semiconductor substrate, wherein the gate structure includes: a gate dielectric on a surface of the semiconductor substrate, a conductive gate aligned on the gate dielectric, a silicide layer aligned on the conductive gate, and a silicon nitride cap aligned on the silicide layer. Insulative spacers are formed on sidewalls of the gate structure, and the insulative spacers contact the semiconductor substrate. A drain region and a source region are formed within the semiconductor substrate, wherein a channel region is disposed between the drain region and the source region, and wherein the gate structure is over the channel region.

Abstract: A semiconductor configuration includes a substrate having a first conduction type. A transistor configuration is disposed at the substrate and is formed from at least one field-effect transistor having at least two doped regions embedded in the substrate and at least one gate electrode. The regions have a second conduction type, are disposed between the transistor configuration and the substrate edge, and extend from the substrate surface into the substrate and surround the transistor configuration. At least two adjacent insulating trench regions are disposed between the regions and extend from the substrate surface into the substrate for isolating the doped regions from one another. The trenches may have a smaller depth than the doped regions. A method for fabricating a semiconductor configuration includes providing a substrate having a first conduction type and producing regions in the substrate by introducing a dopant. The regions have a second conduction type.

Abstract: A semiconductor memory device comprising first and second gate-gate connecting layers, first and second drain-drain connecting layers, and first and second drain-gate connecting layers. The first and second gate-gate connecting layers respectively connect a gate of a driver transistor to a gate of a load transistor. The first and second drain-drain connecting layers are formed over a first interlayer dielectric and have a refractory metal nitride layer. The first and second drain-drain connecting layers respectively connect a drain of the driver transistor to a drain of the load transistor. The first and second drain-gate connecting layers are formed over a second interlayer dielectric, and respectively connect the first drain-drain connecting layer to the second gate-gate connecting layer, and the second drain-drain connecting layer to the first gate-gate connecting layer.

Abstract: To provide an address programming device free from laser-blowing, a first, thin gate oxide film is formed on a semiconductor substrate, a first gate electrode is formed thereon, a second, thick gate oxide film is formed thereon, and a second gate electrode is formed thereon. Such a device is connected in series to a MOS transistor of the opposite polarity and such arrangements are cross-connected together to form a latch circuit. Data to be programmed and the inverted version thereof are written in the programming device. Programmed information is read depending on the change in weight of the latch when the power supply is turned on.

Abstract: In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same substrate, the manufacturing process is complicated in order to set the circuits to the optimum values. As a result, in association with deterioration in the yield and increase in the number of manufacturing days, the manufacturing cost increases. In order to solve the problems, according to the invention, transistors of high and low thresholds are used in a logic circuit, a memory cell uses a transistor of the same high threshold voltage and a low threshold voltage transistor, and an input/output circuit uses a transistor having the same high threshold voltage and the same concentration in a channel, and a thicker gate oxide film.

Abstract: Performance matching devices in SOI are improved by thermally isolating matched devices within a continuous body of active material. Matched devices are isolated by an insulating wall of silicon dioxide (which surrounds the devices) and the oxide layer beneath, and are arranged to minimize effects from external thermal sources.

Abstract: A semiconductor device that operates at high speed using a low voltage power source, in which the output of each gate in the standby state is stable, and which has a delay time that is not affected by the frequency of the input signal. TrQ1 to TrQ8, which form multiple stages of the inverters are designed to have a low threshold voltage in order to accomplish low voltage operation. When input node A is at “L” in the standby state, TrQ2, Q3, Q6, and Q8 which cut-off are connected to high threshold voltage TrQn1 and Qp1. In the standby state, power cutting TrQn1 and Qp1 cut off in accordance with chip selecting signals CS, /CS, thereby blocking the flow of sub-threshold current to TrQ1˜Q8. Since TrQ1, Q4, Q5 and Q8 are not cut off at this time, the output potential of each inverter is stable.

Abstract: A high voltage switching device includes a switching circuit for switching a high voltage to an output line and for providing a control signal. The high voltage switching device also includes a switching transistor connected to the switching circuit for switching a low voltage to the output line based upon the control signal. The output signal is controlled by a control circuit that sets up a control loop between the drop in the gate voltage level of the switching transistor and the voltage level of the output line that is controlled by the switching circuit.

Abstract: The purpose of this invention is to ensure an active use of the inverse short-channel effect in the ratio circuit and to guarantee stable operation at low power source voltage. In this ratio circuit, N-channel MOS transistor 12 of CMOS circuit 10 on one side forms the drive element, while P-channel MOS transistor 18 of CMOS circuit 16 on the other side forms the load element. Said N-channel MOS transistor 12 on the drive side and P-channel MOS transistor 16 on the load side have their drain terminals electrically connected to each other through transfer gate 22 made of N-channel MOS transistor. MOS transistor 12 on the drive side has a single channel CHa with the inverse short-channel effect. MOS transistor 18 on the load side has plural, e.g., two, channels CHb1 and CHb2, connected in tandem, each of which displays the inverse short-channel effect.

Abstract: A semiconductor device comprising a peripheral circuit portion and a memory cell portion including a plurality of memory cells. Each memory cell has first and second gate-gate connecting layers, first and second drain-drain connecting layers, and first and second drain-gate connecting layers. The first and second gate-gate connecting layers respectively connect the gates of driver transistors to the gates of load transistors. The first and second drain-drain connecting layers are formed over a first interlayer dielectric and respectively connect the drains of driver transistors to the drains of load transistors. The first and second drain-gate connecting layers are formed over a second interlayer dielectric and respectively connect the first drain-drain connecting layer to the second gate-gate connecting layer and the second drain-drain connecting layer to the first gate-gate connecting layer.

Abstract: A high frequency switch circuit device includes an FET to be a switching element on a semiconductor substrate. The FET includes an n-type well, a gate electrode, a source layer and a drain layer. An n-type well line to be connected to an n-type well layer to be a back gate is connected to a voltage supply node via an inductor. The flow of a high frequency signal between the voltage supply node and the n-type well layer is blocked by the inductor, and the flow of a high frequency signal in the vertical direction is blocked by a depletion layer extending between the n-type well and a p-type substrate region. Moreover, the flow of a high frequency signal in the horizontal direction is blocked by a trench separation insulative layer.

Abstract: In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

Abstract: In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

Abstract: A semiconductor apparatus includes a cell and a dummy cell. The cell has a first conductivity type of diffusion layer formed in a second conductivity type of semiconductor region. The second conductivity type is opposite to the first conductivity type. The dummy cell has the second conductivity type of dummy diffusion layer formed in the semiconductor region. The dummy cell is adjacent to the cell.

Abstract: In a static random access memory cell including two cross-coupled drive MOS transistors and two transfer MOS transistors connected to the drive MOS transistors, a plurality of gate electrodes of the drive MOS transistors and the transfer MOS transistors are formed over a semiconductor substrate, and a plurality of source/drain impurity diffusion regions of the transistors are formed within the semiconductor substrate. A plurality of pocket regions of the same conductivity type as the semiconductor substrate are formed within the semiconductor substrate. Each of the pocket regions is adjacent to the source of one of the drive MOS transistors and beneath the gate electrode thereof. The impurity concentration of the pocket regions is larger than that of the semiconductor substrate.

Abstract: Disclosed is a semiconductor device and a process for producing a semiconductor device using a gate electrode such as an SRAM, wherein a gate electrode pattern is formed with fidelity to a reticle pattern through no complicated layout design and the gate electrode pattern is formed in an area smaller than that of a conventional semiconductor device. In a lithographic step using a reticle pattern provided with substantially linear gate electrode patterns, a projecting portion in which at least a part of a contact region is arranged is formed such that it is included in almost the center of a long side of a linear gate electrode pattern and a concave portion facing at least the entire length of the projecting portion is formed such that it is included in a long side opposite to the projecting portion between transistor regions of a reticle pattern.

Abstract: Upon formation, by oblique ion injection, of a pocket ion region in a p channel type MISFET forming region (n type well) constituting SRAM, the p channel type MISFET forming region is disposed apart from a resist film formed over an n channel type MISFET forming region (p type well) within a distance, which is the product of the thickness H of the resist film and the tangent of an ion injection angle &thgr;. Consequently, an impurity is not injected from one direction, in spite of the injection from four directions, which makes it possible to suppress fluctuations of the impurity concentration in the pocket ion region.

Abstract: A static semiconductor memory device capable of preventing soft errors is provided. The static semiconductor memory device includes: a silicon substrate having a p-type well region; a storage node; an n-type-low-concentration impurity region and a high-concentration impurity region formed in the surface of p-type well region and connected to storage node; and a p-type impurity region formed to have contact with high-concentration impurity region.

Abstract: A semiconductor memory device has a silicon substrate 10. A first embedded layer 11 is formed in the silicon substrate 10 under a p-well 18 in an area below a region where a drain 36 of a driver transistor 30 is located. The first embedded layer 11 makes a junction with the p-well 18. Also, the first embedded layer 11 is formed below an n-well 16 and contacts the n-well 16. When the drain 36 of the driver transistor 30 is at a voltage of 3V, &agr;-ray may pass through the p-well 18, the first embedded layer 11 and the silicon substrate 10. As a result, electron-hole pairs are cut. Due to the presence of the p-n junction that is formed by the p-well 18 and the first embedded layer 11, only electrons in the p-well 18 are drawn to the drain 36. As a result, a fall in the drain voltage of 3V is reduced. As a consequence, the device structure makes it difficult to destroy retained data.

Abstract: An SRAM cell is arranged in a semiconductor device. A metal oxide semiconductor field effect transistor is arranged in the SRAM cell. An interlayer insulating film is formed on the metal oxide semiconductor field effect transistor. A load resistor conductive layer is formed on the interlayer insulating film. In addition, a wiring conductive layer which connects the gate electrode of the metal oxide semiconductor field effect transistor to the load resistor conductive layer is provided. The resistance of the wiring conductive layer is lower than the resistance of the load resistor conductive layer. A side wall is formed between the load resistor conductive layer and the wiring conductive layer.

Abstract: A DTCMOS circuit produces an output based on a logical combination of input logic signals. The circuit includes input transistors which receive on a respective gate a respective logic signal. The transistors have a body contact which is connected to the gate of another transistor. Transistors which are receiving later arriving logic signals therefore have a threshold voltage lowered by an earlier arriving logic signal. By coupling the earlier arriving logic signal with a body contact of another input transistor, the threshold voltage may be lowered prior to processing of the subsequently arriving logic signal. The DTCMOS circuit may be implemented in SOI with the attendant benefits of a lower supply made possible by the lowered voltage threshold each of the transistors without sacrificing leakage current inherent in DTCMOS circuits.

Abstract: A semiconductor ROM device which enables to obtain a reference current which can securely distinguish data stored in a memory cell in a multilevel mask ROM for storing multilevel data of three or more levels per memory cell. The device comprises a memory cell in which a threshold voltage is set up corresponding to an amount of ions injected to a channel region of a cell transistor and multilevel data of three or more levels are stored, a reference cell for generating the reference current for comparing with a current read out from the memory cell, and dummy cells disposed adjacent to the reference cell. In the channel region of the reference cell and the channel region of the dummy cell, ions are injected simultaneously to set up the equal threshold voltages both in the reference cell and the dummy cell.

Abstract: A SRAM includes a plurality of high-resistance memory cells each having a point symmetric structure. The memory cell has a pair of load resistors each implemented by a contact plug. Each of the contact plugs connects the drain of a first drive transistor and the gate of a second drive transistor with a source line. The source/drain region of each transfer transistor is connected to a bit line implemented by a fourth layer alumninum via a contact plug received in a through-hole having a side wall for insulating the contact plug from the ground line implemented as a third layer polysilicon film.

Abstract: A full CMOS SRAM cell is provided. The SRAM cell includes first and second active regions formed on a semiconductor substrate, arranged parallel to each other. A third active region is formed on the semiconductor substrate between the first active region and the second active region parallel to the first active region, and a fourth active region is formed on the semiconductor substrate between the third active region and the second active region parallel to the second active region. A word line intersects the first and second active regions. A first common conductive electrode intersects the first active region and the third active region, and a second common conductive electrode intersects the second active region and the fourth active region.

Abstract: An SRAM cell and method for fabricating the same including first and second access transistors, first and second drive transistors, and first and second load resistors. A first terminal of the first access transistor, a gate terminal of the second drive transistor, and a first load resistor terminal are connected to one another to form a first cell node terminal. A first terminal of the second access transistor, a gate terminal of the first drive transistor, and a second load resistor terminal are connected to one another to form a second cell node terminal. The SRAM cell includes a gate electrode of each of the first and second drive transistors arranged over a semiconductor substrate in a first direction, and a gate electrode of each of the first and second access transistors arranged in the first direction overlapped with portions of the gate electrodes of the first and second drive transistors.

Abstract: A static random-access memory integrated circuit formed on a single substrate includes a storage IGFET formed on the substrate and having a first area and a first capacitance. A gating FET formed on the substrate has an area substantially equal to the first area with a capacitance substantially less than the first capacitance. In one aspect, the storage FET has a substantially thicker gate oxide than the gating FET. In another aspect, the gate oxide of one of the FETs is formed from a different material than that of the other FET. A method for fabricating such IGFETs on a single substrate is also provided in which source and drain regions are formed adjacent the surface of the substrate. A first layer of gate oxide is formed on the surface of the substrate over the channels of the first and the second FETs. The first layer of gate oxide is then covered by a nitride layer which is thereafter etched away over the channel of one of the FETs.

Abstract: A method of manufacturing a semiconductor device comprising the following steps: forming first, second, and third wiring layers on a semiconductor substrate; forming first, second, and third cover dielectric layers for covering these wiring layers; forming a first impurity diffusion layer of a P type and a second impurity diffusion layer of an N type in an active region, and forming a third impurity diffusion layer of a P type and a fourth impurity diffusion layer of an N type in an active region; self-alignably forming a first local wiring layer for connecting the first impurity diffusion layer with the second wiring layer, and self-alignably forming a second local wiring layer for connecting the fourth impurity diffusion layer with the third wiring layer; in an interlayer dielectric layer, self-alignably forming a first contact hole by using the first and third cover dielectric layers as masking layers, and self-alignably forming a second contact hole by using the second cover dielectric layer as a masking

Abstract: A power semiconductor device of the present invention comprises a voltage drive type power MOS transistor, a series connection of a first resistor and Zener diode, a second resistor, and a series connection of a third resistor and MOS transistor. The power MOS transistor has a gate, source and drain. A drain-to-source voltage of the power MOS transistor is applied across the series connection of the first resistor and Zener diode. A gate-to-source voltage of the power MOS transistor is applied across the second resistor. The gate-to-source voltage of the power MOS transistor is applied across a series connection of a third resistor and the MOS transistor. The MOS transistor has a gate, source and drain. The gate of the MOS transistor is connected to a node between the first resistor and the Zener diode.

Abstract: A first to fifth plugs provide interconnection between each transistor and a first metallic interconnection layer. A sixth to eighth plugs provide interconnection between the first metallic interconnection layer and a second metallic interconnection layer. The total opening area of a connecting window including at least one connecting hole (or the number of connecting holes) is designed in a smaller zone when the type of electric current (waveform) is a bidirectional-directional current, when the flow direction of electric current is from a plug to an interconnection line, when the length of interconnection line is long, or when the width of interconnection line is small. Such arrangement makes it possible to achieve a reduction of the area occupied by interconnections by performing layout design allowing for the permissible electric current amount, without having to prepare complicated tables or without having to perform huge amounts of arithmetic processing.

Abstract: A read-only memory includes a semiconductor substrate; a memory cell matrix which is formed on the semiconductor substrate; and word and bit lines which define the locations of the memory cell matrix. The memory cell matrix includes field effect transistors, each of which turns off when accessed or addressed; and conducting regions, which keep conductive state all the time. Binary data stored in the memory cell matrix are determined by detecting current flowing through the selected bit line.

Abstract: A six transistor static random access memory (SRAM) cell with thin-film pull-up transistors and method of making the same includes providing two bulk silicon pull-down transistors of a first conductivity type, two active gated pull-up thin-film transistors (TFTs) of a second conductivity type, two pass gates, a common word line, and two bit line contacts. The bulk silicon pull-down transistors, two active gated pull-up TFTs, and two pass gates are connected at four shared contacts. In addition, the two bulk silicon pull-down transistors and the two active gated pull-up TFTs are formed with two polysilicon layers, a first of the polysilicon layers (poly1) is salicided and includes poly1 gate electrodes for the two bulk silicon pull-down transistors. A second of the polysilicon layers (poly2) includes desired poly2 stringers disposed along side edges of the poly1 gate electrodes, the desired poly2 stringers forming respective channel regions of the pull-up TFTs.

Abstract: In an access transistor formed on a silicon substrate, its drain region is formed of n− type and n+ type drain regions and its source region is formed of n− type and n+ type source regions. In a driver transistor, its source region is formed of n− type and n++ type source regions and its drain regions is formed of n− type and n+ type drain regions. The n+ +type source region is formed deeper than the n+ type drain region. Accordingly, a semiconductor device ensuring improvement in a static noise margin while suppressing increase in manufacturing cost is provided.

Abstract: A floating gate transistor has a reduced barrier energy at an interface between a gallium nitride (GaN) or gallium aluminum nitride (GaAlN) floating gate an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

Abstract: A lateral MOS transistor including a gate and drain and source regions of a first conductivity type formed in a substrate of a second conductivity type connected to a first power supply, wherein a doped buried layer of the first conductivity type extends under said drain region and under a portion of the gate, the buried layer being connected to the gate via a one-way connection.

Abstract: An SRAM according to the present invention includes a voltage-down circuit and an internal circuit. The voltage-down circuit includes three resistors, two PMOS transistors and an NMOS transistor. One PMOS transistor directly applies an external power supply voltage to the internal circuit. The NMOS transistor applies a voltage obtained by reducing the external power supply voltage by a threshold voltage thereof to the internal circuit. The value of a predetermined voltage as a condition for switching such application of the voltage by the PMOS transistor and application Of the voltage by the NMOS transistor is determined by the resistance ratio of the two resistors. Each of the three resistors is formed by a plurality of resistance elements of one kind. Thus, even if the process parameter varies, the ratio of the resistance values of the two resistors which determines the switching point can be kept constant, thereby preventing variation in switching point.

Abstract: A composite MOS transistor device for a semiconductor integrated circuit includes at least a pair of MOS transistors, or first and second MOS transistors, placed on the same board. The first and second MOS transistors are made up of first and second groups of equally divided transistors with an equal gate width, respectively. These divided transistors are arranged in parallel to each other in the gate longitudinal direction. The divided transistors of these groups are arranged such that the sum of coordinates of respective gates, measured from a centerline, is equalized between these groups along the gate longitudinal direction. Since the sum of errors of respective gates along the length thereof becomes zero in each group of divided transistors, the current difference between the two MOS transistors can be eliminated.

Abstract: An SRAM cell comprising, at least, two driving transistors and two transfer transistors, and two load transistors each comprised of a TFT and disposed on these transistors through a layer insulation film, the load transistors having an active region comprising an Si film having improved crystallizability of amorphous Si by the solid phase growth technique using a catalytic element, and a barrier layer for preventing the catalytic element from diffusion into the driving transistors and the transfer transistors which is disposed between the layer insulation film and the load transistors.

Abstract: A dual bit read only memory cell has two bits separately stored in two different areas of the channel, such as the left and right bit line junctions of the channel. A programmed bit has a threshold pocket implant self-aligned to its bit line junction and an unprogrammed bit has no such implant. An array of such cells is manufactured by laying down a bit line mask and separately programming the two bit line junctions. For each bit line junction, the bit line junctions which are to remain unprogrammed are first covered, with a junction mask, after which the array is exposed to a threshold pocket implant at a 15-45° angle, to the right or to the left. The junction mask is removed and the process repeated for the other bit line junction. Finally, the bit line mask is removed. In an alternative embodiment, the threshold pocket implant is two implants, of two different materials.

Abstract: In a method of manufacturing a semiconductor device, an insulating film is formed on a semiconductor substrate. A semiconductor film pattern is formed on the insulating film. A direct thermal nitriding method is performed to at least a portion of the semiconductor film pattern. The direct thermal nitriding method is performed by lamp annealing in a gas composed of nitrogen such that a thermally nitrided film has a film thickness of equal to or thicker than 1.5 nm. Thus, invasion of a hydrogen atom or ion into the semiconductor film pattern can be prevented.

Abstract: A static random access memory cell is given increased stability and latch-up immunity by using N-type gate NMOS transistors and P-type gate PMOS transistors in the control and sensing circuits, but using the same gate conductivity type for both the NMOS and PMOS memory cell transistors. For example, both NMOS and PMOS memory cell transistors have N-type gates. Weakening the memory cell load transistors by lightly doping the source and/or drain regions further enhances stability.

Abstract: An FS upper nitride film (15) is formed on the upper surface of an FS electrode (5). Therefore, the upper surface of the FS electrode (5) is not exposed even when an FS upper oxide film (41) is partially almost removed in the manufacturing process. Thus, a semiconductor device which prevents degradation in operation characteristics and reliability due to existence of an FS insulating layer can be provided.

Abstract: A shared contact is provided on the side of a drain active region of each of two load transistors. Thus, a stabilized low voltage operation is ensured in a full CMOS type SRAM memory cell having the shared contact.

Abstract: A method of forming a thin film transistor includes, a) forming a thin film transistor layer of semiconductive material; b) providing a gate operatively adjacent the thin film transistor layer; c) forming at least one electrically conductive sidewall spacer over at least one lateral edge of the gate, the spacer being electrically continuous therewith; and d) providing a source region, a drain region, a drain offset region, and a channel region in the thin film transistor layer; the drain offset region being positioned operatively adjacent the one electrically conductive sidewall spacer and being gated thereby. The spacer is formed by anisotropically etching a spacer forming layer.

Abstract: The present invention introduces an SRAM cell which enhances immunity to soft errors and a manufacturing method thereof. A method of manufacturing an SRAM cell having access devices, pull-up devices and pull-down devices and forming a cell node junction in common junction regions of the pull-down devices and the access devices, the manufacturing method including the steps of: providing a semiconductor substrate of which active regions are difined and gate insulating layers and gates are formed on thereof; forming N.sup.- junction regions in the substrates of both sides of the gates for the pull-down devices region and the access devices region, wherein the N.sup.- junction regions formed in the cell node are separated therein and are adjacent to the gates thereof; forming the insulating layer spacers on both side-walls of the gates; and forming N.sup.+ junction regions in the substrate of both side of the spacers for the pull-down devices region and the access devices region.