Abstract: There are contained the steps of forming an undoped or low impurity concentration amorphous silicon film to project from an upper surface of a first insulating film, introducing selectively impurity into an uppermost surface of the amorphous silicon film to form the uppermost surface of the amorphous silicon film as a high concentration impurity region, forming hemispherical grained silicon on the uppermost surface of the amorphous silicon film at a first density and on a side surface at a second density higher than the first density by exposing the amorphous silicon film to a silicon compound gas and then annealing the amorphous silicon film in a low pressure atmosphere, and introducing the impurity into the hemispherical grained silicon and the amorphous silicon film. Accordingly, a semiconductor device having a capacitor, in which a cylindrical storage electrode from an upper surface of which silicon projections are difficult to come off is formed, can be provided.

Abstract: CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively.

Abstract: An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.

Abstract: A high-voltage device. A substrate has a first conductive type. A first well region with the first conductive type is located in the substrate. A second well region with the second conductive type is located in the substrate but is isolated from the first well region. Several field oxide layers are located on a surface of the second well region. A shallow trench isolation is located between the field oxide layers in the second well region. A first doped region with the second conductive type is located beneath the field oxide layers. A second doped region with the first conductive type is located beneath the shallow trench isolation in the second well region. A third well region with the first conductive type is located in the first well region and expands from a surface of the first well region into the first well region. A gate structure is positioned on the substrate between the first and the second well regions and covers a portion of the first, the third well regions and the field oxide layers.

Abstract: A high voltage transistor exhibiting low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a field implant blocking mask over the channel area, thereby producing a transistor with low body effect, the field implant blocking mask having appropriate openings so that the field implant occurs at the edges of the channel, thereby reducing leakage.

Abstract: A submicron semiconductor device having a self-aligned channel stop implant region, and a method for fabricating the semiconductor device using a trim and etch is disclosed. The semiconductor device includes a plurality of active regions separated by insulating regions. The method for fabricating the device includes depositing a nitride over a substrate and selectively covering the active regions with a mask, wherein the mask extends beyond boundaries of the active regions to narrow the width of the insulating regions. Thereafter, a channel stop implant is performed to form channel stops. The mask is then trimmed to the boundaries of the active regions after formation of the channel stops, followed by etching the nitride in exposed areas of the mask. Field oxide is then grown in the insulating regions, whereby the field oxide is self-aligned to the channel stops.

Abstract: A hemispherical grained (HSG) lower electrode, and its manufacturing method, are disclosed in which the yield is enhanced by suppressing the depletion due to insufficient diffusion of an impurity into the hemispherical grains (abbreviated also as HSGs) to reduce the deterioration in the capacity caused by the defect on the negative (lower) electrode side, and preventing the fracture of the HSGs. In a method of forming a capacitor composed of a polysilicon lower electrode, a dielectric film, and an upper electrode, the method of this invention includes at least a step of forming HSG silicon on the lower electrode, where each of its grains has a neck with decreased diameter on the side of the contact plane with the lower electrode, a step of depositing a silicon film covering the HSGs by filling the gaps between the lower electrode in the periphery of the necks and the HSGs while maintaining the rugged shape of the formed HSGs, a step of forming a dielectric film, and a step of forming an upper electrode.

Abstract: A nonvolatile memory device having a lightly doped source and a method for manufacturing the same are provided. In the nonvolatile memory device, a first insulating layer, a floating gate, a second insulating layer and a control gate are sequentially formed on a semiconductor substrate, and a drain, a lightly doped source and a highly doped source are formed around a surface of the semiconductor substrate. At this time, the highly doped source is shallower than the drain without being overlapped by the floating gate. Thus, the integration of the memory cell can be increased, and the trapping of electrons is reduced in the first insulating layer formed between the floating gate and the lightly doped source, to thereby enhance the characteristics of the memory cell.

Abstract: A microelectronic device fabricating method includes providing a substrate having a mean global outer surface extending along a plane. A first portion is formed over the substrate comprising a straight linear segment which is angled from the plane and forming a second portion over the substrate comprising a straight linear segment which is angled from the plane at a different angle than the first portion. A layer of structural material is formed over the first and second portions. The structural material layer is anisotropically etched and a first device feature is ultimately left over the first portion having a first base width and a second device feature is ultimately left over the second portion having a second base width which is different from the first base width. Integrated circuitry includes a substrate having a mean global outer surface extending along a plane.

Abstract: The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the vertical surface area of the trench sidewall. A trench isolation region (40) is formed within the semiconductor substrate (12). A doped region (74, 96) is then formed such that it abuts the trench sidewall (24). A portion (56, 110) of the trench sidewall (24), abutting the doped region (74, 96), is then exposed by forming a recess (55, 112) within the trench isolation region (40). A conductive member (66, 114, 118) is then formed such that it is electrically coupled to the doped region (74, 96) along the exposed trench sidewall, as well as along the major surface (13) of the semiconductor substrate (12), and results in the formation of a low resistance contact structure.

Abstract: A high-voltage device. A first well region with a first conductive type is located in a substrate. A second well region with the second conductive type is located in the substrate but is isolated from the first well region. Several field oxide layers are located on a surface of the second well region. A shallow trench isolation is located between the field oxide layers in the second well region. A first doped region with the second conductive type is located beneath the field oxide layers. A second doped region with the first conductive type is located beneath the shallow trench isolation in the second well region. A third well region with the first conductive type is located in the first well region and expands from a surface of the first well region into the first well region. A gate structure is positioned on the substrate between the first and the second well regions and covers a portion of the first, the third well regions and the field oxide layers.

Abstract: A programmable memory device having slot trenches (14). A plurality of floating gates (22) are separated from a surface of semiconductor body (10) by a gate dielectric (24). A plurality of slot trenches (14) isolate memory cells (12) from each other. Each of the slot trenches (14) extends below the surface of the semiconductor body (10) between adjacent floating gates (22). A control gate (20) extends over the floating gates (22) and a portion of each of the slot trenches (14).

Abstract: A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, and employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants. Appropriate openings are formed in the field implant blocking mask so that the field implant occurs at the edges of the junctions, thus achieving low leakage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

Abstract: A method of forming integrated isolation regions and active regions includes first forming a plurality of dielectric layers upon a semiconductor substrate. Then, a patterned mask is applied to define portions of the dielectric layers that will remain to form isolation regions and to define portions of the dielectric layers that will be removed in an etch step to create voids to the surface of the semiconductor substrate. Subsequently, epitaxially growth is employed to form active regions within the voids that were previously formed. Transistors are then formed in and on the active regions and are subsequently interconnected to form an integrated circuit.

Abstract: An element that prevents the formation of a channel is arranged in a level of the channel region (Kaa) at one of two opposite sidewalls of a semiconductor structure that has a source/drain region (S/D1a) and a channel region (Kaa) of a vertical selection transistor arranged therebelow. The source/drain region as well as a respective word line (W1a) adjoin at both sidewalls. For folded bit lines (B1a), respectively two word lines (W1a) can be formed in the trenches (G2a). The elements of semiconductor structures neighboring along one of the trenches (G2a) are then arranged in alternation at a sidewall of the trench (G2a) and at a sidewall of a neighboring trench (D2a). A storage capacitor can be arranged over a substrate (1a) or can be buried in the substrate (1a). The connection of the selection transistor to a bit line (B1a) can ensue in many ways.

Abstract: The present invention is a semiconductor device comprising an isolated N-type diffusion layer formed on part of a P-type semiconductor substrate or P-type well, a P-type channel barrier region formed so as to contact at least one part of the N-type diffusion layer, and an electrode drawn from the N-type diffusion layer through a contact hole; and constituting check elements to check the state of the P-type channel barrier region through measuring the junction withstand voltage of the N-type diffusion layer. With the aforementioned constitution, the state of the P-type channel barrier region can be checked with good sensitivity and without true breakdown of the thin oxide film having the same thickness as the gate oxide and influence from variations in the thickness of the field oxide, because the state of the P-type channel barrier region is checked by measuring the junction withstand voltage of the N-type diffusion layers.

Abstract: The work surface of a p-type silicon substrate has a section where an E type MOSFET is formed, and a section where an I type MOSFET having a threshold voltage of about 0.1V is formed. The MOSFET is formed using a p-type well layer having a resistivity lower than that of the ground of the silicon substrate. The well layer includes deep and shallow portions which are integrally formed and have the same resistivity. The deep well portion defines an element area for forming the MOSFET, whereas the shallow well portions are arranged immediately below element isolation films surrounding the I type MOSFET, and function as channel stoppers.

Abstract: A structure and process are disclosed in which IC chip-containing layers are stacked to create electronic density. Each layer is formed by mechanically and electrically joining an IC-containing TSOP with an external leadframe. Each leadframe contains conductors which are disposed to connect with TSOP leads, transpose signals to other locations on the periphery of the TSOP, and/or connect with other layers in the stack. The TSOP/leadframe layers are stacked and joined, and the leadframe terminals of the lowest layer are disposed to facilitate connection with a PCB or other circuitry.

Abstract: The semiconductor device comprises a semiconductor substrate having an element region, an element isolation film formed on the semiconductor substrate so as to surround the element region, a gate portion crossing the element region and extending over the semiconductor substrate, the gate portion comprising at least a gate insulation film formed on the semiconcuctor substrate and a gate electrode formed on the gate insulation film, and source/drain regions formed on the surface of the element regions on both sides of the gate portion, wherein an upper surface of the element isolation film is formed in substantially the same plane as an upper surface of the gate portion.

Abstract: A method of fabricating a DRAM cell and the DRAM cell include a substrate, and a bit line formed in a first direction on the substrate. A channel region is then formed on a portion of the bit line. The channel region has a lateral surface extending vertically from the bit line. A first insulating layer is formed over the substrate, excluding the channel region, and is formed on at least a portion of the lateral surface of the channel region. A gate electrode is formed on a portion of the first insulating layer, which is on the portion of the lateral surface of the channel region, and a word line, connected to the gate electrode, is formed in a second direction on the first insulating layer. A second insulating layer is then formed over a portion of the substrate. The second insulating layer has a contact hole which exposes the channel region. Next, a capacitor is formed on a portion of the second insulating layer and on the channel region via the contact hole.

Abstract: An n.sup.- well region is formed at a surface of a semiconductor substrate. A MOS transistor of high breakdown voltage having a drain region and a source region is formed at the surface of the n.sup.- well region. The n.sup.- well region has an impurity concentration peak right below the drain region. Accordingly, a semiconductor device having a high breakdown voltage insulation gate type field effect transistor that can suppress increase of a depletion layer when high voltage is applied across the drain, that can reduce the electric field intensity across the drain, and that has superior breakdown voltage, and a fabrication method thereof, are obtained.

Abstract: A MOS device and method of fabricating the same, wherein the source/drain region has polysilicon trench structure which are formed by self-alignment using silicon oxide layers as masks. The source/drain regions extend to the field oxide layer and/or above the gate. Therefore, contacts can be formed on source/drain conductive regions above the field oxide layer.

Abstract: Disclosed in a microwave integrated circuit, having a semiconductor substrate on which a field effect transistor is formed, a micro strip line, a contact hole and an interconnecting line. The microstrip line comprises a ground conductor, a signal line and a dielectric film interposed between the ground conductor and the signal line, and it is laminated on the semiconductor substrate. The contact hole is formed in the micro strip line so that the dielectric film above the field effect transistor is removed, and the interconnecting line is provided in the contact hole for connecting the field effect transistor with the ground conductor or signal line of the micro strip line.

Abstract: An integrated circuit memory device includes a semiconductor substrate having a memory cell area and a select transistor area. A first field insulation layer is included in the memory cell area, and a first channel stop impurity layer is included beneath the first field insulation layer. The first channel stop impurity layer is narrower than the first field insulation area. A second field insulation layer is included in the select transistor area, and a second channel stop impurity layer is included beneath the second field insulation layer. The second channel stop impurity layer is wider than the second field insulation layer. Integrated circuit memory devices are fabricated by defining a memory cell area and a select transistor area of a semiconductor substrate. The memory cell area includes a memory cell active area and a memory cell field area. The select transistor area includes a select transistor active area and a select transistor field area.

Abstract: A semiconductor device includes a flat, square n-type diffusion layer, a p-type channel stopper region, and an electrode. The n-type diffusion layer is formed to be isolated in a check element region of a p-type semiconductor substrate or a p-type well covered with a field oxide film and having circuit element regions and the check element region sandwiched therebetween. The p-type channel stopper region is formed to contact at least one side of the n-type diffusion layer. The electrode is extracted from the n-type diffusion layer through a contact hole. The n-type diffusion layer, the p-type channel stopper region, and the electrode constitute the check element for checking a state of the p-type channel stopper region by measuring a junction breakdown voltage of the n-type diffusion layer.

Abstract: The semiconductor device according to the present invention includes a semiconductor substrate of a first conductive type. A well area of the first conductive type is formed in the substrate. The well area has higher concentration of impurity than that of the substrate. The well area includes a first element. The first element is of a second conductive type different from the first conductive type. A second element of the second conductive type formed in the substrate. The first element is isolated from the second element by a field oxide.

Abstract: This invention describes a device structure and a method of forming the device structure using trenches with sidewalls formed in the substrate of an integrated circuit. A highly doped polysilicon layer is formed on the walls of the trench or the trench is filled with highly doped polysilicon to form the source and drain of a field effect transistor in an integrated circuit. The invention provides reduced source and drain resistance. The capacitances between the gate and source and the gate and drain are reduced as well.

Abstract: A semiconductor device includes a field insulating film, a channel stopper, and a diffusion layer. The field insulating film is formed on one major surface of a semiconductor substrate of a first conductivity type to surround an element region. The channel stopper of the first conductivity type is formed immediately below the field insulating film. The diffusion layer of an opposite conductivity type is formed to be adjacent to the channel stopper. The impurity concentration peak position of the diffusion layer substantially coincides with that of the channel stopper.

Abstract: A method for forming trench isolation and in specific shallow trench isolation(STI) using SiO.sub.2 plugs is proposed. The SiO.sub.2 plugs of the STI have a buried phosphorus (P) rich layer introduced during and subsequent to the trench formation to tie up any sodium ionic contamination from processes prior to gate formation. P impurity layer is formed below the surface of the deposited SiO.sub.2 layer. A preferred method for forming the buried P layer is by shallow implantation in a vertical direction into the deposited SiO.sub.2 layer prior to planarization. The process is self aligned to the trench isolation regions.

Abstract: A high current power transistor is provided that comprises a drain region that includes a highly-doped drain region (54) and a lightly-doped drain region (50). The channel region (52) is activated by a gate conductor (32). The channel region separates the lightly-doped drain region (50) from a D-well region (40). A sidewall insulator body (44) is used to form the lightly-doped drain region (50) and the lightly-doped drain region (54). The transistor is formed in an active region (20) which comprises a portion of an n-type epitaxial layer (12) formed outwardly from a p-type substrate (10). The isolation structures (14) and (16) as well as the epitaxial layer (12) provides for a transistor that can be used in both source follower and common source configurations.

Abstract: A process for producing integrated circuits including the steps of: selectively growing field insulating regions of insulating material extending partly inside a substrate having a given type of conductivity; depositing a polycrystalline silicon layer on the substrate; shaping the polycrystalline silicon layer through a mask; and selectively implanting ions of the same conductivity type as the substrate, using the shaping mask, through the field insulating regions. The implanted ions penetrate the substrate and form channel stopper regions beneath the field insulating regions.

Abstract: Disclosed is a semiconductor device, which has: a first device-separating insulating film which is formed on a semiconductor substrate and extends in a first(Y) direction; a second device-separating insulting film which is formed on said semiconductor substrate and extends in a second(X) direction normal to the first(Y) direction; a first-conductivity-type device region which is formed on the semiconductor substrate and is sectioned by the first and second device-separating insulating films; and a first first-conductive-type high concentration impurity layer which is formed under the first device-separating insulating film and extends in the first(Y) direction; wherein the second device-separating insulating film is connected with the first device-separating insulating film through an insulating film thinner than both the first and second device-separating insulating films, the thin insulating film extending over the first high concentration impurity layer to separate the device region arranged in the second(

Abstract: A field oxide structure having a reduced number of defects is described. A field oxide mask is formed over a substrate having openings which expose portions of the substrate where the field oxide structures are to be formed. Silicon nitride spacers are formed on the sidewalls of the openings. Channel stop ions are selectively implanted through the opening into the substrate and then the thick field oxide structures are formed. Stress-generated crystalline defects are formed underlying the field oxidation regions at the edges of the openings. The silicon nitride spacers are removed. An additional source/drain ion implantation is performed by implanting ions to doped regions in the substrate deep enough into the substrate so that the crystalline defects are enclosed within the implanted regions to reduce junction leakage. The silicon dioxide, silicon nitride, and pad silicon oxide layers are removed to complete the field oxide structure.

Abstract: A semiconductor device having an SOI structure which involves no parasitic MOS transistor and substrate floating effect and has a planar element isolation region and, a manufacturing method therefor. In the semiconductor device, a field shield gate composed of an oxide film and a field shield gate electrode is formed to be buried under an SOI layer. As a result, it is possible to prevent generation of a parasitic transistor and substrate floating effects inherent in field shield gate while obtaining a planar element isolation structure.

Abstract: The present invention discloses a structure of a transistor in a semiconductor device and a method of manufacturing the same.The present invention manufactures a high voltage transistor by etching a silicon substrate to a depth deeper than that of the field oxide film by a self-aligned wet etching process using the field oxide film as a mask and, thereafter, by forming the first gate electrode which electrically switches ON and OFF between the source region and the drain region by using a gate electrode mask and simultaneously forming a second gate electrode to prevent a junction breakdown below the bird's beak of the field oxide film.Accordingly, the present invention can improve the degree of integration of the device by forming a gate electrode to prevent a junction breakdown below the bird's beak of the field oxide film.

Abstract: Disclosed is a semiconductor memory device which has memory cell transistors each comprising a liner source diffusion layer, a land-shaped drain diffusion layer, a gate oxide film containing a floating gate formed on the channel region between those diffusion layers, and a control gate formed on the gate oxide film. Trenches are formed in the substrate in no contact with the channel regions to isolate the cell transistors from each other.

Abstract: The present invention provides a MOS field effect transistor comprising: a semiconductor substrate having a first conductivity type; source/drain regions of a second conductivity type; lightly doped regions covering the bottom of the source/drain regions and surrounding the source/drain regions, the lightly doped regions having the second conductivity type and a lower impurity concentration than an impurity concentration of the source/drain regions; an off-set region surrounding the lightly doped regions, the off-set region having the first conductivity type, the off-set region having a lower impurity concentration than the impurity concentration of the lightly doped regions; and a channel stopper region having the first conductivity type, the channel stopper region having a higher impurity concentration than the impurity concentration of the off-set region, the channel stopper region surrounding the off-set region, the channel stopper region having projected portions under a gate electrode, the projected por

Abstract: A termination structure (located along a transistor perimeter or a die edge) for a trenched MOSFET or other semiconductor device prevents the undesirable surface channelling phenomena without the need for any additional masking steps to form a channel stop. This structure is especially applicable to P-channel MOSFETs. In the prior art a mask defines a doped channel stop. Instead here, a blanket ion implantation of P-type ions is performed after the active area masking process. Thus this doped channel stop termination is in effect masked during fabrication by the field oxide. In another version the channel stop termination is an additional trench formed in the termination region of the MOSFET. The trench is conventionally lined with oxide and filled with a conductive polysilicon field plate which extends to the edge of the die. In another version, the doped and trenched channel stops are used in combination. The channel stops are enhanced by provision of field plates overlying them on the die surface.

Abstract: The concentration of impurities at the surface of the semiconductor device adjacent and under the bird's beak of a field oxide region is reduced by employing sidewall spacers prior to field implantation. The resulting semiconductor device exhibits reduced sidewall junction capacitance and leakage, an increased junction breakdown voltage and a reduced narrow channel effect.

Abstract: A semiconductor device has an inherent region of the same conductivity type and the same impurity concentration as a semiconductor substrate and well regions located close to each other under a main surface of the semiconductor substrate. A field oxide film is selectively formed on the main surface. A MOSFET, termed an "undoped MOSFET," is formed in the inherent region. A carrier stop layer having a conductivity type opposite to, and an impurity concentration higher than, that of the inherent region is formed within the inherent region. The carrier stop layer extends from the bottom of the field oxide film and underlies the source/drain regions of the undoped MOSFET in spaced relationship therewith. The carrier stop layer prevents punch-through between the well region and densely diffused source/drain regions in the undoped MOSFET region, even when they are located close to each other.

Abstract: A trench is formed on a main surface of a p+ type monocrystalline silicon substrate. A silicon oxide film is formed extending from the inner surface of trench onto the main surface of p+ type monocrystalline silicon substrate. The thickness of a corner portion positioned on the upper end corner portion of the sidewall of trench in silicon oxide film is larger than the thickness of silicon oxide film positioned on the sidewall of trench. An n type polycrystalline silicon layer extending from the inside of trench onto the main surface of p+ type monocrystalline silicon substrate is formed on silicon oxide film. Thus, a semiconductor device having a trench structure with an improved breakdown voltage for an insulating layer positioned on an upper end corner portion of the sidewall of a trench is obtained.

Abstract: A multi-channel type intelligent power IC which solves the problems of parasitic transistor and increase in an area of isolation region, both of which are inherent problem in a pn junction isolation substrate. The power IC also enhances heat-radiation performance. An n type first semiconductor substrate and p type second semiconductor substrate are directly bonded, and a buried oxide film is formed in a portion of a bonding interface thereof. Subsequently, a plurality of isolation trenches are formed and the first semiconductor substrate is separated into an SOI isolation region and a pn isolation region. Logic elements are then formed in the SOI isolation region, and power elements are formed in the pn isolation region. In the case wherein two or more logic elements are hereby formed, the logic elements are isolated by isolation trenches. In the case wherein two or more power elements are formed, a parasitic current extracting portion is formed between mutual power elements.

Abstract: A method for forming field oxide regions on an integrated circuit device includes the steps of providing doped regions for formation of active devices. After the doped regions have been formed, a thick field oxide layer is grown over the entire surface of the device. Field oxide regions are then defined using masking and anisotropic etching steps which provide approximately vertical sidewalls for the field oxide regions, and which do not result in the formation of bird's beaks. Since the active regions are defined prior to formation of the field oxide regions, the active regions extend under the field oxide regions and do not give rise to edge effects.

Abstract: A semiconductor device has a nobel configuration. The device includes a semiconductor substrate, element isolation regions formed on the main surface of the semiconductor substrate and at least one element region formed on the main surface of the semiconductor substrate and enclosed by the element isolation regions. In the device, the depth of each trench from the main surface to the bottom of the semiconductor substrate is shallow at a region where the trench width is less than a specified length, and it is deep at a region where the trench width is larger than the specified length.

Abstract: A buried oxide film 4 is formed on a main surface of a silicon substrate 1. An SOI layer 5 is formed on buried oxide film 4. Channel stop regions 22a and 22b respectively connected to channel regions of an nMOS 2 and a pMOS 3 are formed in an element isolation region of SOI layer 5. nMOS 2 and pMOS 3 are formed in an element formation region of SOI layer. A concentration of a p type impurity or an n type impurity included in channel stop regions 22a and 22b is higher than a concentration of the p type impurity or the n type impurity included in the channel region of nMOS 2 or the channel region of pMOS 3. An FS gate 16 is formed on channel stop regions 22a and 22b with an FS gate oxide film 15 interposed therebetween. Therefore, a semiconductor device having an SOI structure which is capable of suppressing a parasitic bipolar operation by drawing out efficiently excessive carriers stored in the channel region of transistor can be obtained.

Abstract: A CMOS memory cell array, and a process for making it, that avoids problems caused by LOCOS isolation of cells. Moats are formed by etching away columns of a thick field oxide layer. The moats have two-tiered sidewalls, such that an upper tier is sloped, and a lower tier is more vertical. This approach provides the advantages of sloped sidewalls, but avoids filament problems. After the moats are formed, subsequent fabrication steps may be in accordance with conventional fabrication techniques for CMOS arrays.

Abstract: In a semiconductor device having an element isolation region including a LOCOS type field oxide film formed in a surface of a silicon substrate and a U-trench isolation region provided in the silicon substrate, the U-trench isolation region is constituted with a U-trench provided such that it penetrates the field oxide film, a channel stopper provided in a portion of the silicon substrate exposed on a bottom face of the U-trench, a first film in a form of a silicon oxide film formed by thermal oxidation of an exposed portion of the silicon substrate in the U-trench, a second film comprising a buried layer having thermal reflow characteristics and burying the U-trench, a third film having non-thermal reflow characteristics and having a top face substantially coplanar with a top face of the field oxide film and a bottom face connected to a top face of the second films and a fourth film in a form of an insulating film connected to the top face of the third film at an upper end of said U-trench and covering the U

Abstract: The present invention is a CMOS epitaxial silicon wafer (50) on which CMOS integrated circuits (16) can be manufactured, including such circuits that include bipolar components (referred to as "BiCMOS" circuits). The CMOS wafer includes a lightly doped monocrystalline silicon substrate (56) having a major surface (54) that supports a lightly doped monocrystalline epitaxial silicon layer (52). The substrate includes a heavily doped diffused layer (58) extending a short distance (64) into the substrate from the major surface toward a lightly doped bulk portion (66) of the substrate. CMOS integrated circuits manufactured on the epitaxial layer of the CMOS wafer of this invention have a low susceptibility to latch-up. The low susceptibility is provided by the relatively low resistivity of the diffused layer. Since the diffused layer is relatively thin and the bulk portion is lightly doped, the oxygen content of the bulk can be readily measured and controlled.

Abstract: A nonvolatile storage device is provided with at least one stacked poly gate structure formed on the substrate and disposed between a first trench and a second trench. The trenches each having two walls. A first doped area having a first conductivity type extending along the wall of the first trench and a second doped area having a second conductivity type extending along the wall of the second trench. The first doped area and the second doped area having heights greater than widths, the heights being parallel to the trench walls and the widths being perpendicular thereto. The trench walls are lined with a metal silicide to decrease resistivity.

Abstract: An improvement for a semiconductor device in which memory elements and logic elements are formed on the same substrate is disclosed. The semiconductor device is formed so that a concentration of the field inversion preventive layer below the field oxide film within the region where memory elements are formed is higher than a concentration of the field inversion preventive layer below the field oxide film within the region where logic elements are formed.