Abstract: A semiconductor device includes a gate region, a source/drain region and an insulating layer between the gate region and the source/drain region. The source/drain region includes a first leg extending in a first direction, a second leg extending in parallel with the first leg, and a third leg connected between the first leg and the second leg.

Abstract: A semiconductor structure is provided including a strained silicon germanium alloy fin that can be employed as a channel material for a FinFET device and having a gate spacer including a lower portion that fills in a undercut region that lies adjacent to the strained silicon germanium alloy fin and beneath raised source/drain (S/D) structures and silicon pedestal structures that can provide improved overlay capacitance.

Abstract: An alignment mark in a process surface of a semiconductor layer includes a groove with a minimum width of at least 100 ?m and a vertical extension in a range 100 nm to 1 ?m. The alignment mark further includes at least one fin within the groove at a distance of at least 60 ?m to a closest one of inner corners of the groove.

Abstract: A method of forming a III-V semiconductor vertical fin is provided. The method includes forming a fin mandrel on a substrate, forming a spacer layer on the substrate surrounding the fin mandrel, forming a wetting layer on each of the sidewalls of the fin mandrel, forming a fin layer on each of the wetting layers, removing the fin mandrel, removing the wetting layer on each of the fin layers, and forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers.

Abstract: Semiconductor structure is provided. An exemplary semiconductor structure includes a semiconductor substrate including fin structures. The fin structures include a plurality of first fin structures having a first width and a plurality of second fin structures. The second fin structure has a second width at a lower portion and a third width at an upper portion, and the second width is greater than each of the first width and the third width. The semiconductor structure includes a first isolation film formed on the semiconductor substrate and between adjacent fin structures. The first isolation film has a top surface lower than the fin structures. The upper portion of each second fin structure having the third width passes through the top surface of the first isolation film.

Abstract: A structure for use in a fin of a FinFET includes a hard mask formed on a substrate. The hard mask has an opening with at least a portion of the substrate exposed therein. The structure also includes a buffer formed on the portion of the substrate exposed within the hard mask, and multiple channels formed on the substrate proximate to respective sides of the opening.

Abstract: The present application provides a thin film transistor, a method for fabricating the same, a method for driving the same, and a display device. The thin film transistor includes a gate pattern, a gate insulation layer, an active layer pattern, a source/drain pattern, and a passivation layer. The active layer pattern is made of a carbon nanotube material, and the passivation layer is made of a charge-resistant material capable of reducing mobile charges on a surface of the carbon nanotube material.

Abstract: Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

Abstract: A high output and high speed electronic device having low cost and high productivity is disclosed. The copper halide semiconductor based electronic device, includes a substrate, a copper halide channel layer formed on the substrate, an insulating layer formed on the copper halide channel layer, a gate electrode formed on the insulating layer, a first n+copper halide layer formed on the copper halide channel layer to be disposed at a first side of the gate electrode, the first n+copper halide layer comprising n-type impurities, a drain electrode formed on the first n+copper halide layer, a second n+copper halide layer formed on the copper halide channel layer to be disposed at a second side of the gate electrode, which is opposite to the first side, the second n+copper halide layer comprising n-type impurities, and a source electrode formed on the second n+copper halide layer.

Abstract: A cell, in a semiconductor device, including: first and second active areas in a semiconductor substrate on opposite sides of the first axis; first, third and fifth, and correspondingly collinear second, fourth and sixth, having long axes in a second direction perpendicular to the first direction; the (A) first, third and fifth, and (B) second, fourth and sixth, conductive structures correspondingly overlapping the second active area; the first and second conductive structures correspondingly being centered between the (C) third and fifth, and (D) fourth and sixth, conductive structures; and a seventh conductive structure; the fourth conductive structure being located over first and second gaps between corresponding ones of the third through sixth, conductive structures; and the fourth conductive structure occupying an area which substantially overlaps one of the first and second conductive structures and a corresponding one of the first and second gaps.

Abstract: A neuromorphic device is provided. The neuromorphic device may include a pre-synaptic neuron; a row line extending in a row direction from the pre-synaptic neuron; a post-synaptic neuron; a column line extending in a column direction from the post-synaptic neuron; and a synapse disposed at an intersection between the row line and the column line. The synapse may include a first synapse layer including a plurality of first carbon nano-tubes; a second synapse layer including a plurality of second carbon nano-tubes having different structures from the plurality of first carbon nano-tubes; and a third synapse layer including a plurality of third carbon nano-tubes having different structures from the plurality of first carbon nano-tubes and the plurality of second carbon nano-tubes.

Abstract: High-mobility semiconductor fins are formed on an insulator layer using techniques allowing precise control of fin heights. Lattice-matched fins are grown epitaxially on sidewalls of an essentially defect-free portion of a semiconductor template. The fins are formed within laterally extending trenches in a top dielectric layer, the thickness of which determines fin height. The trenches extend orthogonally to the template. Epitaxial overgrowth above the top dielectric layer is removed by planarization. The fin template and top dielectric layer are removed, leaving sets of parallel fins on the insulator layer. The fin template can be replaced by an isolation region for electrically isolating sets of fins.

Abstract: A fin field effect transistor and fabrication method are provided. The method includes: providing a base substrate, initial first fins on the base substrate, and an initial isolation layer covering a portion of sidewalls of the initial first fins; etching the initial first fins using the initial isolation layer as a mask, to form first grooves in the initial isolation layer; forming first fins by forming a filling material film in the first grooves; and etching back the initial isolation layer to form an isolation layer covering a portion of sidewalls of the first fins. A material of the first fins has a thermal conductivity greater than a thermal conductivity of a material in the base substrate.

Abstract: To easily assess a feedback capacitance of a semiconductor element. An assessment method of assessing a feedback capacitance of a semiconductor element is provided, the assessment method including: acquiring a first characteristic correlated with the feedback capacitance and a second characteristic correlated with the feedback capacitance; and assessing the feedback capacitance based on the first characteristic and the second characteristic. The first characteristic may be a characteristic that corresponds to a withstanding voltage of the semiconductor element, and the second characteristic may be an on-resistance of the semiconductor element. In the assessing, the feedback capacitance may be assessed based on a ratio between the first characteristic and the second characteristic.

Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.

Abstract: A semiconductor device includes a substrate including active patterns, a device isolation layer filling a trench between a pair of adjacent active patterns, a gate electrode on the active patterns, and a gate contact on the gate electrode. Each active pattern includes source/drain patterns at opposite sides of the gate electrode. The gate contact includes a first portion vertically overlapping with the gate electrode, and a second portion laterally extending from the first portion such that the second portion vertically overlaps with the device isolation layer and does not vertically overlap with the gate electrode. A bottom surface of the second portion is distal to the substrate in relation to a bottom surface of the first portion. The bottom surface of the second portion is distal to the substrate in relation to a top of a source/drain pattern that is adjacent to the second portion.

Abstract: A layout of a semiconductor device, a semiconductor device and a method of forming the same, the semiconductor device include a first fin and a second fin disposed on a substrate, a gate and a spacer. The first fin and the second fin both include two opposite edges, and the gate completely covers the two opposite edges of the first fin and only covers one sidewall of the two opposite edges of the second fin. The spacer is disposed at two sides of the gate, and the spacer covers another sidewall of the two opposite edges of the second fin.

Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.

Abstract: Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).

Abstract: A semiconductor device implementing a field plate is disclosed. The semiconductor device includes electrodes of a source, a gate, and a drain; an insulating film covering at least the drain electrode; a field plate that includes a first part overlapping with the gate electrode and a second part not overlapping with the gate electrode; and a source interconnect connected with the source electrode. A feature of the semiconductor device of the invention is that both of the first part and the second part are electrically connected with the source interconnection.

Abstract: Embodiments of RF amplifiers and packaged RF amplifier devices each include a transistor with a drain-source capacitance that is relatively low, an input impedance matching circuit, and an input-side harmonic termination circuit. The input impedance matching circuit includes a harmonic termination circuit, which in turn includes a first inductance (a first plurality of bondwires) and a first capacitance coupled in series between the transistor output and a ground reference node. The input impedance matching circuit also includes a second inductance (a second plurality of bondwires), a third inductance (a third plurality of bondwires), and a second capacitance coupled in a T-match configuration between the input lead and the transistor input. The first and second capacitances may be metal-insulator-metal capacitors in an integrated passive device.

Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.

Abstract: A semiconductor device includes a substrate, wherein the substrate includes a channel region. The semiconductor device further includes an isolation feature in the substrate. The isolation feature includes a first portion in the substrate, and a second portion extending along a top surface of the substrate. The second portion partially covers the channel region. The semiconductor device further includes a gate structure over the substrate, wherein the gate structure partially covers the second portion of the isolation feature.

Abstract: Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a plurality of semiconductor fins patterned in a starting semiconductor substrate; a set of gate structures formed on the starting semiconductor substrate; a set of spacers formed around each of the set of gate structures; a source and drain region grown around the plurality of fins; a conductive metal material on the source and drain region, an insulating material is configured to be deposited over an upper surface of the conductive metal material and the gate structure; and a plurality of contacts in the insulator material. The plurality of contacts is formed such that a bottom surface of the plurality of contacts is in contact with at least a portion of the upper surface of the gate structure.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.

Abstract: A silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the silicon fin into a silicon germanium alloy fin. In some embodiments, the silicon germanium alloy fin has a wide upper portion and a narrower lower portion. In such an embodiment, the wide upper portion has a greater germanium content than the narrower lower portion. In other embodiments, the silicon germanium alloy fin has a narrow upper portion and a wider lower portion. In this embodiment, the narrow upper portion of the silicon germanium alloy fin has a greater germanium content than the wider lower portion of the silicon germanium alloy fin.

Abstract: A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate. A second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure. A same geometry for the first and second epitaxial material of the first and second source/drain regions provides a symmetrical device.

Abstract: The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.

Abstract: A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.

Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes providing a substrate having a fin extending from the substrate. An in-situ doped layer is formed on the fin. By way of example, the in-situ doped layer may include an in-situ doped well region formed by an epitaxial growth process. In some examples, the in-situ doped well region includes an N-well or a P-well region. After formation of the in-situ doped layer on the fin, an undoped layer is formed on the in-situ doped layer, and a gate stack is formed over the undoped layer. The undoped layer may include an undoped channel region formed by an epitaxial growth process. In various examples, a source region and a drain region are formed adjacent to and on either side of the undoped channel region.

Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view.

Abstract: Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.

Abstract: A method for forming a semiconductor device is provided. In this method, a stop layer is formed on a semiconductor substrate. A semiconductor fin is formed on the stop layer. Two cells adjacent to each other are formed on the semiconductor fin. A gate conductor is formed on a top of the semiconductor fin at a common boundary that is shared by the two cells. A gate spacer is formed to peripherally enclose the gate conductor. The gate conductor and the semiconductor fin are etched to form a gap extending from the top of the semiconductor fin to the stop layer, thereby dividing the semiconductor fin into two portions of the semiconductor fin. The gap is filled with a dielectric filler.

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.

Abstract: A method of forming a finFET SRAM and related device, are provided. Embodiments include forming a plurality of silicon fins in a substrate; and forming a gate over each of the fins, wherein all of the fins are diagonally skewed in a single direction relative to the gates, and all of the gates extend in a single direction relative to the respective fins.

Abstract: An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. Agate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.

Abstract: Methods for doping a sub-fin region of a semiconductor structure include providing a semiconductor structure that comprises a substrate and a plurality of fins formed on the substrate, the plurality of fins having sub-fin regions adjacent to the substrate; removing the substrate to expose a portion of the sub-fin regions of the plurality of fins, and implanting a dopant material into the exposed portion of the sub-fin region. The method may also include performing an annealing process after the implantation such that the dopant becomes electrically active. The method may also include patterning the backside of the semiconductor structure. Devices constructed using the disclosed methods are also provided, and other embodiments are discussed.

Abstract: A semiconductor device includes a substrate, an isolation structure over the substrate, two fins over the substrate and protruding out of the isolation structure, and an epitaxial feature over the two fins. The epitaxial feature includes two lower portions and one upper portion. The two lower portions are over the two fins respectively. The upper portion is over the two lower portions and connects the two lower portions. The upper portion has a different dopant concentration than the two lower portions. A top surface of the upper portion is substantially flat.

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having an embedded bottom metal contact. A semiconductor fin is formed on a doped region of a substrate. A portion of the doped region adjacent to the semiconductor fin is recessed and an embedded contact is formed on the recessed portion. A material of the conductive rail is selected such that a conductivity of the embedded contact is higher than a conductivity of the doped region.

Abstract: A semiconductor device may include an active fin, an element isolation film on a lower portion of the active fin and a gate structure crossing over the active fin. The gate structure may include first and second sides. The device may also include a source region and a drift region adjacent the first and second sides of the gate structure, respectively. The drift region may have a first impurity concentration. The device may further include a drain region that is in the drift region and may have a second impurity concentration higher than the first impurity concentration, a first trench that is in the drift region and may have a depth less than a height of the active fin, and an upper embedded insulating layer in the first trench. The gate structure may overlap a portion of the drift region and a portion of the first trench.

Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.

Abstract: A method includes forming a crown structure over a substrate; forming fins in the crown structure; forming an intra-device isolation region between the fins and forming inter-device isolation regions on opposing sides of the crown structure; forming a gate structure over the fins; forming a dielectric layer that extends continuously over the inter-device isolation regions, the fins and the intra-device isolation region; performing an etching process to reduce a thickness of the dielectric layer, where after the etching process, upper surfaces of the inter-device isolation regions and upper surfaces of the fins are exposed while an upper surface of the intra-device isolation region is covered by a remaining portion of the dielectric layer; and forming an epitaxial structure over the exposed upper surfaces of the fins, where after the epitaxial structure is formed, there is a void between the epitaxial structure and the intra-device isolation region.

Abstract: An embodiment is a method including forming a first fin in a first region of a substrate and a second fin in a second region of the substrate, forming a first isolation region on the substrate, the first isolation region surrounding the first fin and the second fin, forming a first dummy gate over the first fin and a second dummy gate over the second fin, the first dummy gate and the second dummy gate having a same longitudinal axis, replacing the first dummy gate with a first replacement gate and the second dummy gate with a second replacement gate, forming a first recess between the first replacement gate and the second replacement gate, and a filling an insulating material in the first recess to form a second isolation region.

Abstract: A method of manufacturing a bipolar junction transistor (BJT) structure is provided. Pattern etching through a second semiconductor layer and recessing a silicon germanium layer are performed to form a plurality of vertical fins each including a silicon germanium pattern, a second semiconductor pattern and a hard mask pattern sequentially stacked on a first semiconductor layer above a substrate. First spacers are formed on sidewalls of the plurality of vertical fins. Exposed silicon germanium layer above the first semiconductor layer is directionally etched away. A germanium oxide layer is conformally coated to cover all exposed top and sidewall surfaces. Condensation annealing followed by silicon oxide strip is performed. The first spacers, remaining germanium oxide layer and the hard mask pattern are removed. A dielectric material is deposited to isolate the plurality of vertical fins.

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a spacer integration scheme for both NFET and PFET devices and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for NFET devices having sidewall spacers of a first dimension; and a plurality epitaxial grown fin structures for PFET devices having sidewall spacers of the first dimension.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device by forming a channel fin over a substrate, wherein the channel fin includes a plurality of channel fins, wherein a first spacing is defined between adjacent ones of a first set of the plurality of channel fins, wherein a second spacing is defined between adjacent ones of a second set of the plurality of channel fins, wherein the first spacing is not equal to the second spacing. An initial gate structure is formed over the plurality of channels. Formed along sidewalls of the initial gate structure are spacers that each has a predetermined spacer height, wherein a thickness of each of the spacers is insufficient to allow any one of the spacers to fill the first spacing or the second spacing. Portions of the initial gate structure that are not covered by the spacers are removed.

Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a plurality of fins comprising a first fin, a second fin, a third fin, a fourth fin and a fifth fin, each of the plurality of protruding from the substrate in a first direction, and spaced apart from one another in a second direction that intersects the first direction and a plurality of trenches comprising a first trench, a second trench, a third trench and a fourth trench, each of the plurality of trenches being formed between adjacent fins of the plurality of fins, wherein variation of a first width of the first trench and a third width of the third trench is smaller than a first variation, wherein variation of a second width of the second trench and a fourth width of the fourth trench is smaller than a second variation, and wherein the second variation is greater than the first variation.