Abstract: Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in source/drain regions on fin portions. The fin portions can be located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions can be oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.

Abstract: A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.

Abstract: A method for fabricating an SRAM includes forming a plurality of first fin structures, a plurality of second fin structures, and an isolation layer. Each first fin structure is adjacent to a second fin structure and includes a first replacement region exposed by the isolation layer. The method includes forming pull down (PD) transistors, including forming PD gate structures to partially cover the first fin structures; forming a fin sidewall film on sidewall surfaces of each first replacement region; forming a first PD dielectric layer, exposing each first replacement region, to cover sidewall surfaces of the fin sidewall film; removing the first replacement region and the fin sidewall film on sidewall surfaces of the first replacement region; and forming a first source/drain doped layer. The method also includes forming adjacent transistors, including forming a second source/drain doped layer in the second fin structures adjacent to the first source/drain doped layer.

Abstract: A technique relates to a semiconductor device. A source or drain (S/D) contact liner is formed on one or more S/D regions. Annealing is performed to form a silicide layer around the one or more S/D regions, the silicide layer being formed at an interface between the S/D contact liner and the S/D regions. A block layer is formed into a pattern over the one or more S/D regions, such that a portion of the S/D contact liner is protected by the block layer. Unprotected portions of the S/D contact liner are removed, such that the S/D contact liner protected by the block layer remains over the one or more S/D regions. The block layer and S/D contacts are formed on the S/D contact liner over the one or more S/D regions.

Abstract: A technique relates to a semiconductor device. A trench is formed in a space structured to accommodate at least two dummy gates in a cell, the space structured to accommodate the at least two dummy gates aligning to another two gates in another cell, the space further including an area previously occupied by a portion of fins. Dielectric material is formed in the space, such that the dielectric material in the space in the cell aligns to the another two gates in the another cell.

Abstract: A method for processing a substrate is provided. The method comprises forming a patterned photoresist over a first material, the patterned photoresist comprising island portions and shaped spaces surrounding the island portions. An area of each of the island portions is reduced to enlarge the shaped spaces, which are filled with a second material. The island portions are removed to form first openings in the second material. Portions of the first material exposed through the first openings are removed to form second openings in the first material. Portions of a substrate exposed through the second openings are removed to form holes in the substrate. Methods of patterning a substrate and methods of forming a hole pattern in a substrate are also disclosed.

Abstract: Device structures and fabrication methods for a field-effect transistor. A semiconductor fin includes a first section and a second section in a lengthwise arrangement, a first gate structure overlapping the first section of the semiconductor fin, and a second gate structure overlapping the second section of the semiconductor fin. A pillar is arranged in the first section of the semiconductor fin. The pillar extends through a height of the semiconductor fin and across a width of the semiconductor fin.

Abstract: A method for manufacturing an electrostatic discharge (ESD) protection device includes providing a semiconductor structure including a semiconductor substrate including a first region of a first conductivity type and a semiconductor fin on the semiconductor substrate; forming an electrode on the semiconductor fin; and performing a doping process on the semiconductor structure to forming a second region in the first region, the second region having a second conductivity type opposite the first conductivity type to form a pn junction in the semiconductor substrate. Since the pn junction is formed in the semiconductor substrate, it has a relatively large area to prevent local hot spots from occurring when a current flows through the ESD protection device, thereby reducing performance degradation of a semiconductor device.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a switch with local silicon on insulator (SOI) and deep trench isolation structures and methods of manufacture. The structure a structure comprises an air gap located under a device region and bounded by an upper etch stop layer and deep trench isolation structures.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate cut mask having one cut window exposing one or more portions of multiple sacrificial gate structures of the at least one plurality of sacrificial gate structures. The multiple sacrificial gate structures having been formed over portions of in structures. The method comprises forming a gate cut mask a plurality of semiconductor fins and a plurality of sacrificial gate structures. The gate cut mask being formed with one cut window exposing one or more portions of multiple sacrificial gate structures of the plurality of sacrificial gate structures. At least the portion of multiple sacrificial gate structures and one or more portions of each semiconductor fin of the plurality of semiconductor fins underlying the one or more portions of one of the multiple sacrificial gate structures are removed.

Abstract: Techniques for forming contact over active gate free of metal recess are provided. In one aspect, a method for forming a COAG device includes: forming gates over an active area of a wafer; forming source and drains on opposite sides of the gates; burying the gates in an ILD; forming source/drain contacts in the ILD between the gates; depositing a sacrificial metal selectively on the source/drain contacts with first gaps present in the sacrificial metal over the gates; filling the first gaps with a first dielectric material to form gate caps over the gates; selectively removing the sacrificial metal which forms second gaps between the gate caps over the source/drain contacts; and filling the second gaps with a second dielectric material to form source/drain caps over the source/drain contacts. A COAG device is also provided.

Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin structure on a substrate, in which the fin structure includes a fin stack of alternating first and second semiconductor layers and forming recesses in the fin stack at source and drain regions. The method also includes etching the second semiconductor layers to form recessed second semiconductor layers, and forming third semiconductor layers on sidewalls of the recessed second semiconductor layers. The method further includes epitaxially growing source and drain structures in the recesses, removing the recessed second semiconductor layers to form spaces between the first semiconductor layers, and oxidizing the third semiconductor layers to form inner spacers. In addition, the method includes forming a gate structure to fill the spaces and to surround the first semiconductor layers.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a substrate. The substrate includes an active region and a blank region disposed adjacent to the active region. The method also includes forming a fin material layer on the substrate. Further, the method includes forming a plurality of fins on the active region, and a plurality of dummy fins on the blank region by etching the fin material layer. A spacing between a fin and an adjacent dummy fin is greater than a spacing between adjacent fins.

Abstract: A semiconductor device includes a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other, an isolation pattern disposed between the first and second active regions, a semiconductor extension layer disposed between the first and second active regions, a first source/drain semiconductor layer disposed on the first active region, and a second source/drain semiconductor layer disposed on the second active region. The facing side surfaces of the first and second active regions are closer to the semiconductor extension layer than the isolation pattern.

Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.

Abstract: An integrated circuit device includes a substrate from which a plurality of fin-type active regions protrude, the plurality of fin-type active regions extending in parallel to one another in a first direction, and a plurality of gate structures and a plurality of fin-isolation insulating portions extending on the substrate in a second direction crossing the first direction and at a constant pitch in the first direction, wherein a pair of fin-isolation insulating portions from among the plurality of fin-isolation insulating portions are between a pair of gate structures from among the plurality of gate structures, and the plurality of fin-type active regions include a plurality of first fin-type regions and a plurality of second fin-type regions.

Abstract: A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.

Abstract: A semiconductor device includes a semiconductor substrate, a first standard cell including a first active region and a second active region, and a power switching circuit including a first switching transistor electrically connected between a first interconnect and a second interconnect over the semiconductor substrate, and including a first buffer connected to a gate of the first switching transistor, the first buffer including a third active region and a fourth active region, and wherein the first buffer adjoins, in a plan view, the first standard cell in a first direction, wherein an arrangement of the first active region matches an arrangement of the third active region in a second direction different from the first direction, and wherein an arrangement of the second active region matches an arrangement of the fourth active region in the second direction.

Abstract: A method includes forming a first fin protruding above a substrate, the first fin having a PMOS region; forming a first gate structure over the first fin in the PMOS region; forming a first spacer layer over the first fin and the first gate structure; and forming a second spacer layer over the first spacer layer. The method further includes performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the first fin in the PMOS region; and epitaxially growing a first source/drain material over the first fin in the PMOS region, the first source/drain material extending along the top surface and the sidewalls of the first fin in the PMOS region.

Abstract: A method of fabricating a semiconductor device may include forming a fin structure on a substrate; forming an interface film having a first thickness on the fin structure using a first process; forming a gate dielectric film having a second thickness on the interface film using a second process different from the first process; and densifying the gate dielectric film using a third process different from the first and second processes. The second thickness may be greater than the first thickness, and the first thickness of the interface film may be unchanged after the densifying of the gate dielectric film.

Abstract: An embodiment includes an apparatus comprising: first and second semiconductor fins that are parallel to each other; a first gate, on the first fin, including a first gate portion between the first and second fins; a second gate, on the second fin, including a second gate portion between the first and second fins; a first oxide layer extending along a first face of the first gate portion, a second oxide layer extending along a second face of the second gate portion, and a third oxide layer connecting the first and second oxide layers to each other; and an insulation material between the first and second gate portions; wherein the first, second, and third oxide layers each include an oxide material and the insulation material does not include the oxide material. Other embodiments are described herein.

Abstract: The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

Abstract: A method includes following steps. A semiconductor fin is formed on a substrate and extends in a first direction. A source/drain region is formed on the semiconductor fin and a first interlayer dielectric (ILD) layer over the source/drain region. A gate stack is formed across the semiconductor fin and extends in a second direction substantially perpendicular to the first direction. A patterned mask having a first opening is formed over the first ILD layer. A protective layer is formed in the first opening using a deposition process having a faster deposition rate in the first direction than in the second direction. After forming the protective layer, the first opening is elongated in the second direction. A second opening is formed in the first ILD layer and under the elongated first opening. A conductive material is formed in the second opening.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region and a second well region that have different conductivity types and are adjacent to each other. A first fin structure protrudes from the semiconductor substrate and is formed in the first well region. A second fin structure protrudes from the semiconductor substrate and is formed in the second well region and adjacent to the first fin structure. A first multi-step isolation structure that includes a first isolation portion is formed between the first fin structure and the second fin structure. A second isolation portion extends from the bottom surface of the first isolation portion. The second isolation portion has a top width that is narrower than the bottom width of the first isolation portion.

Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.

Abstract: Embodiments described herein include radio frequency (RF) switches. In general, the embodiments described herein selectively bias the output terminals of one or more switching transistors in the RF switch. Such coupling can provide a bias that significantly reduces the effects of gate-lag. In one embodiment, the RF switch includes an antenna node, a first input/output (I/O) node, a second I/O node, a field-effect transistor (FET), a FET stack, and a bias coupling circuit. In this embodiment the bias coupling circuit electrically couples a gate terminal of the FET to one or more FET output terminals of the FET stack to provide a bias voltage to the output terminal(s).

Abstract: Methods and systems for generating an identifier includes testing an operational characteristic for each device in an array of pairs of devices. Each pair of devices includes a first device and a second device. The first device of each pair has a higher inter-device uniformity for the operational characteristic than the second device of the pair. The operational characteristic between the first device and the second device is compared for each pair of devices to generate a respective identifier bit for each pair of devices. An identifier is generated from the identifier bits.

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of fins formed from a substrate, at least one liner segment formed along a portion of the substrate, a first dielectric layer formed on the substrate and bounded by the liner segment, and a second dielectric layer formed within an interior of the liner segment.

Abstract: A semiconductor device according to an example embodiment of the present inventive concept includes a substrate having a first region and a second region horizontally separate from the first region; a first gate line in the first region, the first gate line including a first lower work function layer and a first upper work function layer disposed on the first lower work function layer; and a second gate line including a second lower work function layer in the second region, the second gate line having a width in a first, horizontal direction equal to or narrower than a width of the first gate line in the first direction, wherein an uppermost end of the first upper work function layer and an uppermost end of the second lower work function layer are each located at a vertical level higher than an uppermost end of the first lower work function layer with respect to a second direction perpendicular to the first direction.

Abstract: An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and spanning from the first dielectric gate to the second dielectric gate. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region.

Abstract: A semiconductor structure includes semiconductor fins protruding out of a substrate, dielectric fins protruding out of the substrate and disposed among the semiconductor fins, and gate stacks disposed over the semiconductor fins and the dielectric fins. The dielectric fins include a first dielectric material layer, a second dielectric material layer disposed over the first dielectric material layer, and a third dielectric material layer disposed over the second dielectric material layer, where the first and second dielectric material layers have different compositions and the first and the third dielectric material layers have the same compositions.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom portion, an intermediate portion disposed over the bottom portion and an upper portion disposed over the intermediate portion is formed. The intermediate portion is removed at a source/drain region of the fin structure, thereby forming a space between the bottom portion and the upper portion. An insulating layer is formed in the space. A source/drain contact layer is formed over the upper portion. The source/drain contact layer is separated by the insulating layer from the bottom portion of the fin structure.

Abstract: In one example, a fin field effect transistor including a single diffusion break with a multi-layer dummy gate is disclosed. One example of field effect transistor includes a first transistor array comprising a first active gate, a second transistor array comprising a second active gate, and a single diffusion break formed between the first transistor array and the second transistor array, wherein the single diffusion break comprises a dummy gate comprising multiple layers of different materials.

Abstract: An embodiment is a method of manufacturing a semiconductor device. The method includes forming a fin on a substrate. A gate structure is formed over the fin. A recess is formed in the fin proximate the gate structure. A gradient doped region is formed in the fin with a p-type dopant. The gradient doped region extends from a bottom surface of the recess to a vertical depth below the recess in the fin. A source/drain region is formed in the recess and on the gradient doped regions.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.

Abstract: A semiconductor device including a substrate having a fin structure surrounded by a trench isolation region; a trench disposed in the fin structure; an interlayer dielectric layer disposed on the substrate; a working gate striding over the fin structure and on the first side of the trench; a dummy gate striding over the fin structure and on the second side of the trench; a doped source region in the fin structure; and a doped drain region in the fin structure. The dummy gate is disposed between the trench and the doped drain region. The fin structure extends along a first direction and the dummy gate extends along a second direction. The first direction is not parallel with the second direction.

Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.

Abstract: The semiconductor structure includes a semiconductor substrate having active regions; field-effect devices disposed on the semiconductor substrate, the field-effect devices including gate stacks with elongated shape oriented in a first direction; a first metal layer disposed over the gate stacks, the first metal layer including first metal lines oriented in a second direction being orthogonal to the first direction; a second metal layer disposed over the first metal layer, the second metal layer including second metal lines oriented in the first direction; and a third metal layer disposed over the second metal layer, the third metal layer including third metal lines oriented in the second direction. The first, second, and third metal lines have a first thickness T1, a second thickness T2, and t a third thickness T3, respectively. The second thickness is greater than the first thickness and the third thickness.

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a first dielectric layer over the base portion and a first sidewall of the fin portion. The method includes forming a first spacer layer over the first dielectric layer. The method includes forming a first dielectric fin over the first spacer layer. The method includes forming an epitaxial structure over the fin portion, wherein a void is surrounded by the epitaxial structure, the first dielectric layer, and the first spacer layer. The method includes removing the first spacer layer between the epitaxial structure and the first dielectric fin. The method includes forming a silicide layer over the epitaxial structure, wherein a first lower portion of the silicide layer covers a lower surface of the epitaxial structure and is in the void.

Abstract: Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of etching steps. For example, a first anisotropic dry etch is performed, a second isotropic dry etch is performed, and a third wet etch is performed. In some embodiments, the second isotropic etch removes a residual portion of a metal gate layer including a metal containing layer. In some embodiments, the third etch removes a residual portion of a dielectric layer.

Abstract: The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material.

Abstract: A semiconductor structure includes a substrate, a plurality of parallel fins extending above the substrate, a plurality of gate structures perpendicular to the plurality of fins and including a plurality of sidewall spacers, and a plurality of source-drain regions intermediate the plurality of gate structures. A liner of a silicon-containing material is deposited over outer surfaces of the plurality of gate structures; over the liner, an inter-layer dielectric material is deposited. The semiconductor substrate with the deposited liner of silicon-containing material and deposited inter-layer dielectric material is annealed to at least partially consume the liner of silicon-containing material into the inter-layer dielectric material, to control residual stress such that resultant gate structures following the annealing have an aspect ratio range of 3:1 to 10:1, and are uniform in range to within seven percent of a target critical dimension.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over a top of the fin and laterally adjacent sidewalls of the fin. An N-type gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin, the N-type gate electrode comprising a P-type metal layer on the gate dielectric layer, and an N-type metal layer on the P-type metal layer. A first N-type source or drain region is adjacent a first side of the gate electrode. A second N-type source or drain region is adjacent a second side of the gate electrode, the second side opposite the first side.

Abstract: The invention provides a semiconductor device. The semiconductor device includes a gate structure over fin structures arranged in parallel. Each of the fin structures has a drain portion and a source portion on opposite sides of the gate structure. A drain contact structure is positioned over the drain portions of the fin structures. A source contact structure is positioned over the source portions of the fin structures. A first amount of drain via structures is electrically connected to the drain contact structure. A second amount of source via structures is electrically connected to the source contact structure. The sum of the first amount and the second amount is greater than or equal to 2, and the sum of the first amount and the second amount is less than or equal to two times the amount of fin structures.

Abstract: A display panel with reduced power consumption is described. An example of the display panel includes an array of light emitting elements that are controllable to form an image, and a Thin-Film-Transistor (TFT) backplane comprising circuitry to drive the array of light emitting elements. The TFT backplane includes a plurality of field effect transistors (FETs). Each FET includes a source electrode, a drain electrode, a channel layer contacting the source electrode and the drain electrode, and a gate electrode adjacent to the channel layer and separated from the channel layer by an insulator. The channel layer includes a layer of metal phosphide.

Abstract: A semiconductor device is formed to include a fin structure, a first trench at a first lateral end of the fin, a second trench at a second lateral end of the fin, and a filler filled on a first traverse side of the fin and a second traverse side of the fin. The filler is contained between the first trench and the second trench, and oxidized in-place to cause a stress to be exerted on the first and second traverse sides of the fin, the stress causing the fin to exhibit a tensile strain in a lateral running direction of the fin.