Abstract: A semiconductor structure includes a substrate, a plurality of parallel fins extending above the substrate, a plurality of gate structures perpendicular to the plurality of fins and including a plurality of sidewall spacers, and a plurality of source-drain regions intermediate the plurality of gate structures. A liner of a silicon-containing material is deposited over outer surfaces of the plurality of gate structures; over the liner, an inter-layer dielectric material is deposited. The semiconductor substrate with the deposited liner of silicon-containing material and deposited inter-layer dielectric material is annealed to at least partially consume the liner of silicon-containing material into the inter-layer dielectric material, to control residual stress such that resultant gate structures following the annealing have an aspect ratio range of 3:1 to 10:1, and are uniform in range to within seven percent of a target critical dimension.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over a top of the fin and laterally adjacent sidewalls of the fin. An N-type gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin, the N-type gate electrode comprising a P-type metal layer on the gate dielectric layer, and an N-type metal layer on the P-type metal layer. A first N-type source or drain region is adjacent a first side of the gate electrode. A second N-type source or drain region is adjacent a second side of the gate electrode, the second side opposite the first side.

Abstract: The invention provides a semiconductor device. The semiconductor device includes a gate structure over fin structures arranged in parallel. Each of the fin structures has a drain portion and a source portion on opposite sides of the gate structure. A drain contact structure is positioned over the drain portions of the fin structures. A source contact structure is positioned over the source portions of the fin structures. A first amount of drain via structures is electrically connected to the drain contact structure. A second amount of source via structures is electrically connected to the source contact structure. The sum of the first amount and the second amount is greater than or equal to 2, and the sum of the first amount and the second amount is less than or equal to two times the amount of fin structures.

Abstract: A display panel with reduced power consumption is described. An example of the display panel includes an array of light emitting elements that are controllable to form an image, and a Thin-Film-Transistor (TFT) backplane comprising circuitry to drive the array of light emitting elements. The TFT backplane includes a plurality of field effect transistors (FETs). Each FET includes a source electrode, a drain electrode, a channel layer contacting the source electrode and the drain electrode, and a gate electrode adjacent to the channel layer and separated from the channel layer by an insulator. The channel layer includes a layer of metal phosphide.

Abstract: A semiconductor device is formed to include a fin structure, a first trench at a first lateral end of the fin, a second trench at a second lateral end of the fin, and a filler filled on a first traverse side of the fin and a second traverse side of the fin. The filler is contained between the first trench and the second trench, and oxidized in-place to cause a stress to be exerted on the first and second traverse sides of the fin, the stress causing the fin to exhibit a tensile strain in a lateral running direction of the fin.

Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

Abstract: Described examples include microelectronic devices and integrated circuits with an active first circuit in a first segment of a first wafer, a second circuit in a second segment of the first wafer, and second and third wafers bonded to different surfaces of the first wafer to provide first and second cavities with surfaces spaced from the first segment. An opening extends through the first wafer between the first and second cavities to separate portions of the first and second segments and to form a sealed cavity that surrounds the first segment. A bridge segment of the first wafer supports the first segment in the sealed cavity and includes one or more conductive structures to electrically connect the first and second circuits.

Abstract: A semiconductor device includes a fin extending from an upper surface of a substrate, a gate stack disposed over the fin, a first dielectric material disposed on a sidewall of the gate stack, an epitaxy region disposed adjacent the fin, a second dielectric material disposed on the epitaxy region and on a sidewall of the first dielectric material, wherein the second dielectric material has a greater thickness in a first portion over the epitaxy region than in a second portion over the epitaxy region disposed closer to the substrate than the first portion, a third dielectric material disposed on the second dielectric material, and a conductive feature extending through the third dielectric material and the second dielectric material to contact the epitaxy region.

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate, an isolation feature between and adjacent to the first fin and the second fin, and a fin isolation structure between the first fin and the second fin. The fin isolation structure includes a first insulating layer partially embedded in the isolation feature, a second insulating layer having sidewall surfaces and a bottom surface that are covered by the first insulating layer, a first capping layer covering the second insulating layer and having sidewall surfaces that are covered by the first insulating layer, and a second capping layer having sidewall surfaces and a bottom surface that are covered by the first capping layer.

Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.

Abstract: A method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and forming a fin structure in the NFET region. The fin structure includes a first layer having a first semiconductor material, and a second layer under the first layer and having a second semiconductor material different from the first semiconductor material. The method further includes forming a patterned hard mask to fully expose the fin structure in gate regions of the NFET region and partially expose the fin structure in at least one source/drain (S/D) region of the NFET region. The method further includes oxidizing the fin structure not covered by the patterned hard mask, wherein the second layer is oxidized at a faster rate than the first layer. The method further includes forming an S/D feature over the at least one S/D region of the NFET region.

Abstract: A semiconductor device includes a substrate, a dielectric region, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The plurality of conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and is electrically connected to a first conductive region of the plurality of conductive regions. The conductive structure is arranged to penetrate through the substrate and formed under the first conductive rail. The conductive structure is electrically connected to the first conductive rail.

Abstract: A semiconductor device including a first fin pattern and a second fin pattern, which are in parallel in a lengthwise direction; a first trench between the first fin pattern and the second fin pattern; a field insulating film partially filling the first trench, an upper surface of the field insulating film being lower than an upper surface of the first fin pattern and an upper surface of the second fin pattern; a spacer spaced apart from the first fin pattern and the second fin pattern, the spacer being on the field insulating film and defining a second trench, the second trench including an upper portion and an lower portion; an insulating line pattern on a sidewall of the lower portion of the second trench; and a conductive pattern filling an upper portion of the second trench and being on the insulating line pattern.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights.

Abstract: A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrate forming an interfacial layer over the nanosheets depositing a high-k dielectric layer conformally on the interfacial layer. The method also includes depositing a layer of silicon nitride (SiN) above the high-k dielectric layer and performing reliability anneal after depositing the layer of SiN to crystalize the high-k dielectric layer.

Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include performing a fin cut by removing a first fin section of the plurality of fins and a first portion of the STI material, and forming a second STI material over a second fin section of the plurality of fins, wherein the second fin section is left remaining following removal of the first fin section. The method may further include recessing the STI material and the second STI material, forming a spin-on-carbon (SOC) layer over the semiconductor device, and implanting the STI material and the second STI material through the SOC layer.

Abstract: A semiconductor structure and fabrication method are provided. The method includes: providing a substrate; forming first fins on the substrate; forming barrier layers covering sidewalls of the first fins; forming a first groove in each first between the adjacent first barrier layers; and forming a first inner epitaxial layer in each first groove. The first fin and the adjacent first barrier layers surround the corresponding first groove.

Abstract: An integrated circuit device includes a first fin separation insulating portion over the first device region; a pair of first fin-type active regions apart from each other with the first fin separation insulating portion therebetween and collinearly extending in a first horizontal direction; a first dummy gate structure vertically overlapping the first fin separation insulating portion; a second fin separation insulating portion apart from the first fin separation insulating portion and arranged over the second device region; and a plurality of second fin-type active regions apart from each other with the second fin separation insulating portion therebetween in the second device region and collinearly extending in the first horizontal direction, wherein a vertical level of a lowermost surface of the second fin separation insulating portion is equal to or lower than a vertical level of a lowermost surface of the first fin separation insulating portion.

Abstract: A semiconductor structure, a method for fabricating the semiconductor structure, and a static random access memory are provided. The method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate. The substrate includes a pass gate transistor region. The method also includes forming a gate structure across a length portion of each fin, covering top and sidewall surfaces of each fin, and on each fin. Further, the method includes forming pass gate doped regions in the fin on both sides of the gate structure in the pass gate transistor region. At least one of the pass gate doped regions is formed by performing an ion-doped non-epitaxial layer process on the fin.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming a gate structure on a base substrate and forming a first dielectric layer on the base substrate. The first dielectric layer has a top lower than the gate structure and exposes a sidewall portion of the gate structure. The method also includes forming an isolation sidewall spacer on the exposed sidewall portion of the gate structure.

Abstract: Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

Abstract: Techniques for reducing off-state current in dual channel CMOS devices are provided. In one aspect, a method for forming a dual channel finFET includes: patterning NFET/PFET fins on a wafer from a first channel material and a second Ge-containing channel material; depositing a GeO2 layer on the fins; annealing the fins to selectively oxidize the at least one PFET fin; depositing a liner onto the fins which induces a negative charge in the PFET fin(s); removing unreacted GeO2 and the liner from the NFET fin(s); depositing a dielectric layer onto the fins which induces a positive charge in the NFET fin(s). A dual channel finFET device is also provided.

Abstract: A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.

Abstract: An ESD protection semiconductor device is disclosed. The ESD protection semiconductor device includes a substrate and a gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins are formed in the substrate respectively at two sides of the gate set. At least a first doped fin is formed in the substrate at one side of the gate set the same as the source fins. A plurality of isolation structures are formed in one of the drain fins to define at least a second doped fin in the one of the drain fins. The source fins and the drain fins are of a first conductivity type. The first doped fin is of a second conductivity type that is complementary to the first conductivity type. The first doped fin and the second doped fin are electrically connected to each other.

Abstract: An integrated circuit device includes a substrate including a first device region and a second device region; a first fin separation insulating portion on the first device region; a pair of first fin-type active regions spaced from each other with the first fin separation insulating portion therebetween in the first device region and collinearly extending in a first horizontal direction; a second fin separation insulating portion extending in a second horizontal direction over the first device region and the second device region; and a pair of second fin-type active regions spaced from each other with the second fin separation insulating portion therebetween and collinearly extending in the first horizontal direction, wherein the first fin separation insulating portion and the second fin separation insulating portion vertically overlap each other.

Abstract: A semiconductor device includes a first contact positioned on an externally accessible surface of the semiconductor device and electrically coupled with a first structure in the semiconductor device, a second contact positioned on an externally accessible surface and electrically coupled with a second structure in the semiconductor device, and an isolation structure disposed between the first contact and the second contact, the isolation structure self-aligning with a first surface of the first contact such that the first surface of the first contact is orthogonal to the externally accessible surface up to a depth and faces the second contact.

Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

Abstract: A semiconductor device includes a fin-like structure extending along a first axis; a first source/drain feature disposed at a first end portion of the fin-like structure; and a constraint layer disposed at a first side of the first end portion of the fin-like structure, wherein the first source/drain feature comprises a first portion, disposed at the first side, the first portion comprising a shorter extended width along a second axis, and a second portion, disposed at a second side that is opposite to the first side, the second portion comprising a longer extended width along the second axis.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, at least two spacer layers are formed around a first fin of the plurality of fins, and a single spacer layer is formed around a second fin of the plurality of fins. The at least two spacer layers include a first spacer layer including a first material and a second spacer layer including a second material different from the first material. The single spacer layer includes the second material. The method also includes selectively removing part of the first spacer layer to expose part of the first fin, and epitaxially growing a source/drain region around the exposed part of the first fin.

Abstract: A method includes providing metal gate structures in a first and a second region, respectively, of a semiconductor substrate, simultaneously cutting the metal gate structures by a two-step etching process to form a first and a second trench in metal gate structures of the first and the second region, respectively, and filling each trench with an insulating material to form a first and a second gate isolation structure. Each step of the two-step etching process employs different etching chemicals and conditions. The metal gate structures in the first region and the second region differ in gate lengths and composition of gate electrode.

Abstract: A structure and a method of a semiconductor device structure are provided. The method includes forming a first fin structure, a second fin structure, and a third fin structure over a semiconductor substrate. The method includes forming first spacer elements over sidewalls of the first fin structure and the second fin structure and partially removing the first fin structure and the second fin structure. The method includes forming second spacer elements over sidewalls of the third fin structure and partially removing the third fin structure. The second spacer element is taller than the first spacer element. The method includes epitaxially growing a semiconductor material over the first fin structure, the second fin structure, and the third fin structure such that a merged semiconductor element is formed on the first fin structure and the second fin structure, and an isolated semiconductor element is formed on the third fin structure.

Abstract: Semiconductor device and fabrication method are provided. The method includes: providing a base substrate; forming an isolation structure film on the base substrate, a top portion of the isolation structure film containing a plurality of first openings; forming a second opening at a bottom of each first opening by removing a portion of the isolation structure film to expose a surface of the base substrate, where the second opening has a size larger than a corresponding first opening along a direction in parallel with the surface of the base substrate; forming fins in the first and second openings; and forming an isolation structure by removing a portion of an isolation material film, where a top surface of the isolation structure is lower than a top surface of the fins and the isolation structure covers a portion of the sidewalls of the fins. The semiconductor devices formed by the method may reduce the self-heating effect and improve the performance of semiconductor devices.

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

Abstract: A DC-AC converter is disclosed. The DC-AC converter generates an output AC signal, and has an input DC-AC converter which generates a first AC signal, a transformer device which receives the first AC signal and generates a second AC signal, and a first bidirectional switch which selectively connects a first transformer output terminal and a first output terminal. The DC-AC converter also has a first capacitor which powers the first bidirectional switch, a first charging circuit which charges the first capacitor, and a second bidirectional which selectively conduct connects a second transformer output terminal and a second output terminal. The DC-AC converter also has a second capacitor which powers the second bidirectional switch, and a second charging circuit which charges the second capacitor. Each of the bidirectional switches includes series connected transistors between first and second input/output terminals, and a transistor driver which drives the transistors.

Abstract: Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A body feature is formed that includes a sacrificial layer arranged vertically between the first and second nanosheet channel layers. The sacrificial layer is laterally recessed at a sidewall of the body feature to expose respective portions of the first and second nanosheet channel layers. A sacrificial spacer is formed by oxidizing a portion of the sacrificial layer at the sidewall of the body feature. Sections of a semiconductor material are epitaxially grown on the exposed portions of the first and second nanosheet channel layers to narrow a gap vertically separating the first and second nanosheet channel layers. The sacrificial spacer is removed to form a cavity between the sections of the semiconductor material and the sacrificial layer. A dielectric spacer is conformally deposited in the cavity.

Abstract: A method of forming a nanosheet device is provided. The method includes forming a plurality of narrow nanosheets on a first region of a substrate, and forming a plurality of wide nanosheets on a second region of the substrate. The method further includes forming an interfacial layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a dummy gate layer on the gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes forming a dummy cover layer on the dummy gate layer on the plurality of narrow nanosheets and the plurality of wide nanosheets.

Abstract: A method of generating a layout and manufacturing a semiconductor device, including receiving a design layout of a semiconductor device including active fins; extracting a design rule of the active fins from the design layout; forming fin lines overlapping the active fins such that the fin lines have a length that is greater than a length of the active fins, wherein the fin lines continuously extend from a position adjacent to one edge of a layout region of the semiconductor device toward another edge, and are formed in an entirety of the layout region of the semiconductor device; forming a mandrel pattern layout in an entirety of the layout region of the semiconductor device, using the fin lines; and forming a cut pattern layout in the entirety of the layout region of the semiconductor device, using the active fins.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure having a substrate and a semiconductor fin on the substrate, forming a dummy gate structure on the semiconductor fin, forming a first dielectric layer on the semiconductor structure exposing an upper surface of the dummy gate structure, removing the dummy gate structure and a portion of the semiconductor fin below the dummy gate structure to form a trench that divides the semiconductor fin into a first portion and a second portion spaced apart from each other, and forming a second dielectric layer on the semiconductor structure filling the trench. The method provides a semiconductor device having a non-recessed trench isolation structure.

Abstract: A method for providing a semiconductor device is described. The method provides a plurality of fins. A first portion of each of the plurality of fins is covered by a mask. A second portion of each of the plurality of fins is exposed by the mask. The method also performs an anneal in a volume-increasing ambient, such as hydrogen, at anneal temperature(s) above one hundred degrees Celsius and not more than six hundred degrees Celsius. The second portion of each of the fins is exposed during the anneal such that the second portion of each of the fins undergoes a volume expansion.

Abstract: A complementary metal-oxide-semiconductor (CMOS) transistor may include a first semiconductor structure and a gate stack on the first semiconductor structure. The gate stack may include a gate dielectric layer on the first semiconductor structure, a work function material on the gate dielectric layer, and a gate metal fill material on the work function material of the gate stack. The gate metal fill material may include a low resistivity carbon alloy. A dielectric fill material may be included on the gate stack.

Abstract: Some embodiments include a method of forming a pattern. A first layer is formed to extend over a photoresist feature and along sidewalls of the photoresist feature. The first layer is etched to form first features. The photoresist feature is removed. A second layer is formed to extend over the first features and along sidewalls of the first features. The second layer is etched to form second features. A third layer is formed to extend over the first and second features and along sidewalls of the second features. A fourth layer is spin-coated over the third layer. A portion of the fourth layer is removed from over the first and second features. Segments of the third layer remain along the sidewalls of the second features. Regions of the fourth layer remain as blocks adjacent the segments. The first features and the segments are removed to leave the pattern.

Abstract: A method of forming a semiconductor device may include providing a semiconductor device structure. The semiconductor device structure may include semiconductor fins pitched at a fin pitch on a substrate. The semiconductor device structure may include an isolation oxide layer on the substrate and between the semiconductor fins and a mask. The mask may be disposed over the isolation oxide layer and the mask may define at least one opening. The method may further comprise directing hot ions into the at least one opening, to implant hot ions in a volume of isolation oxide in the isolation oxide layer. The volume may be adjacent to at least one of the semiconductor fins.

Abstract: A transistor includes an active region bounded by an outer periphery and formed in a substrate. The active region includes sets of input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. The transistor further includes an input port, an output port, a first via connection disposed at the outer periphery of the active region proximate the input port and a second via connection disposed at the outer periphery of the active region proximate the output port. The second via connection has a noncircular cross-section with a second major axis and a second minor axis, the second major axis having a second major axis length, the second minor axis having a second minor axis length that is less than the second major axis length. The second major axis is oriented parallel to a longitudinal dimension of the input, output, and common fingers.

Abstract: A semiconductor structure includes a first region. The first region includes at least three first gate structures separate one from another and adjacent to each other and at least three second gate structures separate one from another and adjacent to each other. The first gate structures are further away from each other than the second gate structures. The first region further includes first epitaxial semiconductor features proximate the first gate structures and second epitaxial semiconductor features proximate the second gate structures. A first distance from the first epitaxial semiconductor features to the respective first gate structures is smaller than a second distance from the second epitaxial semiconductor features to the respective second gate structures.

Abstract: A display device is disclosed, which includes: a substrate; a first metal conductive layer disposed on the substrate; a semiconductor layer disposed on the first metal conductive layer; and a second metal conductive layer disposed on the semiconductor layer and including a data line, a first part and a second part separated from the first part, the data line with a data extending direction connected to the second part. A first extending direction is a direction that the first part extends toward the second part, a first region is a region that the first part overlaps the first metal conductive layer, the first part has a first maximum breadth outside the first region along the data extending direction and a second maximum breadth inside the first region along a direction substantially perpendicular to the first extending direction, and the first maximum breadth is greater than the second maximum breadth.

Abstract: A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided.

Abstract: Integrated circuit devices, such as fin-like field effect transistors, and methods of fabricating thereof are disclosed herein. An exemplary device includes a fin that includes a first semiconductor layer and a second semiconductor layer disposed on the first semiconductor layer. The second semiconductor layer includes a partially oxidized portion and a completely oxidized portion. A third semiconductor layer is disposed on the partially oxidized portion of the second semiconductor layer, where a source region and a drain region are defined in the third semiconductor layer. A fourth semiconductor layer is disposed on the completely oxidized portion of the second semiconductor layer, where a channel region is defined in the fourth semiconductor layer between the source region and the drain region defined in the third semiconductor layer. A gate structure is disposed over the channel region defined in the fourth semiconductor layer of the fin.

Abstract: A method of forming features of a finFET structure includes forming fins on a surface of a substrate. A first liner is formed around each fin and a shallow trench isolation region is formed around each fin. A dopant layer is implanted in each fin. A portion of the shallow trench isolation region is etched from each fin. A first portion of the structure is blocked and the first liner replaced with a second liner in a second portion of the structure.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.