Abstract: A semiconductor device includes a substrate partitioned into a cell region, a peripheral circuit region, and an interface region between the cell region and the peripheral circuit region. A guard ring is provided in the interface region of the substrate and surrounds the cell region. A first gate structure is in the cell region, and a second gate structure is in the peripheral circuit region.

Abstract: A semiconductor FinFET device in fabrication includes a semiconductor substrate and at least one semiconductor fin coupled to the substrate. Each of the semiconductor fins further include a single drain branch coupled to at least two source branches at a common area, with the two source branches acting together as a source. A channel area is situated in the common area. In one example, the single drain branch and two source branches are coupled at the common area to form a generally Y-shaped fin. Further fabrication to complete the FinFET may then proceed.

Abstract: A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a central conductive layer, a silicon nitride layer, a metal diffusion layer, a channel region, and a metal sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. A silicon nitride layer is formed on the central conductive layer. A metal diffusion layer is formed within the guard ring and the central conductive layer. Afterwards, a metal sputtering layer is formed, and the mask layer is partially exposed.

Abstract: An ultra high voltage MOS transistor device includes a substrate having a first conductivity type and a first recess formed thereon, a gate positioned on the first recess, and a pair of source region and drain region having a second conductivity type formed in two sides of the gate, respectively.

Abstract: A semiconductor device includes a drift region of a first doping type, a junction between the drift region and a device region, and a field electrode structure in the drift region. The field electrode structure includes a field electrode, a field electrode dielectric adjoining the field electrode, arranged between the field electrode and the drift region, and having an opening, and at least one of a field stop region and a generation region. The semiconductor device further includes a coupling region of a second doping type complementary to the first doping type. The coupling region is electrically coupled to the device region and coupled to the field electrode.

Abstract: An N type layer made of an N type epitaxial layer in which an N+ type drain layer etc are formed is surrounded by a P type drain isolation layer extending from the front surface of the N type epitaxial layer to an N+ type buried layer. A P type collector layer is formed in an N type layer made of the N type epitaxial layer surrounded by the P type drain isolation layer and a P type element isolation layer, extending from the front surface to the inside of the N type layer. A parasitic bipolar transistor that uses the first conductive type drain isolation layer as the emitter, the second conductive type N type layer as the base, and the collector layer as the collector is thus formed so as to flow a surge current into a ground line.

Abstract: An isolated device is formed in a substrate in which is formed a high voltage device. The isolated device includes: an isolated well formed in the substrate by a lithography process and an ion implantation process used in forming the high voltage device; a gate formed on the substrate; a source and a drain, which are located in the isolated well at both sides of the gate respectively; a drift-drain region formed beneath the substrate surface, wherein the gate and the drain are separated by the drift-drain region, and the drain is in the drift-drain region; and a mitigation region, which is formed in the substrate and has a shallowest portion located at least below 90% of a depth of the drift-drain region as measured from the substrate surface, wherein the mitigation region and the drift-drain region are defined by a same lithography process.

Abstract: A monolithic bidirectional switching device includes a drift layer having a first conductivity type and having an upper surface, and first and second vertical metal-oxide semiconductor (MOS) structures at the upper surface of the drift layer. The drift layer provides a common drain for the first and second vertical MOS structures. The first and second vertical MOS structures are protected by respective first and second edge termination structures at the upper surface of the drift layer. A monolithic bidirectional switching device according to further embodiments includes a vertical MOS structure at the upper surface of the drift layer, and a diode at the upper surface of the drift layer. The drift layer provides a drain for the vertical MOS structure and a cathode for the diode, and the vertical MOS structure and the diode are protected by respective first and second edge termination structures.

Abstract: An integrated circuit device includes a semiconductor body, active components formed over the semiconductor body, one or more seal rings surrounding the active components, and a signal line. One or more of the seal rings are configured to provide the primary return path for current flowing through the signal line.

Abstract: Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) having a high drain-to-body breakdown voltage. Discrete conductive field (CF) plates are adjacent to opposing sides of the drain drift region, each having an angled sidewall such that the area between the drain drift region and the CF plate has a continuously increasing width along the length of the drain drift region from the channel region to the drain region. The CF plates can comprise polysilicon or metal structures or dopant implant regions within the same semiconductor body as the drain drift region. The areas between the CF plates and the drain drift region can comprise tapered dielectric regions or, alternatively, tapered depletion regions within the same semiconductor body as the drain drift region. Also disclosed are embodiments of a method for forming an LEDMOSFET and embodiments of a silicon-controlled rectifier (SCR) incorporating such LEDMOSFETs.

Abstract: A semiconductor device includes a gate structure over a substrate, a source region in the substrate, where the source region is adjacent to the gate structure. Additionally, the semiconductor device includes a drain region in the substrate, where the drain region is adjacent to the gate structure. Moreover, the semiconductor device includes a first dislocation in the substrate between the source region and the drain region. Furthermore, the semiconductor device includes a second dislocation in the substrate between the source region and the drain region, where the second dislocation is substantially parallel to the first dislocation.

Abstract: Some embodiments include transistors having a channel region under a gate, having a source/drain region laterally spaced from the channel region by an active region, and having one or more dielectric features extending through the active region in a configuration which precludes any straight-line lateral conductive path from the channel region to the source/drain region. The dielectric features may be spaced-apart islands in some configurations. The dielectric features may be multi-branched interlocking structures in some configurations.

Abstract: The present invention is a finFET type semiconductor device using LDMOS features. The device includes a first portion of a substrate doped with a second doping type and has a first trench, second trench, and first fin. The second portion of the substrate with a first doping type includes a third trench and second fin. The second fin between the second and third trench covers a part the first portion and a part of the second portion of the substrate. A first segment of the second fin is between the second segment and second trench. A second segment covers a part of the second portion of the substrate and is between the first segment and third trench. A gate covering at least a part of the first segment and a part of the first portion and a part of the second portion of the substrate.

Abstract: Disclosed is a power device, such as power MOSFET, and method for fabricating same. The device includes an upper trench situated over a lower trench, where the upper trench is wider than the lower trench. The device further includes a trench dielectric inside the lower trench and on sidewalls of the upper trench. The device also includes an electrode situated within the trench dielectric. The trench dielectric of the device has a bottom thickness that is greater than a sidewall thickness.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, an isolation layer, and a guard ring layer of the second conductivity type. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer to be joined to the second semiconductor layer. The isolation layer surrounds a periphery of the third semiconductor layer and is deeper than the third semiconductor layer. The guard ring layer is provided between the third semiconductor layer and the isolation layer, adjacent to the third semiconductor layer, and deeper than the third semiconductor layer.

Abstract: A semiconductor device has a shield plate electrode short-circuited to a source electrode near the drain electrode. The shield plate electrode is connected to the source terminal electrode which has a VIA hole via the first line of air-bridge structure or overlay structure.

Abstract: The invention provides a stable oxide material system for a capacitor, electronic device or a memory device having an effective high-k value with an effective zero alpha while exhibiting low leakage current density. The stable oxide material comprises Mx-Si1-xO2, wherein the elements M & Si are mixed such that the insulator layer comprises staggered edge-linked SiO2-MO2 bonding chains to provide a stable 3-dimensional single crystal system.

Abstract: A body region (3) with a first type of electric conductivity is arranged at the upper surface (10) of a substrate (1) in a well (2), wherein a portion of the well that is not occupied by the body region has a second type of conductivity opposite the first type of conductivity. At the upper surface, a source region is arranged in the body region and a drain region is arranged in the well at a distance from the body region; the source region and the drain region both have the second type of conductivity. The body region is arranged underneath a surface area of the upper surface that has a border (7) with opposing first border sides (8). The well has a varying depth in the substrate. The depth of the well is smaller underneath the first border sides of the body region than in a portion of the body region that is spaced apart from the first border sides.

Abstract: A semiconductor device which provides compactness and enhanced drain withstand voltage. The semiconductor device includes: a gate electrode; a source electrode spaced from the gate electrode; a drain electrode located opposite to the source electrode with respect to the gate electrode in a plan view and spaced from the gate electrode; at least one field plate electrode located between the gate and drain electrodes in a plan view, provided over the semiconductor substrate through an insulating film and spaced from the gate electrode, source electrode and drain electrode; and at least one field plate contact provided in the insulating film, coupling the field plate electrode to the semiconductor substrate. The field plate electrode extends from the field plate contact at least either toward the source electrode or toward the drain electrode in a plan view.

Abstract: In one general aspect, an apparatus can include a plurality of trench metal-oxide-semiconductor field effect transistors (MOSFET) devices formed within an epitaxial layer of a substrate, and a gate-runner trench disposed around the plurality of trench MOSFET devices and disposed within the epitaxial layer. The apparatus can also include a floating-field implant defined by a well implant and disposed around the gate-runner trench.

Abstract: A semiconductor device includes a semiconductor body including an inner region, and an edge region, a first doped device region of a first doping type in the inner region and the edge region and coupled to a first terminal, and at least one second doped device region of a second doping type complementary to the first doping type in the inner region and coupled to a second terminal. Further, the semiconductor device includes a minority carrier converter structure in the edge region. The minority carrier converter structure includes a first trap region of the second doping type adjoining the first doped device region, and a conductor electrically coupling the first trap region to the first doped device region.

Abstract: An n well region and an n?region surrounding the n well region are provided in the surface layer of a p?silicon substrate. The n?region includes breakdown voltage regions in which high voltage MOSFETs are disposed. The n well region includes a logic circuit region in which a logic circuit is disposed. A p? opening portion is provided between a drain region of each high voltage MOSFET and the logic circuit region. An n buffer region used as load resistances is provided between a second pick-up region and the drain region. The p?opening portion is provided between the n buffer region and logic circuit region. By so doing, it is possible to realize a reduction in the area of chips, and provide a high voltage semiconductor device having a level shift circuit with a high switching response speed.

Abstract: A semiconductor device concerning an embodiment is provided with a semiconductor layer, an impurity-doped layer selectively formed on the semiconductor layer, and a drain electrode formed on the impurity-doped layer. The semiconductor device is further provided with a source electrode which is formed and isolated from the drain electrode, and a gate electrode which is formed between the source electrode and the drain electrode. The semiconductor device is provided with an insulating film which is formed between the gate electrode and the drain electrode, and a shielding plate which is formed on the insulating film and is electrically connected to the source electrode. At least a part of the shielding plate is formed above an extending portion of the impurity-doped layer which extends in the direction to the gate electrode from the drain electrode.

Abstract: A semiconductor device comprises a substrate provided with a doping of a first type, on which an electronic circuit is provided surrounded by a circuit portion of the substrate provided with a doping of a second type; at least one pad for connecting the electronic circuit to an external device outside the substrate, surrounded by a pad portion provided with a doping of the second type; a sensing device comprising a sensor portion of the substrate provided with a doping of the first type, for sensing a parameter forming a measure for a local electrical potential of the substrate; and an evaluation unit connected to the sensing device, for providing an evaluation signal based on a difference between the parameter and a reference value.

Abstract: A power semiconductor device includes a cell region on a semiconductor substrate, at least a transistor device in the cell region, a peripheral termination region encompassing the cell region, a plurality of epitaxial islands arranged around the cell region, and a grid type epitaxial layer in the peripheral termination region. The grid type epitaxial layer separates the plurality of epitaxial islands from one another.

Abstract: A semiconductor device includes an active section for a main current flow and a breakdown withstanding section for breakdown voltage. An external peripheral portion surrounds the active section on one major surface of an n-type semiconductor substrate. The breakdown withstanding section has a ring-shaped semiconductor protrusion, with a rectangular planar pattern including a curved section in each of four corners thereof, as a guard ring. The ring-shaped semiconductor protrusion has a p-type region therein, is sandwiched between a plurality of concavities deeper than the p-type region, and has an electrically conductive film across an insulator film on the surface thereof. Because of this, it is possible to manufacture at low cost a breakdown withstanding structure with which a high breakdown voltage is obtained in a narrow width, wherein there is little drop in breakdown voltage, even when there are variations in a patterning process of a field oxide film.

Abstract: A semiconductor rectifier device includes a semiconductor substrate of a first conductive type of a wide gap semiconductor; a semiconductor layer of the first conductive type of the wide gap semiconductor formed on an upper surface of the semiconductor substrate, wherein an impurity concentration of the semiconductor layer is between 1E+14 atoms/cm3 and 5E+16 atoms/cm3 inclusive, and a thickness thereof is 8 ?m or more; a first semiconductor region of the first conductive type of the wide gap semiconductor formed at the semiconductor layer surface; a plurality of second semiconductor regions of a second conductive type of the wide gap semiconductor formed as sandwiched by the first semiconductor regions, wherein a width of each of the second semiconductor regions is 15 ?m or more; a first electrode formed on the first and second semiconductor regions; and a second electrode formed on a lower surface of the semiconductor substrate.

Abstract: Among other things, one or more semiconductor devices and techniques for forming such semiconductor devices are provided. The semiconductor device comprises a strip-ground field plate. The strip-ground field plate is connected to a source region of the semiconductor device and/or a ground plane. The strip-ground field plate provides a release path for a gate edge electric field. The release path directs an electrical field away from a gate region of the semiconductor device. In this way, breakdown voltage and gate charge are improved.

Abstract: An insulating layer, an undoped first GaN layer and an AlGaN layer are laminated in this order on a surface of a semiconductor substrate. A surface barrier layer formed by a two-dimensional electron gas is provided in an interface between the first GaN layer and the AlGaN layer. A recess (first recess) which reaches the first GaN layer but does not pierce the first GaN layer is formed in a surface layer of the AlGaN layer. A first high withstand voltage transistor and a control circuit are formed integrally on the aforementioned semiconductor substrate. The first high withstand voltage transistor is formed in the first recess and on a surface of the AlGaN layer. The control circuit includes an n-channel MOSFET formed in part of the first recess, and a depression type n-channel MOSFET formed on a surface of the AlGaN layer.

Abstract: A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions. Alternatively, the isolation region can be configured to collect holes that are generated in the transistor device. The isolation region may simultaneously achieve both of these functions.

Abstract: A semiconductor device includes a semiconductor layer with a super junction structure including first columns of a first conductivity type and second columns of a second conductivity type opposite the first conductivity type. The super junction structure is formed in a cell area and in an inner portion of an edge area surrounding the cell area. In the inner portion of the edge area a reverse blocking capability is locally reduced by a local modification of the semiconductor layer. The local modification allows an electric field to extend in case an avalanche breakdown occurs. The reverse blocking capability is locally reduced in the edge area, wherein once an avalanche breakdown has been triggered the semiconductor device accommodates a higher reverse voltage. Avalanche ruggedness is improved.

Abstract: Disclosed is a semiconductor component, including: a drift zone arranged between a first and a second connection zone; a channel control layer of an amorphous semi-insulating material arranged adjacent to the drift zone.

Abstract: A semiconductor device including a cell region and a peripheral region, the semiconductor device comprising: a guard ring region provided between the cell region and the peripheral region, the guard ring region having a barrier structure.

Abstract: A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in a region near the body zone and a second thickness in a region near the drift zone.

Abstract: A semiconductor device using one or more guard rings includes a p-type guard ring region surrounding a pn junction region, an insulating film covering the p-type guard ring region, one or more conductive films electrically connected with the p-type guard ring region through one or more contact holes made in the insulating film, and a semi-insulating film covering the insulating film and the conductive films. Thus, a desired breakdown voltage characteristic can be ensured even if a foreign matter or the like adheres to a surface of the conductive films.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

Abstract: A drift layer forms a first main surface of a silicon carbide layer and has a first conductivity type. A source region is provided to be spaced apart from the drift layer by a body region, forms a second main surface, and has the first conductivity type. A relaxing region is provided within the drift layer and has a distance Ld from the first main surface. The relaxing region has a second conductivity type and has an impurity dose amount Drx. The drift layer has an impurity concentration Nd between the first main surface and the relaxing region. Relation of Drx>Ld·Nd is satisfied. Thus, a silicon carbide semiconductor device having a high breakdown voltage is provided.

Abstract: A tunneling field effect transistor and a method for fabricating the same are provided. The tunneling field effect transistor includes: a semiconductor substrate and a drain layer formed in the semiconductor substrate, in which the drain layer is first type heavily doped; an epitaxial layer formed on the drain layer, with an isolation region formed in the epitaxial layer; a buried layer formed in the epitaxial layer, in which the buried layer is second type lightly doped; a source formed in the buried layer, in which the source is second type heavily doped; a gate dielectric layer formed on the epitaxial layer, and a gate formed on the gate dielectric layer; and a source metal contact layer formed on the source, and a drain metal contact layer formed under the drain layer.

Abstract: A semiconductor device containing an extended drain MOS transistor with an integrated snubber formed by forming a drain drift region of the MOS transistor, forming a snubber capacitor including a capacitor dielectric layer and capacitor plate over the extended drain, and forming a snubber resistor over a gate of the MOS transistor so that the resistor is connected in series between the capacitor plate and a source of the MOS transistor.

Abstract: A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the device region is provided, an align trench is formed in the outer region, a dummy trench is formed in the device region, an epi layer is formed over a top surface of the semiconductor substrate and within the dummy trench, a current path changing part is formed over the epi layer, and a gate electrode is formed over the current path changing part. When the epi layer is formed, a current path changing trench corresponding to the dummy trench is formed over the epi layer, and the current path changing part is formed within the current path changing trench.

Abstract: A semiconductor device includes a p-type semiconductor layer, n-type column regions formed of columnar thermal donors exhibiting an n-type property, a p-type column region interposed between the n-type column regions, the n-type column regions configured to form a super-junction structure in cooperation with the p-type column region, a channel region formed in the semiconductor layer, a source region formed in the channel region, a gate insulator film formed on the semiconductor layer, and a gate electrode formed on the gate insulator film and opposite to the channel region across the gate insulator film.

Abstract: The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate with a p-type conductivity, a buried layer with an n-type conductivity provided on the semiconductor substrate, a back gate layer with a p-type conductivity provided on the buried layer, a drain layer with an n-type conductivity provided on the back gate layer, a source layer with an n-type conductivity provided spaced from the drain layer, a gate electrode provided in a region immediately above a portion of the back gate layer between the drain layer and the source layer, and a drain electrode in contact with a part of an upper surface of the drain layer. A thickness of the drain layer in a region immediately below a contact surface between the drain layer and the drain electrode is half a total thickness of the back gate and drain layers in the region.

Abstract: An partially depleted Dieler LDMOSFET transistor (100) is provided which includes a substrate (150), a drift region (110) surrounding a drain region (128), a first well region (107) surrounding source region (127), a well buffer region (106) separating the drift region and first well region to at least partly define a first channel region, a gate electrode (118) formed over the first channel region having a source-side gate edge aligned with the first well region (107), an LDD extension region (120) extending from the source region to the channel region, and a dielectric RESURF drain extension structure (161) formed at the drain of the gate electrode (118) using the plurality of STI stripes (114).

Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.

Abstract: A high voltage semiconductor device, particularly a device including a number of high breakdown voltage transistors having a common drain, first well, and insulating structure between the gate and the drain as well as method for using the same is provided in this disclosure. The high breakdown voltage transistors in the device together are in an elliptical shape. A second well region, gate structure, and a source region are partially overlapping discontinuous elliptical rings having at least two discontinuities or openings in a top view. The respective discontinuities or openings define each of the high breakdown voltage transistors.

Abstract: A semiconductor device includes a first well, a second well, and a separator structure. The first well and the second well are implanted in the semiconductor substrate. The separator structure is also implanted in the semiconductor substrate and separates the first well and the second well so that the first well and the second well do not contact each other.

Abstract: In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions.

Abstract: A semiconductor device is disclosed wherein a peripheral region with a high breakdown voltage and high robustness against induced surface charge is manufactured using a process with high mass productivity. The device has n-type drift region and p-type partition region of layer-shape deposited in a vertical direction to one main surface of n-type semiconductor substrate with high impurity concentration form as drift layer, alternately adjacent parallel pn layers in a direction along one main surface. Active region through which current flows and peripheral region enclosing the active region include parallel pn layers.

Abstract: Disclosed is a transistor component having a control structure with a channel control layer of an amorphous semiconductor insulating material extending in a current flow direction along a channel zone.