Abstract: A transistor structure that improves ESD withstand voltages is offered. A high impurity concentration drain layer is formed in a surface of an intermediate impurity concentration drain layer at a location separated from a drain-side end of a gate electrode. And a P-type impurity layer is formed in a surface of a substrate between the gate electrode and the high impurity concentration drain layer so as to surround the high impurity concentration drain layer. When a parasitic bipolar transistor is turned on by an abnormal surge, electrons travel from a source electrode to a drain electrode. Here, electrons travel dispersed in the manner to avoid a vicinity X of the surface of the substrate and travel through a deeper path to the drain electrode as indicated by arrows in FIG. 4.

Abstract: A superjunction semiconductor device is disclosed which has, in the active section, a first alternating-conductivity-type layer which makes a current flow in the ON-state of the device and sustains a bias voltage in the OFF-state of the device. There is a second alternating-conductivity-type layer in a edge-termination section surrounding the active section. The width of a region of a second conductivity type in the second alternating-conductivity-type layer becomes narrower at a predetermined rate from the edge on the active section side toward the edge of the edge termination section. The superjunction semiconductor device facilitates manufacturing the edge-termination section which exhibits a high breakdown voltage and a high reliability for breakdown voltage through a process that exhibits a high mass-productivity.

Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.

Abstract: A semiconductor device includes a semiconductor substrate, a body region of a first conductivity type in the substrate, a source region of a second conductivity type opposite the first conductivity type adjacent the body region, and a trench extending into the substrate adjacent the source and body regions. The trench contains a polysilicon gate electrode insulated from the substrate. The device further includes a dielectric layer on the substrate, a gate metallization on the dielectric layer and covering part of the substrate and a source metallization on the dielectric layer and electrically connected to the source region. The source metallization is spaced apart from the gate metallization and covers a different part of the substrate than the gate metallization. A metal-filled groove in the polysilicon gate electrode is electrically connected to the gate metallization, and extends along a length of the trench underneath at least part of the source metallization.

Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).

Abstract: A semiconductor device includes a first conduction-type semiconductor substrate, a first semiconductor region of a first conduction-type formed on the semiconductor substrate, a second semiconductor region of a second conduction-type formed on a surface of the first semiconductor region, a third semiconductor region of the second conduction-type formed to be separated from the second semiconductor region on the surface of the first semiconductor region, a fourth semiconductor region of the second conduction-type formed to be separated from the second semiconductor region and the third semiconductor region on the surface of the first semiconductor region, and a first electrode connected to the second semiconductor region and the third semiconductor region.

Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).

Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.

Abstract: In a method for producing an electronic component, a substrate is doped by introducing doping atoms. In the doped substrate, at least one connection region of the electronic component is formed by doping with doping atoms. Furthermore, at least one additional doped region is formed at least below the at least one connection region by doping with doping atoms. Furthermore, at least one well region is formed in the substrate by doping with doping atoms in such a way that the well region doping is blocked at least below the at least one additional doped region.

Abstract: A MOS semiconductor device has a MOS structure, including a p? region that surrounds an n+-type source region and has a net doping concentration lower than a concentration of a p-type impurity in a surface of a p-type well region, and a gate electrode that is provided on top of the surface of the p-type well region sandwiched between the n+-type source region and a surface layer of an n? layer, with a gate insulator disposed between the p-type well region and the gate electrode. This configuration can make the gate insulator thicker without increasing a gate threshold voltage, and help improve the reliability of the gate insulator and reduce the gate capacitance.

Abstract: In a general aspect, a semiconductor device can include a gate having a first trench portion disposed within a first trench of a junction field-effect transistor device, a second trench portion disposed within a second trench of the junction field-effect transistor device, and a top portion coupled to both the first trench portion and to the second trench portion. The semiconductor device can include a mesa region disposed between the first trench and the second trench, and including a single PN junction defined by an interface between a substrate dopant region having a first dopant type and a channel dopant region having a second dopant type.

Abstract: An integrated circuit (IC) comprising a shielding mesh in at least one layer of the IC, the shielding mesh having a first plurality of lines which are designed to provide a first reference voltage and having a second plurality of lines which are designed to provide a second reference voltage and wherein the shielding mesh comprises a window in which signal lines are routed with less shielding than signal lines which are routed in the shielding mesh. The IC further comprising power supply lines in at least a first layer of the IC, the first layer being different than the at least one layer which contains the shielding mesh, the power supply lines being coupled to the shielding mesh and being larger in width than the first plurality of lines and the second plurality of lines.

Abstract: According to one embodiment, a flat panel display includes a first mounting portion including a first input pad and a first output pad, a second mounting portion including a second input pad and a second output pad, a first common terminal and a second common terminal, which have a common potential, and a guard ring wiring which is formed in a manner to extend from the first common terminal, to pass between the first input pad and the first output pad of the first mounting portion, to pass between the second input pad and the second output pad of the second mounting portion, and to reach the second common terminal, the guard ring wiring including a first resistor element of a first resistance value and a second resistor element of a second resistance value which is higher than the first resistance value.

Abstract: A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring.

Abstract: A semiconductor device is provided. The semiconductor device includes a gate on a substrate, a source region at a first side of the gate, a first conductive type body region under the source region, a second conductive type drain region at a second side of the gate, a device isolation region in the substrate between the source region and the drain region and overlapping part of the gate, and a first buried layer extending in a direction from the source region to the drain region, the first buried layer under the body region, overlapping part of the device isolation region, and not overlapping the drain region.

Abstract: Provided is a power semiconductor device including a guard ring region to protect control devices. The power semiconductor device includes a semiconductor body layer extending over a semiconductor substrate of a first conductivity type. The semiconductor body layer has a second conductivity type opposite the first conductivity type. A well of the first conductivity type extends in the semiconductor body layer and is configured to be electrically insulated from the semiconductor substrate. At least one control device is formed in the well, where the control device comprises at least one of PN junction. A guard ring region of the first conductivity type is laterally spaced from but surrounds the well. The guard ring region together with the semiconductor substrate and the semiconductor body layer form a parasitic bipolar transistor, and the guard ring region functions as a collector of the parasitic bipolar transistor.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: A semiconductor device having a super junction structure includes: multiple first columns extending in a current flowing direction; and multiple second columns extending in the current flowing direction. The first and second columns are alternately arranged in an alternating direction. Each first column provides a drift layer. The first and second columns have a boundary therebetween, from which a depletion layer expands in case of an off-state. At least one of the first columns and the second columns have an impurity dose, which is inhomogeneous by location with respect to the alternating direction.

Abstract: An apparatus includes a wafer annealing tool and a plurality of electrodes coupled to the wafer annealing tool, wherein the electrodes are configured to be in physical contact with a wafer so that, when the wafer is annealed, a negative electrical bias is formed across one or more gate stacks of the wafer.

Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

Abstract: A semiconductor element, a manufacturing method thereof and an operating method thereof are provided. The semiconductor element includes a substrate, a first well, a second well, a third well, a fourth well, a bottom layer, a first heavily doping region, a second heavily doping region, a third heavily doping region and a field plane. The first well, the bottom layer and the second well surround the third well for floating the third well and the substrate. The first, the second and the third heavily doping regions are disposed in the first, the second and the third wells respectively. The field plate is disposed above a junction between the first well and the fourth well.

Abstract: A transistor comprising a plurality of active semiconductor layers on a substrate, with source and drain electrodes in contact with the semiconductor layers. A gate is formed between the source and drain electrodes and on the plurality of semiconductor layers. A plurality of field plates are arranged over the semiconductor layers, each of which extends from the edge of the gate toward the drain electrode, and each of which is isolated from said semiconductor layers and from the others of the field plates. The topmost of the field plates is electrically connected to the source electrode and the others of the field plates are electrically connected to the gate or the source electrode.

Abstract: An electrostatic discharge semiconductor device can include a first conductivity type substrate that includes inner first conductivity type wells therein and a plurality of gate electrodes that are on an active region of the substrate. A second conductivity type well can be located in the substrate beneath the plurality of gate electrodes including at least one slit therein providing electrical contact between the inner first conductivity type wells and a first conductivity type outer well outside the active region.

Abstract: A semiconductor device with a field electrode and method. One embodiment provides a controllable semiconductor device including a control electrode for controlling the semiconductor device and a field electrode. The field electrode includes a number of longish segments which extend in a first lateral direction and which run substantially parallel to one another. The control electrode includes a number of longish segments extending in a second lateral direction and running substantially parallel to one another, wherein the first lateral direction is different from the second lateral direction.

Abstract: A semiconductor device includes a substrate including a first region and a second region, a trench-gate transistor in the first region, the trench-gate transistor including a first trench in the substrate, a gate filling at least part of the first trench, and a source in the substrate and on each sidewall of the first trench, a first field diffusion junction in the second region, an interlayer insulating film on the substrate, the interlayer insulating film covering the trench-gate transistor and the first field diffusion junction, a first contact in the first region, the first contact passing through the interlayer insulating film and contacting the source, and a second contact in the second region, the second contact passing through the interlayer insulating film and contacting the first field diffusion junction, the first contact and the second contact having an equal height and including a same material.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate in which isolation regions are formed for defining a device region; a gate formed on the first conductive type substrate; a source and a drain formed in the device region and located at both sides of the gate respectively, and doped with second conductive type impurities; a second conductive type well, which is formed in the first conductive type substrate, and surrounds the drain from top view; and a first deep trench isolation structure, which is formed in the first conductive type substrate, and is located in the second conductive type well between the source and the drain from top view, wherein the depth of the first deep trench isolation structure is deeper than the second conductive type well from the cross-sectional view.

Abstract: A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source.

Abstract: A carrier is prevented from being stored in a guard ring region in a semiconductor device. The semiconductor device has an IGBT cell including a base region and an emitter region formed in an n? type drift layer, and a p type collector layer arranged under the drift layer with a buffer layer interposed therebetween. A guard ring region having a guard ring is arranged around the IGBT cell. A lower surface of the guard ring region has a mesa structure provided by removing the collector layer.

Abstract: A disclosed MOS transistor has a drain region offset from a gate electrode structure, wherein the gate electrode structure includes at least a first gate electrode and a second gate electrode such that the second gate electrode is located at the drain side of the first gate electrode and the second gate electrode is isolated from the first gate electrode by an insulation film, and wherein the first and second gate electrodes are formed respectively on a first gate insulation film and a second gate insulation film having an increased thickness as compared with the first gate insulation film.

Abstract: A semiconductor device includes a drift region of a first doping type, a junction between the drift region and a device region, a compensation region of a second doping type, and at least one field electrode structure arranged between the drift region and the compensation region. The at least one field electrode includes a field electrode and a field electrode dielectric adjoining the field electrode. The field electrode dielectric is arranged between the field electrode and the drift region and between the field electrode and the compensation. The field electrode dielectric includes a first opening through which the field electrode is coupled to drift region and a second opening through which the field electrode is coupled to the compensation region.

Abstract: A semiconductor device includes a channel layer formed over a substrate, a gate formed over the channel layer, junction regions formed on both sides of the channel layer to protrude from the substrate, and a buried barrier layer formed between the channel layer and the junction regions.

Abstract: A semiconductor device includes a semiconductor substrate including an element region, an inner sealing and an outer sealing which are formed on the element region and have a first opening part and a second opening part, respectively, a multilayer interconnection structure which is formed on the substrate and stacks multiple inter-layer insulation films each including a wiring layer, a moisture resistant film formed between a first inter-layer insulation film and a second inter-layer insulation film which are included in the multilayer interconnection structure, a first portion which extended from a first side of the moisture resistant film and passes the first opening part, a second portion which extended from a second side of the moisture resistant film and passes through the second opening part, and a wiring pattern including a via plug which penetrates the moisture resistant film and connects the first portion and the second portion.

Abstract: An electro-static discharge protection circuit includes: a PNPN junction, a P-type side of the PNPN junction being coupled to a terminal, an N-type side of the PNPN junction being coupled to ground; and a P-type metal oxide semiconductor transistor, a source and a gate of the P-type metal oxide semiconductor transistor being coupled to an N-type side of a PN junction whose P-type side coupled to the ground, and a drain of the P-type metal oxide semiconductor transistor being coupled to the terminal.

Abstract: A device includes a first and a second heavily doped region in a semiconductor substrate. An insulation region has at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions. A gate dielectric is formed over the semiconductor substrate and having a portion over a portion of the insulation region. A gate is formed over the gate dielectric. A floating conductor is over and vertically overlapping the insulation region. A metal line includes a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region.

Abstract: A semiconductor device includes a cell region and a contact region, the cell region including a functional unit including a gate electrode, a source and a drain electrode, and the contact region including a gate pad. The gate electrode, the gate pad and the source electrode are disposed on a first main surface of a semiconductor substrate, and the drain electrode is disposed on a second main surface of the semiconductor substrate, the second main surface being opposite to the first main surface. A shielding member is disposed between the gate pad and the drain electrode, the shielding member being electrically connected to the source electrode.

Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.

Abstract: A nitride semiconductor device includes a semiconductor substrate and a nitride semiconductor layer disposed on the semiconductor substrate. The semiconductor substrate includes a normal region, a carrier supplying region, and an interface current blocking region. The interface current blocking region surrounds the normal region and the carrier supplying region. The interface current blocking region and the carrier supplying region include impurities. The carrier supplying region has a conductivity type allowing the carrier supplying region to serve as a source of carriers supplied to or a destination of carriers supplied from a carrier layer generated at an interface between the nitride semiconductor layer and the semiconductor substrate. The interface current blocking region has a conductivity type allowing the interface current blocking region to serve as a potential barrier to the carriers.

Abstract: In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings.

Abstract: A transistor device includes a lightly doped layer of semiconductor material of a first type and a body region of semiconductor material of a second type. A source region of the first type is formed in the body region, the source region being more doped than the lightly doped layer. A drain region of the first type is formed in the lightly doped layer, the drain region being more doped than the lightly doped layer. A drift region of the lightly doped layer is further provided disposed between the body region and the drain region. Additionally, a gate electrode is provided surrounding the drain region. The gate electrode is partially disposed over a thin oxide and partially over a thick oxide, wherein the gate electrode extended over the thick oxide from the thin oxide controls the electric field in the drift region to increase the avalanche breakdown of the drain region.

Abstract: Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.

Abstract: A semiconductor device includes: a transistor region including an IGBT having a gate electrode and an emitter electrode; a termination region placed around the transistor region; and an extraction region placed between the transistor and the termination region and extracting redundant carriers. A P-type layer is placed on an N-type drift layer in the extraction region. The P-type layer is connected to the emitter electrode. A dummy gate electrode is placed via an insulation film on the P-type layer. The dummy gate electrode is connected to the gate electrode. Life time of carriers in the termination region is shorter than life time of carriers in the transistor region and the extraction region.

Abstract: A high voltage lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOS) comprises a substrate; an epitaxy layer on the substrate; a drift region on the epitaxy layer; and a drain region and a source region at two ends. At least one pair of n-type and p-type semiconductor regions is arranged alternately above the interface of the substrate and the epitaxy layer and firmly attached to a lower surface of the drifting region; the n-type and p-type semiconductor regions are firmly closed to each other and arranged to form a lateral PN junction; and the p-type semiconductor region and the drifting region form a vertical PN junction. The n-type and p-type semiconductor regions are also totally called “a reduced surface field (RESURF) layer in body”, and the LDMOS device with a RESURF layer in body effectively solves conflict between raising reverse withstand voltage and reducing forward on-resistance of the current LDMOS devices.

Abstract: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

Abstract: A guard ring system is disclosed for protecting an integrated circuit comprising. It has a first guard ring area formed by a well in the substrate, a capacitor area formed within the first guard ring area which further includes two well contacts formed into the well and biased by a first supply voltage, and a dielectric layer placed between the two contacts on the well with its first side in contact with the well. A second supply voltage complementary to the first supply voltage is applied to a second side of the dielectric layer so that a voltage difference across the dielectric layer provides a local capacitance embedded therein.

Abstract: A super-junction trench MOSFET is disclosed for high voltage device by applying a first doped column region of first conductivity type between a pair of second doped column regions of second conductivity type adjacent to sidewalls of a pair of deep trenches with buried voids in each unit cell for super-junction. Meanwhile, at least one trenched gate and multiple trenched source-body contacts are formed in each unit cell between the pair of deep trenches.

Abstract: In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other.

Abstract: A super-junction trench MOSEET is disclosed for high voltage device by applying a first doped column region of first conductivity type between a pair of second doped column regions of second conductivity type adjacent to sidewalls of a pair of deep trenches in each unit cell for super-junction. Meanwhile, at least one trenched gate and multiple trenched source-body contacts are formed in each unit cell between the pair of deep trenches.

Abstract: A semiconductor power device having shielded gate structure integrated with a trenched clamp diode formed in a semiconductor silicon layer, wherein the shielded gate structure comprises a shielded electrode formed by a first poly-silicon layer and a gate electrode formed by a second poly-silicon layer. The trenched clamp diode is formed by the first poly-silicon layer. A shielded gate mask used to define the shielded gate is also used to define the trenched clamp diode. Therefore, one poly-silicon layer and a mask for the trenched clamp diode are saved.

Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.

Abstract: N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).