Gate Electrode Of Refractory Material (e.g., Polysilicon Or A Silicide Of A Refractory Or Platinum Group Metal) Patents (Class 257/412)
  • Patent number: 10692788
    Abstract: A conductive-insulator-semiconductor (CIS) device with low flicker noise is provided. In some embodiments, the CIS device comprises a semiconductor substrate, a pair of source/drain regions, a selectively-conductive channel, and a gate electrode. The pair of source/drain regions is in the semiconductor substrate, and the source/drain regions are laterally spaced. The selectively-conductive channel is in the semiconductor substrate, and extends laterally in a first direction, from one of the source/drain regions to another one of the source/drain regions. The gate electrode comprises a pair of peripheral segments and a central segment. The peripheral segments extend laterally in parallel in the first direction. The central segment covers the selectively-conductive channel and extends laterally in a second direction transverse to the first direction, from one of the peripheral segments to another one of the peripheral segments. A method for manufacturing the CIS device is also provided.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Shun Lo, Ching-Hsien Huang, Yu-Chi Chang
  • Patent number: 10622449
    Abstract: A method of fabricating a tunnel oxide layer for a semiconductor memory device, the method comprising: fabricating on a substrate a first oxide layer by a plasma oxidation process; and fabricating at least one further oxide layer by a furnace oxidation process, wherein during fabrication of the at least one further oxide layer, reactive gases penetrate the first oxide layer and react with the silicon substrate to form at least a first portion of the at least one further oxide layer beneath the first oxide layer.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: April 14, 2020
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES GMBH
    Inventors: Eng Gek Hee, Ka Siong Wisley Ung
  • Patent number: 10615166
    Abstract: The present disclosure relates to a programmable device. The programmable device comprises a first vertical transistor; and a second vertical transistor coupled to the first vertical transistor via a shared terminal, wherein: a first gate dielectric of the first vertical transistor has a first thickness and a second gate dielectric of the second vertical transistor has a second thickness, the first thickness being greater than the second thickness, and the second gate dielectric breaks down based on an application of a gate voltage that is lower than a first breakdown voltage of the first gate dielectric and higher than a second breakdown voltage of the second gate dielectric.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10608084
    Abstract: A semiconductor device includes a plurality of stacked structures spaced apart from each other on a substrate, wherein the plurality of stacked structures each comprise a plurality of gate layers and a plurality of channel layers, a plurality of arsenic implanted regions on portions of a surface of the substrate adjacent the plurality of stacked structures, and a plurality of epitaxial source/drain regions extending from the plurality of stacked structures, wherein the plurality of epitaxial source/drain regions are spaced apart from the plurality of arsenic implanted regions.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventor: Alexander Reznicek
  • Patent number: 10593598
    Abstract: Techniques for forming VFETs with differing gate lengths Lg on the same wafer using a gas cluster ion beam (GCIB) process to produce fins of differing heights are provided. In one aspect, a method of forming fins having different heights includes: patterning the fins having a uniform height in a substrate, the fins including at least one first fin and at least one second fin; forming an oxide at a base of the at least one second fin using a low-temperature directional oxidation process (e.g., GCIB oxidation); and removing the oxide from the base of the at least one second fin to reveal the at least one first fin having a height HI and the at least one second fin having a height H2, wherein H2>H1. VFETs and methods for forming VFETs having different fin heights using this process are also provided.
    Type: Grant
    Filed: December 23, 2017
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xin Miao, Kangguo Cheng, Chen Zhang
  • Patent number: 10586867
    Abstract: A semiconductor structure, such as a strained FinFETs, includes a strain relief buffer (SRB) layer isolated and separated from a source and a drain by a spacer that may be simultaneously formed with a gate spacer upon the sidewalls of a gate structure. The spacer limits the source and drain from contacting the SRB layer thereby limiting source drain junction leakage. Further, the spacer limits source and drain punch through to the SRB layer underneath a channel. An etch may partially remove a SRB layer portion within a fin stack. The etch undercuts the source and drain forming a fin void without under cutting the channel. The spacer may be formed by depositing spacer material with the fin void.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang
  • Patent number: 10546785
    Abstract: After forming a material stack including a gate dielectric, a work function metal and a cobalt gate electrode in a gate cavity formed by removing a sacrificial gate structure, the cobalt gate electrode is recessed by oxidizing the cobalt gate electrode to provide a cobalt oxide layer on a surface of the cobalt gate electrodes and removing the cobalt oxide layer from the surface of the cobalt gate electrodes by a chemical wet etch. The oxidation and oxide removal steps can be repeated until the cobalt gate electrode is recessed to any desired thickness. The work function metal can be recessed after the recessing of the cobalt gate electrode is completed or during the recessing of the cobalt gate electrode.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: January 28, 2020
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES INC., LAM RESEARCH CORPORATION
    Inventors: Georges Jacobi, Vimal K. Kamineni, Randolph F. Knarr, Balasubramanian Pranatharthiharan, Muthumanickam Sankarapandian
  • Patent number: 10483167
    Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. A hard mask and a mask layer are formed on a first region and a second region of the substrate. The substrate is recessed using the hard mask and the mask layer to form a fin structure in the first region and a raised structure in the second region. First isolation structures and second isolation structures are formed on lower portions of opposite sidewalls of the fin structure and opposite sidewalls of the raised structure. A first gate structure is formed on a portion of the fin structure, and a second gate structure is formed on a portion of the raised structure. A first source and a first drain are formed on opposite sides of the first gate structure, and a second source and a second drain are formed on opposite sides of the second gate structure.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Barn Chen, Ting-Huang Kuo, Shiu-Ko Jangjian, Chi-Cherng Jeng, Kuang-Yao Lo
  • Patent number: 10446592
    Abstract: An integrated ultraviolet (UV) detector includes a silicon carbide (SiC) substrate, supporting metal oxide field effect transistors (MOSFETs), Schottky photodiodes, and PN Junction photodiodes. The MOSFET includes a first drain/source implant in the SiC substrate and a second drain/source implant in the SiC substrate. The Schottky photodiodes include another implant in the SiC substrate and a surface metal area configured to pass UV light.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: October 15, 2019
    Assignee: CoolCAD Electronics, LLC
    Inventors: Neil Goldsman, Akin Akturk, Zeynep Dilli, Brendan Michael Cusack, Mitchell Adrian Gross
  • Patent number: 10439043
    Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: October 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee, Shogo Mochizuki
  • Patent number: 10373876
    Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a substrate having at least a first area with a plurality of polysilicon gates and a second area adjacent to the first area is provided. A contact etch stop layer (CESL) over the polysilicon gates of the first area is formed, and the CESL extends to the second area. Then, a dielectric layer is formed on the CESL, and a nitride layer is formed on the dielectric layer. The nitride layer is patterned to expose the dielectric layer in the first area and to form a pattern of dummy nitrides on the dielectric layer in the second area.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: August 6, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Kuan-Liang Liu
  • Patent number: 10354928
    Abstract: A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: July 16, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Suraj Kumar Patil, Katsunori Onishi, Pei Liu, Chih-Chiang Chang
  • Patent number: 10312158
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first amorphous layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the first amorphous layer covers the first fin portion. The method includes annealing the first amorphous layer to crystallize the first amorphous layer into a first polycrystalline layer. The method includes forming a second amorphous layer over the first polycrystalline layer. The method includes removing a first portion of the second amorphous layer and a second portion of the first polycrystalline layer under the first portion. The remaining second amorphous layer and the remaining first polycrystalline layer together form a first gate structure over and across the first fin portion.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Cheng Li, Chien-Hao Chen, Yung-Cheng Lu, Jr-Jung Lin, Chun-Hung Lee, Chao-Cheng Chen
  • Patent number: 10299379
    Abstract: A sheet-shaped stretchable structure used as an electronics element has a stretch of not less than 10% and includes a plurality of laminated stretchable resin sheet, and at least one hollow is provided between at least one of pairs of two adjacent ones of the laminated stretchable resin sheets.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: May 21, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takatoshi Abe, Tomoaki Sawada, Shingo Yoshioka
  • Patent number: 10297509
    Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. The method includes providing a base substrate including a first region and a second region; and forming a first doped region in the first region, and a second doped region in the second region. The second doped region is doped with blocking ions. The method also includes forming a first metal layer on a surface of the first doped region and on a surface of the second doped region; and forming a second metal layer on a surface of the first metal layer. The second metal layer is made of a material different from the first metal layer. Further, the method includes forming a first metal silicide layer and a second metal silicide layer by performing an annealing process. The blocking ions block atoms of the second metal layer from diffusing into the second metal silicide layer.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: May 21, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 10295877
    Abstract: An array substrate includes a first light-shielding insulation layer formed on the substrate, for block a light entering the substrate, and including a first region and a second region, and each is made of an insulation material; a first function layer formed on the second region, under a light-shielding function of the second region, an affection of light is avoided; a second function layer formed above the first region of the first light-shielding insulation layer and the first function layer, under the light-shielding function of the first light-shielding insulation layer, an affection of light is avoided; and a third function layer formed above the second function layer, under the light-shielding function of the first light-shielding insulation layer, an affection of light is avoided; wherein, each of the first, the second and the third function layer is a conductor material or a semiconductor material. A photo-leakage current can be avoided.
    Type: Grant
    Filed: June 12, 2016
    Date of Patent: May 21, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Mengmeng Zhang
  • Patent number: 10283417
    Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a semiconductor device includes a first gate structure and a second gate structure on a substrate; wherein the first gate structure includes a first gate dielectric layer having a first material, and the second gate structure includes a second gate dielectric layer having a second material, the first material being different from the second material, wherein the first and the second gate structures further includes a first and a second self-protective layers disposed on the first and the second gate dielectric layers respectively, wherein the first self-protective layer includes metal phosphate and the second self-protective layer includes boron including complex agents and a first work function tuning layer on the first self-protective layer in the first gate structure.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Li Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 10276687
    Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: April 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee, Shogo Mochizuki
  • Patent number: 10269967
    Abstract: A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET). The Method includes performing an implantation to form a pre-amorphization implantation (PAI) region adjacent to a gate electrode of the MOSFET, forming a strained capping layer over the PAI region, and performing an annealing on the strained capping layer and the PAI region to form a dislocation plane. The dislocation plane is formed as a result of the annealing, with a tilt angle of the dislocation plane being smaller than about 65 degrees.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wei-Yuan Lu
  • Patent number: 10243078
    Abstract: An embodiment includes a device comprising: a trench that includes a doped trench material having: (a)(i) a first bulk lattice constant and (a)(ii) at least one of a group III-V material and a group IV material; a fin structure, directly over the trench, including fin material having: (b) (ii) a second bulk lattice constant and (b)(ii) at least one of a group III-V material and a group IV material; a barrier layer, within the trench and directly contacting a bottom surface of the fin, including a barrier layer material having a third bulk lattice constant; wherein (a) the trench has an aspect ratio (depth to width) of at least 1.5:1, and (b) the barrier layer has a height not greater than a critical thickness for the barrier layer material. Other embodiments are described herein.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Tahir Ghani, Anand S. Murthy, Chandra S. Mohapatra, Harold W. Kennel, Glenn A. Glass
  • Patent number: 10229984
    Abstract: A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate structure at least including a polysilicon layer. After forming the replacement gate structure, a gate spacer is formed on the replacement gate structure. Atoms are implanted in an upper portion of the polysilicon layer. The implanting expands the upper portion of the polysilicon layer and a corresponding upper portion of the gate spacer in at least a lateral direction beyond a lower portion of the polysilicon layer and a lower portion of the spacer, respectively. After the atoms have been implanted, the polysilicon layer is removed to form a gate cavity. A metal gate stack is formed within the gate cavity. The metal gate stack includes an upper portion having a width that is greater than a width of a lower portion of the metal gate stack.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Victor Chan, Jin Ping Han, Shangbin Ko
  • Patent number: 10204942
    Abstract: A method for manufacturing the top-gated thin film transistors is disclosed and includes forming a first photoresist pattern with a first shielding portion and two second shielding portions, and etching a gate metal layer by adopting the first photoresist pattern as a mask. Thus, a size of the gate pattern coincides with a size of a channel region of a conductive channel, to increase a control force of a gate to the conductive channel, thereby improving performance of device.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: February 12, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Liwang Song
  • Patent number: 10170373
    Abstract: A method of fabricating advanced multi-threshold field effect transistors using a replacement metal gate process. A first method includes thinning layers composed of multilayer film stacks and incorporating a portion of the remaining thinned film in some transistors. A second method includes patterning dopant materials for a high-k dielectric by using thinning layers composed of multilayer thin film stacks, or in other embodiments, by a single thinning layer.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Balaji Kannan, Rekha Rajaram, Unoh Kwon
  • Patent number: 10170367
    Abstract: In an embodiment, a method includes: patterning a plurality of mandrels over a mask layer; forming an etch coating layer on top surfaces of the mask layer and the mandrels; depositing a dielectric layer over the mask layer and the mandrels, a first thickness of the dielectric layer along sidewalls of the mandrels being greater than a second thickness of the dielectric layer along the etch coating layer; removing horizontal portions of the dielectric layer; and patterning the mask layer using remaining vertical portions of the dielectric layer as an etching mask.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Chao-Cheng Chen, Hao-Ming Lien, Wei-Che Hsieh, Chun-Hung Lee
  • Patent number: 10163837
    Abstract: A method of forming an integrated circuit device includes forming a bump structure on a substrate, wherein the bump structure has a top surface and a sidewall surface, and the substrate has a surface region exposed by the bump structure. The method further includes depositing a non-metal protection layer on the top surface and the sidewall surface of the bump structure and the surface region of the substrate. The method further includes removing the non-metal protection layer from the top surface of the bump structure, wherein a remaining portion of the non-metal protection layer forms an L-shaped protection structure, and a top surface of the remaining portion of the non-metal protection layer is farther from the substrate than a top surface of the bump structure.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Ling Hwang, Yi-Wen Wu, Chung-Shi Liu
  • Patent number: 10141398
    Abstract: A semiconductor structure includes a HV NMOS structure. The HV NMOS structure includes a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The source region and the drain region are separated from each other. The channel region is disposed between the source region and the drain region. The channel region has a channel direction from the source region toward the drain region. The gate dielectric is disposed on the channel region and on portions of the source region and the drain region. The gate electrode is disposed on the gate dielectric. The gate electrode includes a first portion of n-type doping and two second portions of p-type doping. The two second portions are disposed at two sides of the first portion. The two second portions have an extending direction perpendicular to the channel direction.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: November 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Tsai, Jung Han, Chin-Chia Kuo, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 10103066
    Abstract: A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and dummy fins on a substrate, the dummy fins adjacent to each other and between the active fins; forming STI regions between and next to the active and dummy fins; forming gate structures in parallel across the active and dummy fins; forming a gate cut region by cutting the gate structures between the dummy fins; forming a TS layer between the gate structures, the TS layer crossing the gate cut region; and forming a contact connecting a gate structure and the TS layer on a first side of the gate cut region and forming a contact connecting a gate structure and the TS layer on a second side of the gate cut region, the TS layer and contacts cross coupling the gate structures.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: October 16, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Ryan Ryoung-han Kim
  • Patent number: 10079182
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, depositing a first nitride layer on exposed portions of the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer, the scavenging layer, and the first nitride layer to expose a portion of the first dielectric layer in an n-type field effect transistor (nFET) region of the gate stack, forming a barrier layer over the first dielectric layer and the capping layer, forming a first gate metal layer over the barrier layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: September 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Patent number: 10008581
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.
    Type: Grant
    Filed: August 30, 2015
    Date of Patent: June 26, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
  • Patent number: 9978647
    Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a substrate having at least a first area with a plurality of polysilicon gates and a second area adjacent to the first area is provided. A contact etch stop layer (CESL) over the polysilicon gates of the first area is formed, and the CESL extends to the second area. Then, a dielectric layer is formed on the CESL, and a nitride layer is formed on the dielectric layer. The nitride layer is patterned to expose the dielectric layer in the first area and to form a pattern of dummy nitrides on the dielectric layer in the second area.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: May 22, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Kuan-Liang Liu
  • Patent number: 9960252
    Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: May 1, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Takashi Ando, Eduard A. Cartier, Kisik Choi, Vijay Narayanan
  • Patent number: 9953876
    Abstract: The present disclosure provides a method of forming a semiconductor device structure including forming a first gate stack comprising a first gate dielectric material and a first gate electrode material over a first active region in an upper portion of a substrate, forming a first spacer structure adjacent to the first gate stack, and forming first raised source/drain (RSD) regions at opposing sides of the first gate stack on the first active region in alignment with the first spacer structure. Herein, forming the first spacer structure includes forming a first spacer structure on sidewalls of the first gate stack, the first gate dielectric extending in between the first spacer and the upper surface portion, patterning the first gate dielectric material, and forming a second spacer over the first spacer and the patterned first gate dielectric material.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 24, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Hans-Juergen Thees
  • Patent number: 9941373
    Abstract: A device comprises a metal gate structure over a substrate, wherein the metal gate structure comprises a first metal sidewall, a metal bottom layer, a first corner portion between the first metal sidewall and the metal bottom layer, wherein the first corner portion comprises a first step and a first ramp, a second metal sidewall and a second corner portion between the second metal sidewall and the metal bottom layer, wherein the second corner portion comprises a second step and a second ramp.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
  • Patent number: 9882013
    Abstract: Provided is a semiconductor device including a gate electrode, source and drain regions, and a spacer. The gate electrode is located over a substrate, and an angle of a base corner of the gate electrode is greater than 90 degrees. The source and drain regions are located in the substrate at sides of the gate electrode. The spacer is located at a sidewall of the gate electrode.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Wang Lu, Kuo Hui Chang, Mu-Tsang Lin
  • Patent number: 9875925
    Abstract: A method of fabricating a semiconductor device includes forming a doped polysilicon layer on a substrate, forming a barrier layer on the doped polysilicon layer, forming an oxidized barrier layer by oxidizing a surface of the barrier layer, and forming a metal layer on the oxidized barrier layer.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: January 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung-ho Kong, Jeong-hee Park, Taek-jung Kim, Han-young Kim, Keon-seok Seo, Jong-myeong Lee, Hee-sook Park
  • Patent number: 9831244
    Abstract: A method for manufacturing a semiconductor device includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern and a second metal gate film pattern in the trench, redepositing a second metal gate film on the first and second metal gate film patterns and the insulation film, and forming a redeposited second metal gate film pattern on the first and second metal gate film patterns by performing a planarization process for removing a portion of the redeposited second metal gate film so as to expose a top surface of the insulation film, and forming a blocking layer pattern on the redeposited second metal gate film pattern by oxidizing an exposed surface of the redeposited second metal gate film pattern.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: November 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Youn Kim, Je-Don Kim
  • Patent number: 9824929
    Abstract: A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure is fluorine incorporated and includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3. The semiconductor device further includes a p-type gate structure over a second semiconductor fin, in which the p-type gate structure is fluorine incorporated includes a p-type work function metal layer overlying the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), in which an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko Jangjian, Ren-Hau Yu, Chi-Cherng Jeng
  • Patent number: 9825058
    Abstract: An oxide semiconductor transistor used in a pixel element of a display device and a method of manufacturing the same are disclosed. The oxide semiconductor transistor used in a pixel element of a display device comprises a substrate, a first gate electrode located on the substrate, a source electrode and a drain electrode located on the first gate electrode and a second gate electrode located on the source electrode and the drain electrode. Here, the first gate electrode is electrically connected to the second gate electrode, the same voltage is applied to the first gate electrode and the second gate electrode, and a width of the second gate electrode is shorter than a length between the source electrode and the drain electrode.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: November 21, 2017
    Assignee: University-Industry Cooperation Group of Kyung Hee University
    Inventors: Jin Jang, Man Ju Seok, Jae Gwang Um, Su Hui Lee
  • Patent number: 9805944
    Abstract: A p-type base region, n+-type source region, p+-type contact region, and n-type JFET region are formed on a front surface side of a silicon carbide base by ion implantation. The front surface of the silicon carbide base is thermally oxidized, forming a thermal oxide film. Activation annealing at a high temperature of 1500 degrees C. or higher is performed with the front surface of the silicon carbide base being covered by the thermal oxide film. The activation annealing is performed in a gas atmosphere that includes oxygen at a partial pressure from 0.01 atm to 1 atm and therefore, the thermal oxide film thickness may be maintained or increased without a decrease thereof. The thermal oxide film is used as a gate insulating film and thereafter, a poly-silicon layer that is to become a gate electrode is deposited on the thermal oxide film, forming a MOS gate structure.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: October 31, 2017
    Assignees: OSAKA UNIVERSITY, FUJI ELECTRIC CO., LTD.
    Inventors: Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Mitsuru Sometani
  • Patent number: 9799827
    Abstract: A method of manufacturing an electronic device including a semiconductor memory is provided. The method may include forming a material layer for forming a variable resistance element over a substrate, forming a metal layer over the material layer, forming a mask pattern over the metal layer, forming a metal layer pattern by etching the metal layer using the mask pattern as an etch barrier, performing a surface treatment on the metal layer pattern, and etching the material layer using the metal layer pattern and the metal compound layer as an etch barrier to form a variable resistance element having an external side aligned with an external side of the metal compound layer. An external part of the metal layer pattern may be transformed into a metal compound layer. The metal compound layer may have a low etch rate as an etch barrier.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: October 24, 2017
    Assignee: SK hynix Inc.
    Inventors: Min-Suk Lee, Chang-Hyup Shin
  • Patent number: 9793406
    Abstract: A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-? dielectric layer and a gate electrode. The high-? dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-? dielectric layer.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 9786565
    Abstract: A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nMOS gate electrode formed in an nMOS region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: October 10, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hidenobu Fukutome, Mitsugu Tajima
  • Patent number: 9786754
    Abstract: A method for forming a semiconductor device structure is provided. The method includes: forming a plurality of trenches in the substrate; forming a gate dielectric layer lining the trenches; filling the trenches with a gate material; etching back the gate material to expose an upper portion of the trenches; forming a first dielectric layer to refill the upper portion of the trenches, and to cover a substrate surface between the trenches; performing a first chemical mechanical planarization process to partially remove the first dielectric layer until the substrate surface between the trenches is exposed. The method also includes using the first dielectric layer in the upper portion of the trenches as an etching mask, etching the substrate through the exposed substrate surface to form a self-aligned contact opening between the trenches.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: October 10, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chung-Yeh Lee, Chih-Ping Lin
  • Patent number: 9741799
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor layer, a gate insulating film formed on the silicon carbide semiconductor layer, and a gate electrode provided on the gate insulating film, wherein the gate electrode has a polysilicon layer at least on a side of an interface with the gate insulating film, and the gate insulating film has an oxide film derived from the polysilicon layer, at an interface between the gate insulating film and the polysilicon layer of the gate electrode.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: August 22, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Taku Horii, Takeyoshi Masuda, Shunsuke Yamada
  • Patent number: 9685332
    Abstract: A method for self-aligned patterning includes providing a substrate, forming a patterned mandrel layer that includes a plurality of mandrel features, the patterned mandrel layer being formed on the substrate, depositing a first spacer layer over the mandrel layer, the first spacer layer comprising a first type of material, anisotropically etching the first spacer layer to leave a first set of spacers on sidewalls of the mandrel features, removing the mandrel layer, depositing a second spacer layer over remaining portions of the first set of spacers, and anisotropically etching the second spacer layer to form a second set of spacers on sidewalls of the first set of spacers.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: June 20, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: De-Fang Chen, Huan-Just Lin, Chun-Hung Lee, Chao-Cheng Chen
  • Patent number: 9660084
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 9613803
    Abstract: A method provides a substrate having a top surface; forming a first semiconductor layer on the top surface, the first semiconductor layer having a first unit cell geometry; epitaxially depositing a layer of a metal-containing oxide on the first semiconductor layer, the layer of metal-containing oxide having a second unit cell geometry that differs from the first unit cell geometry; ion implanting the first semiconductor layer through the layer of metal-containing oxide; annealing the ion implanted first semiconductor layer; and forming a second semiconductor layer on the layer of metal-containing oxide, the second semiconductor layer having the first unit cell geometry. The layer of metal-containing oxide functions to inhibit propagation of misfit dislocations from the first semiconductor layer into the second semiconductor layer. A structure formed by the method is also disclosed.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: April 4, 2017
    Assignee: International Business Machines Corporation
    Inventor: Alexander Reznicek
  • Patent number: 9595443
    Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: March 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming Zhu, Hui-Wen Lin, Harry-Hak-Lay Chuang, Bao-Ru Young, Yuan-Sheng Huang, Ryan Chia-Jen Chen, Chao-Cheng Chen, Kuo-Cheng Ching, Ting-Hua Hsieh, Carlos H. Diaz
  • Patent number: 9577055
    Abstract: The present disclosure relates to a semiconductor device. Such a semiconductor device includes a trench metal-oxide-semiconductor (MOS) transistor having two or more electrodes in a trench formed on a substrate of the semiconductor, where a part of a shield electrode positioned at a bottom of the trench is formed to have a large thickness, and a groove is formed in a gate electrode that is stacked on the shield electrode, such that a part of the shield electrode protrudes to a surface of the semiconductor device so as to be connected with a source power. In such a manner, by minimizing a region in which the shield electrode and the gate electrode overlap, a region that decreases problematic effects, such as leakage current of gate/source or gate/drain of a trench MOS transistor, and a region where high difference of a gate electrode is generated, are removed.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: February 21, 2017
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Jin Woo Han
  • Patent number: 9570505
    Abstract: In image sensors and methods of manufacturing the same, a substrate has a photoelectric conversion area, a floating diffusion area and a recess between the photoelectric conversion area and the floating diffusion area. A plurality of photodiodes is vertically arranged inside the substrate in the photoelectric conversion area. A transfer transistor is arranged along a surface profile of the substrate having the recess and configured to transfer electric charges generated from the plurality of photodiodes to the floating diffusion area. The transfer transistor includes a gate insulation pattern on a sidewall and a bottom of the recess and on a surface of the substrate around the recess, and a gate conductive pattern including polysilicon doped with impurities and positioned on the gate insulation pattern along the surface profile of the substrate having the recess, wherein a cavity is in an upper surface of the gate conductive pattern.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: February 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ihara Hisanori