Abstract: Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO2 or low-k dielectric sidewall spacer. Embodiments include transistors comprising a trench silicide layer spaced apart from a replacement metal gate electrode, and a layer of SiO2 or low-k material on a side surface of the replacement metal gate electrode facing the trench silicide layer. Implementing methodologies may include forming an intermediate structure comprising a removable gate with nitride spacers, removing the removable gate, forming a layer of high-k material on the nitride spacers, forming a layer of metal nitride on the high-k material, filling the opening with insulating material and then removing a portion thereof to form a recess, removing the metal nitride layers and layers of high-k material, depositing a layer of SiO2 or low-k material, and forming a replacement metal gate in the remaining recess.

Abstract: A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal.

Abstract: A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion.

Abstract: Techniques are described to form a low-noise, high-gain semiconductor device. In one or more implementations, the device includes a substrate including a first dopant material having a concentration ranging from about 1×1010/cm3 to about 1×1019/cm3. The substrate also includes at least two active regions formed proximate to a surface of the substrate. The at least two active regions include a second dopant material, which is different than the first dopant material. The device further includes a gate structure formed over the surface of the substrate between the active regions. The gate structure includes a doped polycrystalline layer and an oxide layer formed over the surface between the surface and the doped polycrystalline layer. The doped polycrystalline layer includes the first dopant material having a concentration ranging from about 1×1019/cm3 to about 1×1021/cm3.

Abstract: A semiconductor device and a method of forming the semiconductor device includes: forming gate electrodes on a semiconductor substrate and forming spacers on both side surfaces of the gate electrodes; forming capping patterns on the gate electrodes; and forming a metal contact between the gate electrodes. Each of the capping patterns is formed to have a width greater than a width of each of the gate electrodes.

Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed.

Abstract: An object is to provide a field effect transistor (FET) having a conductor-semiconductor junction, which has excellent characteristics, which can be manufactured through an easy process, or which enables high integration. Owing to the junction between a semiconductor layer and a conductor having a work function lower than the electron affinity of the semiconductor layer, a region into which carriers are injected from the conductor is formed in the semiconductor layer. Such a region is used as an offset region of the FET or a resistor of a semiconductor circuit such as an inverter. Further, in the case of setting up such an offset region and a resistor in one semiconductor layer, an integrated semiconductor device can be manufactured.

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a Field Effect Transistor with a low resistance metal gate electrode. An exemplary structure for a gate electrode for a Field Effect Transistor comprises a lower portion formed of a first metal material having a recess and a first resistance; and an upper portion formed of a second metal material having a protrusion and a second resistance, wherein the protrusion extends into the recess, wherein the second resistance is lower than the first resistance.

Abstract: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

Abstract: A semiconductor device includes a substrate having an active region and a device isolation layer defining the active region, a gate electrode on the active region, source/drain regions at the active region at both sides of the gate electrode, a buffer insulating layer on the device isolation layer, an etch stop layer formed on the buffer insulating layer and extending onto the gate electrode and the source/drain region, a first interlayer insulating layer on the etch stop layer, a first contact and a second contact penetrating the first interlayer insulating layer and the etch stop layer. The first contact and the second contact are spaced apart from each other and are in contact with the source/drain region and the buffer insulating layer, respectively.

Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.

Abstract: Methods for forming an electronic device having a fluorine-stabilized semiconductor substrate surface are disclosed. In an exemplary embodiment, a layer of a high-? dielectric material is formed together with a layer containing fluorine on a semiconductor substrate. Subsequent annealing causes the fluorine to migrate to the surface of the semiconductor (for example, silicon, germanium, or silicon-germanium). A thin interlayer of a semiconductor oxide may also be present at the semiconductor surface. The fluorine-containing layer can comprise F-containing WSix formed by ALD from WF6 and SiH4 precursor gases. A precise amount of F can be provided, sufficient to bind to substantially all of the dangling semiconductor atoms at the surface of the semiconductor substrate and sufficient to displace substantially all of the hydrogen atoms present at the surface of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate and a gate insulation layer formed over the semiconductor substrate. A gate electrode is formed over the gate insulation layer. The gate electrode includes a silicon-containing electrode including a dopant, a capturing material to capture the dopant, and an activation control material to control an activation of the dopant.

Abstract: Provided is a semiconductor structure including a gate structure, a first spacer, and a second spacer. The gate structure is formed on a substrate and includes a gate material layer, a first hard mask layer disposed on the gate material layer, and a second hard mask layer disposed on the first hard mask layer. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed adjacent to the first spacer. The etch rate of the first hard mask layer, the etch rate of the first spacer, and the etch rate of the second spacer are substantially the same and significantly smaller than the etch rate of the second hard mask layer in a rinsing solution.

Abstract: A semiconductor device includes a workpiece and a first material layer disposed over the workpiece. The first material layer has a first number of atoms at a surface. A seed layer is disposed over the first material layer. The seed layer includes a chemisorbed monolayer of a second number of atoms at the surface having a surface coverage of at least 0.5 such that the ratio of the number of first atoms at the surface to the number of second atoms at the surface is no more than 2:1. The second atoms of the seed layer include oxygen or nitrogen.

Abstract: Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA.

Abstract: The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.

Abstract: One method disclosed herein includes forming a conformal liner layer in a plurality of trenches that define a fin, forming a layer of insulating material above the liner layer, exposing portions of the liner layer, removing portions of the liner layer so as to result in a generally U-shaped liner positioned at a bottom of each of the trenches, performing at least one third etching process on the layer of insulating material, wherein at least a portion of the layer of insulating material is positioned within a cavity of the U-shaped liner layer, and forming a gate structure around the fin. A FinFET device disclosed herein includes a plurality of trenches that define a fin, a local isolation that includes a generally U-shaped liner that defines, in part, a cavity and a layer of insulating material positioned within the cavity, and a gate structure positioned around the fin.

Abstract: A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor.

Abstract: Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor.

Abstract: A fully silicided gate with a selectable work function includes a gate dielectric over the substrate, a first metal silicide layer over the gate dielectric, and a second metal silicide layer wherein the first metal silicide has a different phase then the second metal silicide layer. The metal silicide layers comprises at least one alloy element. The concentration of the alloy element on the interface between the gate dielectric and the metal silicide layers influence the work function of the gate.

Abstract: A semiconductor device includes a layer of semiconductor material having an active transistor region defined therein, an isolation trench formed in the semiconductor material adjacent the active transistor region, and a trench liner lining the isolation trench, wherein the trench liner is formed from a material that substantially inhibits formation of high-k material thereon, and wherein the isolation trench and the trench liner together form a lined trench. The device has an insulating material in the lined trench, and high-k gate material overlying at least a portion of the insulating material and overlying at least a portion of the active transistor region, such that the trench liner divides and separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region.

Abstract: A field effect transistor device includes a first gate stack portion including a dielectric layer disposed on a substrate, a first TiN layer disposed on the dielectric layer, a metallic layer disposed on the dielectric layer, and a second TiN layer disposed on the metallic layer, a first source region disposed adjacent to the first gate stack portion, and a first drain region disposed adjacent to the first gate stack portion.

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a source and a drain in the substrate, a gate electrode disposed over the substrate between the source and drain. An inner spacer is disposed at least partially over the gate electrode. An outer spacer is disposed adjacent to a sidewall of the gate electrode.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a region; a gate structure disposed on the region of the substrate; a raised epitaxial layer disposed in the substrate adjacent to two sides of the gate structure, wherein the surface of the raised epitaxial layer is even with the surface of the gate structure.

Abstract: The present invention relates to memory devices incorporating therein a novel memory cell architecture which includes an array of selection transistors sharing a common channel and method for making the same. A memory device comprises a semiconductor substrate having a first type conductivity, a plurality of drain regions and a common source region separated by a common plate channel in the substrate, and a selection gate disposed on top of the plate channel with a gate dielectric layer interposed therebetween. The plurality of drain regions and the common source region have a second type conductivity opposite to the first type provided in the substrate.

Abstract: A semiconductor device includes: a channel layer made of GaN; a barrier layer formed on the channel layer, the bather layer being made of AlGaN and having a larger band gap than the channel layer; a p-type GaN layer selectively formed on the barrier layer; a gate electrode made of ITO on the p-type GaN layer; and a source electrode and a drain electrode on regions of the barrier layer laterally outward of the gate electrode. The width of the gate electrode in the gate length direction is smaller than or equal to the width of the p-type GaN layer in the gate length direction, and the difference between the width of the gate electrode in the gate length direction and the width of the p-type GaN layer in the gate length direction is less than or equal to 0.2 ?m.

Abstract: A method of fabricating a FINFET includes the following steps. A plurality of fins is patterned in a wafer. A dummy gate is formed covering a portion of the fins which serves as a channel region. Spacers are formed on opposite sides of the dummy gate. The dummy gate is removed thus forming a trench between the spacers that exposes the fins in the channel region. A nitride material is deposited into the trench so as to cover a top and sidewalls of each of the fins in the channel region. The wafer is annealed to induce strain in the nitride material thus forming a stressed nitride film that covers and induces strain in the top and the sidewalls of each of the fins in the channel region of the device. The stressed nitride film is removed. A replacement gate is formed covering the fins in the channel region.

Abstract: The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate.

Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.

Abstract: A method of forming a gate structure is provided. The method includes providing a metal layer in the gate structure, the metal layer includes an oxygen-gettering composition. The metal layer getters oxygen from the interface layer, which may decrease the thickness of the interface layer. The gettered oxygen converts the metal layer to a metal oxide, which may act as a gate dielectric for the gate structure. A multi-layer metal gate structure is also provided including a oxygen-gettering metal layer, an oxygen-containing metal layer, and a polysilicon interface metal layer overlying a high-k gate dielectric.

Abstract: The present disclosure provides a semiconductor device which includes a semiconductor substrate, a first gate structure disposed over the substrate, the first gate structure including a first gate electrode of a first conductivity type, a second gate structure disposed over the substrate and proximate the first gate structure, the second gate structure including a second gate electrode of a second conductivity type different from the first conductivity type, a first doped region of the first conductivity type disposed in the substrate, the first doped region including a first lightly doped region aligned with a side of the first gate structure, and a second doped region of the second conductivity type disposed in the substrate, the second doped region including a second lightly doped region aligned with a side of the second gate structure.

Abstract: A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is proviced. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.

Abstract: A thin film transistor (TFT), an array substrate including the TFT, and methods of manufacturing the TFT and the array substrate. The TFT includes an active layer, and a metal member that corresponds to a portion of each of the source region and the drain region of the active layer, and is arranged on the active layer, a portion of the metal member contacts the source and drain regions of the active layer and the source and drain electrodes, and portions of the active layer that corresponds to portions below the metal member of the active layer are not doped.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.

Abstract: Provided are a semiconductor device which enables reduction of diffusion of Si in the manufacturing process of an MIPS element and suppression of an increase in EOT, and a method of manufacturing the same. An embodiment of the present invention is a semiconductor device including a field effect transistor having a gate insulating film provided on a silicon substrate and a gate electrode provided on the gate insulating film. The gate electrode is a stack-type electrode including a conductive layer containing at least Ti, N, and O (oxygen) and a silicon layer provided on the conductive layer, and the concentration of oxygen in the conductive layer is highest in the side of the silicon layer.

Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.

Abstract: A field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer.

Abstract: A method of forming a transistor is disclosed, in which gate-to-substrate leakage is addressed by forming and maintaining a conformal oxide layer overlying the transistor gate. Using the method disclosed for an n-type device, the conformal oxide layer can be formed as part of the source-drain doping process. Subsequent removal of residual phosphorous dopants from the surface of the oxide layer is accomplished without significant erosion of the oxide layer. The removal step uses a selective deglazing process that employs a hydrolytic reaction, and an acid-base neutralization reaction that includes an ammonium hydroxide component.

Abstract: A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 ?, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region.

Abstract: There is provided a semiconductor device and a method of fabricating the same. The method of fabricating a semiconductor device according to the present invention comprises: forming a transistor structure including a gate, and source and drain regions on a semiconductor substrate; carrying out a first silicidation to form a first metal silicide layer on the source and drain regions; depositing a first dielectric layer on the substrate, the top of the first dielectric layer being flush with the top of the gate region; forming contact holes at the portions corresponding to the source and drain regions in the first dielectric layer; and carrying out a second silicidation to form a second metal silicide at the gate region and in the contact holes, wherein the first metal silicide layer is formed to prevent silicidation from occurring at the source and drain regions during the second silicidation.

Abstract: A non-planar semiconductor transistor device includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness, a work-function electrode layer covers the dielectric layer and is arranged with a substantially uniform layer thickness, and a metal layer, distinct from the work-function electrode layer, covers the work-function electrode layer and is arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels.

Abstract: Methods are provided for fabricating an integrated circuit that includes metal filled narrow openings. In accordance with one embodiment a method includes forming a dummy gate overlying a semiconductor substrate and subsequently removing the dummy gate to form a narrow opening. A layer of high dielectric constant insulator and a layer of work function-determining material are deposited overlying the semiconductor substrate. The layer of work function-determining material is exposed to a nitrogen ambient in a first chamber. A layer of titanium is deposited into the narrow opening in the first chamber in the presence of the nitrogen ambient to cause the first portion of the layer of titanium to be nitrided. The deposition of titanium continues, and the remaining portion of the layer of titanium is deposited as substantially pure titanium. Aluminum is deposited overlying the layer of titanium to fill the narrow opening and to form a gate electrode.

Abstract: A device includes a metal-oxide-semiconductor (MOS) device, which includes a gate electrode and a source/drain region adjacent the gate electrode. A first and a second contact plug are formed directly over and electrically connected to two portions of a same MOS component, wherein the same MOS component is one of the gate electrode and the source/drain region. The same MOS component is configured to be used as a resistor that is connected between the first and the second contact plugs.

Abstract: The present invention is directed to a field effect transistor having a trough channel structure. The transistor comprises a semiconductor substrate of a first conductivity type having a trough structure therein with the trough structure extending along a first direction; an insulating layer formed on top of the trough structure; a gate formed on top of the insulator layer in a second direction perpendicular to the first direction and extending over and into the trough structure with a gate dielectric layer interposed therebetween; a source and a drain of a second conductivity type opposite to the first conductivity type formed in the trough structure on opposite sides of the gate.

Abstract: A structure and a process for a microelectromechanical system (MEMS)-based sensor are provided. The structure for a MEMS-based sensor includes a substrate chip. A first insulating layer covers a top surface of the substrate chip. A device layer is disposed on a top surface of the first insulating layer. The device layer includes a periphery region and a sensor component region. The periphery region and a sensor component region have an air trench therebetween. The component region includes an anchor component and a moveable component. A second insulating layer is disposed on a top surface of the device layer, bridging the periphery region and a portion of the anchor component. A conductive pattern is disposed on the second insulating layer, electrically connecting to the anchor component.

Abstract: Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is disposed in the insulating layer and the liner, the first contact plug disposed above and in contact with a portion of the active area, the first contact plug including a first conductive material. A second contact plug is disposed in the insulating layer and the liner, the second contact plug disposed above and in contact with a portion of the gate electrode, the second contact plug includes the first conductive material. A contact material layer is disposed in the active region, the contact material layer disposed under the first contact plug and includes the first conductive material.

Abstract: A semiconductor device and a method of manufacturing a gate stack for such a semiconductor device. The device includes a gate stack that has a gate insulation layer provided over a channel region of the device, and a metal layer that is insulated from the channel region by the gate insulation layer. The metal layer contains work function modulating impurities which have a concentration profile that varies along a length of the metal layer from the source region to the drain region. The gate stack has a first effective work function in the vicinity of a source region and/or the drain region of the device and a second, different effective work function toward a center of the channel region.

Abstract: A transistor having a metal nitride layer pattern, etchant and methods of forming the same is provided. A gate insulating layer and/or a metal nitride layer may be formed on a semiconductor substrate. A mask layer may be formed on the metal nitride layer. Using the mask layer as an etching mask, an etching process may be performed on the metal nitride layer, forming the metal nitride layer pattern. An etchant, which may have an oxidizing agent, a chelate agent and/or a pH adjusting mixture, may perform the etching. The methods may reduce etching damage to a gate insulating layer under the metal nitride layer pattern during the formation of a transistor.

Abstract: A semiconductor device and associated methods, the semiconductor device including a semiconductor substrate with a first well region, a first gate electrode disposed on the first well region, and a first N-type capping pattern, a first P-type capping pattern, and a first gate dielectric pattern disposed between the first well region and the first gate electrode.