Gate Electrode Of Refractory Material (e.g., Polysilicon Or A Silicide Of A Refractory Or Platinum Group Metal) Patents (Class 257/412)
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Patent number: 8975666Abstract: A MOS transistor includes a gate structure on a substrate, and the gate structure includes a wetting layer, a transitional layer and a low resistivity material from bottom to top, wherein the transitional layer has the properties of a work function layer, and the gate structure does not have any work function layers. Moreover, the present invention provides a MOS transistor process forming said MOS transistor.Type: GrantFiled: August 22, 2012Date of Patent: March 10, 2015Assignee: United Microelectronics Corp.Inventors: Ya-Hsueh Hsieh, Chi-Mao Hsu, Hsin-Fu Huang, Min-Chuan Tsai, Chien-Hao Chen, Chi-Yuan Sun, Wei-Yu Chen, Chin-Fu Lin
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Publication number: 20150061042Abstract: A metal gate structure is provided. The metal gate structure includes a semiconductor substrate, a gate dielectric layer, a multi-layered P-type work function layer and a conductive metal layer. The gate dielectric layer is disposed on the semiconductor substrate. The multi-layered P-type work function layer is disposed on the gate dielectric layer, and the multi-layered P-type work function layer includes at least a crystalline P-type work function layer and at least an amorphous P-type work function layer. Furthermore, the conductive metal layer is disposed on the multi-layered P-type work function layer.Type: ApplicationFiled: September 3, 2013Publication date: March 5, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Tsun-Min Cheng, Nien-Ting Ho, Chien-Hao Chen, Ching-Yun Chang, Hsin-Fu Huang, Min-Chuan Tsai, Chi-Yuan Sun, Chi-Mao Hsu
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Publication number: 20150061035Abstract: Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers.Type: ApplicationFiled: November 7, 2014Publication date: March 5, 2015Inventors: Ching-Kun Huang, Shih-Che Lin, Hung-Chih Yu
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Publication number: 20150041926Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: ApplicationFiled: September 30, 2011Publication date: February 12, 2015Inventors: Sameer S. Pradhan, Daniel B. Bergstrom, Julia Chiu
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Patent number: 8951901Abstract: In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior.Type: GrantFiled: July 22, 2011Date of Patent: February 10, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Sven Beyer, Berthold Reimer, Falk Graetsch
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Patent number: 8951856Abstract: Techniques are described to form a low-noise, high-gain semiconductor device. In one or more implementations, the device includes a substrate including a first dopant material having a concentration ranging from about 1×1010/cm3 to about 1×1019/cm3. The substrate also includes at least two active regions formed proximate to a surface of the substrate. The at least two active regions include a second dopant material, which is different than the first dopant material. The device further includes a gate structure formed over the surface of the substrate between the active regions. The gate structure includes a doped polycrystalline layer and an oxide layer formed over the surface between the surface and the doped polycrystalline layer. The doped polycrystalline layer includes the first dopant material having a concentration ranging from about 1×1019/cm3 to about 1×1021/cm3.Type: GrantFiled: February 26, 2014Date of Patent: February 10, 2015Assignee: Maxim Integrated Products, Inc.Inventors: Xiang Lu, Albert Bergemont
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Patent number: 8946035Abstract: A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed and are replaced with a replacement channel material formed by an epitaxial growth/deposition process to include a first dopant concentration level less than a first dopant concentration level. A subsequent doping operation or operations is then used to boost the average dopant concentration to a level greater than the first dopant concentration level. The replacement channel material is formed to include a gradient in which the upper portion of the replacement channel material has a greater dopant concentration than the lower portion of replacement channel material.Type: GrantFiled: September 27, 2012Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Lien Huang, Ming-Huan Tsai, Clement Hsingjen Wann
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Publication number: 20150028430Abstract: Semiconductor devices and methods of manufacturing the same are disclosed. The semiconductor device a gate dielectric pattern on a substrate and a gate electrode on the gate dielectric pattern opposite the substrate. The gate electrode includes a first conductive pattern disposed on the gate dielectric pattern and including aluminum, and a second conductive pattern disposed between the first conductive pattern and the gate dielectric pattern. The second conductive pattern has an aluminum concentration that is higher than an aluminum concentration of the first conductive pattern. The second conductive pattern may be thicker than the first conductive pattern.Type: ApplicationFiled: June 27, 2014Publication date: January 29, 2015Inventors: Junehee Lee, Sangjin Hyun, Jaeyeol Song, Hye-Lan Lee
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Publication number: 20150028431Abstract: The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing an O2 flash while shaping gate spacers, and then cleaning and applying a second application of Aqua Regia. Embodiments include sputter depositing a layer of Ni/Pt on a semiconductor substrate, annealing the Ni/Pt layer, wet stripping unreacted Ni, annealing the Ni stripped Ni/Pt layer, stripping unreacted Pt from the annealed Ni/Pt layer, e.g., with Aqua Regia, treating the Pt stripped Ni/Pt layer with an oxygen plasma, cleaning the Ni/Pt layer, and stripping unreacted Pt from the cleaned Ni/Pt layer, e.g., with a second application of Aqua Regia.Type: ApplicationFiled: October 14, 2014Publication date: January 29, 2015Inventors: Peter BAARS, Marco LEPPER, Uwe KAHLER, Vivien SCHROEDER
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Patent number: 8940596Abstract: A method includes removing a first portion of a gate layer of a structure. The structure includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer directly on the gate dielectric layer, and the gate layer directly on the gate conductive layer. A drain contact region is formed on the drain region, and a source contact region is formed on the source region. A conductive region is formed directly on the gate conductive layer and adjacent to a second portion of the gate layer. A gate contact terminal is formed in contact with the conductive region.Type: GrantFiled: October 21, 2013Date of Patent: January 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Ming-Hsiang Song, Kuo-Ji Chen, Ming Zhu, Po-Nien Chen, Bao-Ru Young
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Publication number: 20150021715Abstract: Techniques for integrating low temperature salicide formation in a replacement gate device process flow are provided. In one aspect, a method of fabricating a FET device is provided that includes the following steps. A dummy gate(s) is formed over an active area of a wafer. A gap filler material is deposited around the dummy gate. The dummy gate is removed selective to the gap filler material, forming a trench in the gap filler material. A replacement gate is formed in the trench in the gap filler material. The replacement gate is recessed below a surface of the gap filler material. A gate cap is formed in the recess above the replacement gate. The gap filler material is etched back to expose at least a portion of the source and drain regions of the device. A salicide is formed on source and drain regions of the device.Type: ApplicationFiled: July 22, 2013Publication date: January 22, 2015Applicant: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Gen P. Lauer, Isaac Lauer, Jeffrey W. Sleight
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Patent number: 8921181Abstract: Methods for forming an electronic device having a fluorine-stabilized semiconductor substrate surface are disclosed. In an exemplary embodiment, a layer of a high-? dielectric material is formed together with a layer containing fluorine on a semiconductor substrate. Subsequent annealing causes the fluorine to migrate to the surface of the semiconductor (for example, silicon, germanium, or silicon-germanium). A thin interlayer of a semiconductor oxide may also be present at the semiconductor surface. The fluorine-containing layer can comprise F-containing WSix formed by ALD from WF6 and SiH4 precursor gases. A precise amount of F can be provided, sufficient to bind to substantially all of the dangling semiconductor atoms at the surface of the semiconductor substrate and sufficient to displace substantially all of the hydrogen atoms present at the surface of the semiconductor substrate.Type: GrantFiled: December 27, 2012Date of Patent: December 30, 2014Assignee: Intermolecular, Inc.Inventor: Dipankar Pramanik
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Publication number: 20140374844Abstract: A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.Type: ApplicationFiled: September 11, 2014Publication date: December 25, 2014Inventors: Christian Lavoie, Zhengwen Li, Ahmet S. Ozcan, Filippos Papadatos, Chengwen Pei, Jian Yu
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Patent number: 8916460Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.Type: GrantFiled: May 5, 2014Date of Patent: December 23, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Byoung-Ho Kwon, Cheol Kim, Ho-Young Kim, Se-Jung Park, Myeong-Cheol Kim, Bo-Kyeong Kang, Bo-Un Yoon, Jae-Kwang Choi, Si-Young Choi, Suk-Hoon Jeong, Geum-Jung Seong, Hee-Don Jeong, Yong-Joon Choi, Ji-Eun Han
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Publication number: 20140367803Abstract: An intermediate semiconductor structure of a FinFET device in fabrication includes a substrate, a plurality of fin structures coupled to the substrate and a dummy gate disposed perpendicularly over the fin structures. A portion of the dummy gate is removed between the fin structures to create one or more vias and the one or more vias are filled with a dielectric. The dummy gate is then replaced with a metal gate formed around the dielectric-filled vias.Type: ApplicationFiled: June 13, 2013Publication date: December 18, 2014Inventors: Hong YU, Wang ZHENG, Huang LIU, Yongsik MOON
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Publication number: 20140367804Abstract: A transistor gate is formed of a stack of layers including a polysilicon layer and a tungsten layer separated by a barrier layer. A titanium layer reduces interface resistance. A tungsten liner reduces sheet resistance. The tungsten liner, a tungsten nitride barrier layer, and the tungsten layer may be formed sequentially in the same chamber.Type: ApplicationFiled: June 14, 2013Publication date: December 18, 2014Inventor: Naoki Takeguchi
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Patent number: 8912612Abstract: A FinFET structure which includes: silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; a gate wrapping around at least one of the silicon fins, the gate having a first surface and an opposing second surface facing the at least one of the silicon fins; a hard mask on a top surface of the gate; a silicon nitride layer formed in each of the first and second surfaces so as to be below and in direct contact with the hard mask on the top surface of the gate; spacers on the gate and in contact with the silicon nitride layer; and epitaxially deposited silicon on the at least one of the silicon fins so as to form a raised source/drain.Type: GrantFiled: August 30, 2013Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: Veeraraghavan S. Basker, Sanjay Mehta, Tenko Yamashita, Chun-Chen Yeh
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Publication number: 20140361385Abstract: Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure.Type: ApplicationFiled: June 6, 2013Publication date: December 11, 2014Inventors: Alban Zaka, Ran Yan, Nicolas Sassiat, El Mehdi Bazizi, Jan Hoentschel
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Publication number: 20140361386Abstract: Provided is a semiconductor device including a substrate, a gate structure, a second dielectric layer and a source/drain region. A first dielectric layer is disposed on the substrate, and the first dielectric layer has a trench therein. The gate structure is disposed on the substrate in the trench and includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench, and includes a TiAl3 phase metal layer. A height of the work function metal layer disposed on a sidewall of the trench is lower than a height of a top surface of the first dielectric layer. The metal layer fills the trench. The second dielectric layer is disposed between the gate structure and the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure.Type: ApplicationFiled: August 21, 2014Publication date: December 11, 2014Inventors: Hsin-Fu Huang, Kun-Hsien Lin, Chi-Mao Hsu, Min-Chuan Tsai, Tzung-Ying Lee, Chin-Fu Lin
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Patent number: 8900899Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.Type: GrantFiled: June 28, 2013Date of Patent: December 2, 2014Inventor: Payam Rabiei
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Patent number: 8901562Abstract: There are provided a transistor and a radiation imaging device in which a shift in a threshold voltage due to radiation exposure may be suppressed. The transistor includes a first gate electrode, a first gate insulator, a semiconductor layer, a second gate insulator, and a second gate electrode in this order on a substrate. Each of the first and second gate insulators includes one or a plurality of silicon compound films having oxygen, and a total sum of thicknesses of the silicon compound films is 65 nm or less.Type: GrantFiled: December 22, 2011Date of Patent: December 2, 2014Assignee: Sony CorporationInventors: Yasuhiro Yamada, Tsutomu Tanaka, Makoto Takatoku
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Patent number: 8900952Abstract: A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer. An annealing process may be applied to the scavenging metal stack during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material. A gate conductor layer is formed on the high-k gate dielectric layer. The gate conductor layer and the high-k gate dielectric layer are then patterned to provide a gate structure. A source region and a drain region are then formed on opposing sides of the gate structure.Type: GrantFiled: March 11, 2013Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Martin M. Frank, Isaac Lauer, Jeffrey W. Sleight
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Publication number: 20140346606Abstract: Gate-rounding fabrication techniques can be implemented to increase an effective channel length of a transistor and to consequently reduce the leakage current and static power consumption associated with the transistor. The transistor comprises a substrate region that includes a source region and a drain region. The transistor can also comprise a gate region that includes a main gate portion, one or more gate tips, and one or more corresponding gate-rounded portions. Each of the one or more gate tips is formed at a suitable position along the side of the main gate portion. During fabrication, the junction between the main gate region and each of the gate tips takes on a rounded shape to form a corresponding gate-rounded region. The gate-rounded regions increase the average length of the gate region and the effective channel length of the transistor.Type: ApplicationFiled: December 14, 2011Publication date: November 27, 2014Applicant: QUALCOMM IncorporatedInventors: Yanfei Cai, Ji Li
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Publication number: 20140346617Abstract: A semiconductor device includes an interlayer insulating film on a substrate, the interlayer insulating film including first and second trenches, a gate insulating film in the first and second trenches, a first conductivity type work function control film on the gate insulating film in the first trench, a second conductivity type work function control film on the gate insulating film in the second trench, a first gate metal on the first conductivity type work function control film, the first gate metal filling the first trench, a second gate metal on the gate insulating film in the second trench, and a carrier mobility improving film on the second conductivity type work function control film, the carrier mobility improving film filling the second trench.Type: ApplicationFiled: March 28, 2014Publication date: November 27, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Pil KIM, Yun-Young YEOH
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Patent number: 8889504Abstract: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. A method of forming a semiconductor structure includes forming sidewalls and spacers adjacent to a gate stack structure, and forming a recess in the gate stack structure. The method further includes epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure. The straining material is Si:C and the gate stack structure is a PFET gate stack structure. The straining material is grown above and covering a top surface of the sidewalls and the spacers.Type: GrantFiled: February 2, 2012Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Thomas W Dyer, Haining S Yang
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Patent number: 8884377Abstract: In one embodiment, first and second pattern structures respectively include first and second conductive line patterns and first and second hard masks sequentially stacked, and at least portions thereof extends in a first direction. The insulation layer patterns contact end portions of the first and second pattern structures. The first pattern structure and a first insulation layer pattern of the insulation layer patterns form a first closed curve shape in plan view, and the second pattern structure and a second insulation layer pattern of the insulation layer patterns form a second closed curve shape in plan view. The insulating interlayer covers upper portions of the first and second pattern structures and the insulation layer patterns, a first air gap between the first and second pattern structures, and a second air gap between the insulation layer patterns.Type: GrantFiled: February 18, 2013Date of Patent: November 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sok-Won Lee, Joon-Hee Lee, Jung-Dal Choi, Seong-Min Jo
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Patent number: 8883621Abstract: Provided is a semiconductor structure including a gate structure, a first spacer, and a second spacer. The gate structure is formed on a substrate and includes a gate material layer, a first hard mask layer disposed on the gate material layer, and a second hard mask layer disposed on the first hard mask layer. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed adjacent to the first spacer. The etch rate of the first hard mask layer, the etch rate of the first spacer, and the etch rate of the second spacer are substantially the same and significantly smaller than the etch rate of the second hard mask layer in a rinsing solution.Type: GrantFiled: December 27, 2012Date of Patent: November 11, 2014Assignee: United Microelectronics Corp.Inventors: Chia-Jung Li, Po-Chao Tsao
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Patent number: 8877621Abstract: Embodiments of the invention provide an approach for bottom-up growth of a low resistivity gate conductor. Specifically, a low resistivity metal (e.g., aluminum or cobalt) is selectively grown directly over metal layers in a set of gate trenches using a chemical vapor deposition or atomic layer deposition process to form the gate conductor.Type: GrantFiled: September 5, 2012Date of Patent: November 4, 2014Assignee: GLOBALFOUNDRIES Inc.Inventor: Hoon Kim
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Patent number: 8877645Abstract: Methods of forming an integrated circuit structure utilizing a selectively formed and at least partially oxidized metal cap over a gate, and associated structures. In one embodiment, a method includes providing a precursor structure including a transistor having a metal gate; forming an etch stop layer over an exposed portion of the metal gate; at least partially oxidizing the etch stop layer; and forming a dielectric layer over the at least partially oxidized etch stop layer.Type: GrantFiled: September 15, 2011Date of Patent: November 4, 2014Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, David V. Horak, Charles W. Koburger, III, Shom Ponoth
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Patent number: 8878311Abstract: A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.Type: GrantFiled: March 28, 2013Date of Patent: November 4, 2014Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kerber, Christian Lavoie
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Patent number: 8872286Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.Type: GrantFiled: August 22, 2011Date of Patent: October 28, 2014Assignee: United Microelectronics Corp.Inventors: Tsun-Min Cheng, Min-Chuan Tsai, Chih-Chien Liu, Jen-Chieh Lin, Pei-Ying Li, Shao-Wei Wang, Mon-Sen Lin, Ching-Ling Lin
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Patent number: 8860150Abstract: The metal gate structure of the present invention can include a TiN complex, and the N/Ti proportion of the TiN complex is decreased from bottom to top. In one embodiment, the TiN complex can include a single TiN layer, which has an N/Ti proportion gradually decreasing from bottom to top. In another embodiment, the TiN complex can include a plurality of TiN layers stacking together. In such a case, the lowest TiN layer has a higher N/Ti proportion than the adjusted TiN layer.Type: GrantFiled: December 10, 2009Date of Patent: October 14, 2014Assignee: United Microelectronics Corp.Inventors: Chin-Fu Lin, Nien-Ting Ho, Chun-Hsien Lin, Chih-Hao Yu, Cheng-Hsien Chou
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Publication number: 20140299939Abstract: Provided are a semiconductor device and a fabricating method of the semiconductor device. The semiconductor device may include an interlayer dielectric film formed on a substrate and including a trench, a gate insulating film formed in the trench, a first work function control film formed on the gate insulating film of the trench along bottom and sidewalls of the trench, a first metal gate pattern formed on the first work function control film of the trench and filling a portion of the trench, and a second metal gate pattern formed on the first metal gate pattern of the trench, the second metal gate pattern different from the first metal gate pattern.Type: ApplicationFiled: December 18, 2013Publication date: October 9, 2014Applicant: Samsung Electronics Co., Ltd.Inventor: Ju-Youn Kim
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Patent number: 8853788Abstract: In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function material portion to form a gate structure that enhances performance of a replacement gate field effect transistor.Type: GrantFiled: October 21, 2013Date of Patent: October 7, 2014Assignee: International Business Machines CorporationInventors: Dechao Guo, Shu-Jen Han, Keith Kwong Hon Wong, Jun Yuan
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Patent number: 8847292Abstract: Disclosed herein is a method for manufacturing a semiconductor device, the method including the step of forming a gate electrode that contains a metal over a semiconductor substrate with intermediary of a gate insulating film, the step including the sub-steps of, forming a first gate electrode layer that defines a work function of the gate electrode on the gate insulating film, forming a second gate electrode layer that has a barrier property for underlayers on the first gate electrode layer, and forming a third gate electrode layer of which resistance is lower than a resistance of the first gate electrode layer on the second gate electrode layer by chemical vapor deposition.Type: GrantFiled: June 18, 2007Date of Patent: September 30, 2014Assignee: Sony CorporationInventor: Shinpei Yamaguchi
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Publication number: 20140284728Abstract: A metal silicide thin film and ultra-shallow junctions and methods of making are disclosed. In the present disclosure, by using a metal and semiconductor dopant mixture as a target, a mixture film is formed on a semiconductor substrate using a physical vapor deposition (PVD) process. The mixture film is removed afterwards by wet etching, which is followed by annealing to form metal silicide thin film and ultra-shallow junctions. Because the metal and semiconductor dopant mixture is used as a target to deposit the mixture film, and the mixture film is removed by wet etching before annealing, self-limiting, ultra-thin, and uniform metal silicide film and ultra-shallow junctions are formed concurrently in semiconductor field-effect transistor fabrication processes, which are suitable for field-effect transistors at the 14 nm, 11 nm, or even further technology node.Type: ApplicationFiled: December 12, 2012Publication date: September 25, 2014Applicant: FUDAN UNIVERSITYInventors: Dongping Wu, Peng Xu, Wei Zhang, Shi-Li Zhang
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Patent number: 8841733Abstract: A method of fabricating a semiconductor device includes following steps. A substrate is provided, wherein a first dielectric layer having a trench therein is formed on the substrate, a source/drain region is formed in the substrate at two sides of the trench, and a second dielectric layer is formed on the substrate in the trench. A first physical vapor deposition process is performed to form a Ti-containing metal layer in the trench. A second physical vapor deposition process is performed to form an Al layer on the Ti-containing metal layer in the trench. A thermal process is performed to anneal the Ti-containing metal layer and the Al layer so as to form a work function metal layer. A metal layer is formed to fill the trench.Type: GrantFiled: May 17, 2011Date of Patent: September 23, 2014Assignee: United Microelectronics Corp.Inventors: Hsin-Fu Huang, Kun-Hsien Lin, Chi-Mao Hsu, Min-Chuan Tsai, Tzung-Ying Lee, Chin-Fu Lin
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Publication number: 20140264640Abstract: The invention provides a semiconductor device, including: a substrate; a U-shaped gate dielectric layer formed on the substrate; and a dual work function metal gate layer on the inner surface of U-shaped gate dielectric layer, wherein the dual work function metal gate layer includes a first conductive type metal layer and a second conductive type metal layer.Type: ApplicationFiled: March 18, 2013Publication date: September 18, 2014Applicant: NANYA TECHNOLOGY CORP.Inventors: Shin-Yu Nieh, Tieh-Chiang Wu, Wei-Ming Liao, Jei-Cheng Huang, Hai-Han Hung, Hsiu-Chun Lee
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Publication number: 20140264641Abstract: When forming semiconductor devices with contact plugs comprising protection layers formed on sidewalls of etch stop layers to reduce the risk of shorts, the protection layers may be formed by performing a sputter process to remove material from a contact region and redeposit the removed material on the sidewalls of the etch stop layers.Type: ApplicationFiled: February 20, 2014Publication date: September 18, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Kai Frohberg, Marco Lepper, Katrin Reiche, Torsten Huisinga
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Patent number: 8836049Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. Moreover a semiconductor process forming said semiconductor structure is also provided.Type: GrantFiled: June 13, 2012Date of Patent: September 16, 2014Assignee: United Microelectronics Corp.Inventors: Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chien-Hao Chen, Wei-Yu Chen, Chi-Yuan Sun, Ya-Hsueh Hsieh, Tsun-Min Cheng
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Patent number: 8835296Abstract: The present invention provides an electronic component manufacturing method including a step of embedding a metal film. An embodiment of the present invention includes a first step of depositing a barrier layer containing titanium nitride on an object to be processed on which a concave part is formed and a second step of filling a low-melting-point metal directly on the barrier layer under a temperature condition allowing the low-melting-point metal to flow, by a PCM sputtering method while forming a magnetic field by a magnet unit including plural magnets which are arranged at grid points of a polygonal grid so as to have different polarities between the neighboring magnets.Type: GrantFiled: June 20, 2011Date of Patent: September 16, 2014Assignee: Canon Anelva CorporationInventors: Shunichi Wakayanagi, Takayuki Saito, Takuya Seino, Akira Matsuo, Koji Yamazaki, Eitaro Morimoto, Yohsuke Shibuya, Yu Sato, Naomu Kitano
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Patent number: 8836048Abstract: A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy layer present on a work function metal layer, and a dielectric capping layer present on the metal semiconductor alloy layer. The at least one gate sidewall spacer and the dielectric capping layer may encapsulate the metal semiconductor alloy layer within the gate structure.Type: GrantFiled: October 17, 2012Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Josephine B. Chang, Michael P. Chudzik, Martin M. Frank, Michael A. Guillorn, Christian Lavoie, Shreesh Narasimha, Vijay Narayanan
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Publication number: 20140252504Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Taiwan Semiconductor Manufacturing Company, Ltd
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Patent number: 8828825Abstract: The likelihood of forming silicon germanium abnormal growths, which can be undesirably formed on the gate electrode of a strained-channel PMOS transistor at the same time that silicon germanium source and drain regions are formed, is substantially reduced by using protection materials that reduce the likelihood that the gate electrode is exposed during the formation of the silicon germanium source and drain regions.Type: GrantFiled: July 16, 2012Date of Patent: September 9, 2014Assignee: Texas Instruments IncorporatedInventors: Hiroaki Niimi, James Joseph Chambers
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Patent number: 8829482Abstract: A programmable impedance memory device structure can include a multi-layer variable impedance memory element formed on a planar surface of a first barrier layer, the multi-layer variable impedance memory element comprising a plurality of layers substantially parallel to the planar surface, including a memory material layer in contact with the planar surface, the first barrier layer being formed above a first insulating layer; and a second barrier layer formed over the memory element having a top surface substantially parallel with the planar surface. The first and second barrier layers can have lower mobility rates for at least one element within the memory material layer than the first insulating layer, and the memory material layer can be programmable by application of an electrical field between at least two different impedance states.Type: GrantFiled: September 23, 2011Date of Patent: September 9, 2014Assignee: Adesto Technologies CorporationInventors: Antonio R. Gallo, Chakravarthy Gopalan, Yi Ma
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Patent number: 8829622Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.Type: GrantFiled: June 13, 2012Date of Patent: September 9, 2014Assignee: STMicroelectronics (Crolles 2) SASInventors: Grégory Bidal, Laurent Favennec, Raul Andres Bianchi
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Patent number: 8822332Abstract: A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer.Type: GrantFiled: April 26, 2013Date of Patent: September 2, 2014Assignees: STMicroelectronics S.A., Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Heimanu Niebojewski, Yves Morand, Cyrille Le Royer, Fabrice Nemouchi
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Publication number: 20140239420Abstract: A method of forming a FinFET structure which includes forming fins on a semiconductor substrate; forming a gate wrapping around at least one of the fins, the gate having a first surface and an opposing second surface facing the fins; depositing a hard mask on a top of the gate; angle implanting nitrogen into the first and second surfaces of the gate so as to form a nitrogen-containing layer in the gate that is below and in direct contact with the hard mask on top of the gate; forming spacers on the gate and in contact with the nitrogen-containing layer; and epitaxially depositing silicon on the at least one fin so as to form a raised source/drain. Also disclosed is a FinFET structure.Type: ApplicationFiled: February 25, 2013Publication date: August 28, 2014Applicant: International Business Machines CorporationInventors: Veeraraghavan S. Basker, Sanjay Mehta, Tenko Yamashita, Chun-Chen Yeh
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Patent number: 8816446Abstract: Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. A rare earth-rare earth alloy incorporated metal nitride layer is formed above a gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting NMOS transistors.Type: GrantFiled: September 23, 2011Date of Patent: August 26, 2014Assignee: Texas Instruments IncorporatedInventors: Hiroaki Niimi, Manuel Angel Quevedo-Lopez
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Patent number: 8816448Abstract: A semiconductor device including a semiconductor substrate, an interface layer formed on the semiconductor substrate including at least 1×1020 atoms/cm3 of S (Sulfur), a metal-semiconductor compound layer formed on the interface layer, the metal-semiconductor compound layer including at least 1×1020 atoms/cm3 of S in the its whole depth, and a metal electrode formed on the metal-semiconductor compound layer.Type: GrantFiled: October 30, 2009Date of Patent: August 26, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoshifumi Nishi, Atsuhiro Kinoshita