Abstract: Disclosed is an image sensor having an isolation structure. The isolation structure includes a deep well region of a first conductive type disposed in a substrate of a second conductive type and an isolation region disposed between charge accumulation regions for accumulating photo-charges in order to electrically isolate the charge accumulation regions from each other. The charge accumulation regions are disposed on the deep well region and have the second conductive type. The isolation region is connected with the deep well region and has the first conductive type.

Abstract: There is provided a solid state imaging apparatus including a pixel array in which a plurality of unit pixels are arranged two-dimensionally. Each pixel includes a photoelectric conversion element, a transfer transistor which transfers a charge accumulated in the photoelectric conversion element to floating diffusion, a reset transistor which resets the charge of the floating diffusion, and an output transistor which outputs the charge of the floating diffusion. The floating diffusion of at least one of the plurality of unit pixels is electrically connected via the output transistor.

Abstract: An imaging system may include an image sensor having an array of image pixels formed in a substrate. Each image pixel may include a photodiode directly coupled to an anti-blooming diode. The anti-blooming diode may be connected to a positive voltage supply line and may be configured to drain excess charge from the photodiode when the photodiode is saturated. The anti-blooming drain may be formed from an n-type diffusion region partially surrounded by a p-type doped layer. The p-type doped layer may be interposed between and in contact with the n-type diffusion region of the anti-blooming diode and an n-type doped region of the photodiode. The anti-blooming diode may begin to drain excess charge from the photodiode in response to the photodiode reaching a threshold potential during integration. If desired, multiple pixels may share a common anti-blooming diode.

Abstract: A lateral overflow drain and a channel stop are fabricated using a double mask process. Each lateral overflow drain is formed within a respective channel stop. Due to the use of two mask layers, one edge of each lateral overflow drain is aligned, or substantially aligned, with an edge of a respective channel stop.

Abstract: A solid-state imaging device includes: a plurality of substrates stacked via a wiring layer or an insulation layer; a light sensing section that is formed in a substrate, of the plurality of substrates, disposed on a light incident side and that generates a signal charge in accordance with an amount of received light; and a contact portion that is connected to a non-light incident-surface side of the substrate in which the light sensing section is formed and that supplies a desired voltage to the substrate from a wire in a wiring layer disposed on a non-light incident side of the substrate.

Abstract: Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into individual chips. Methods shown provide removal of defective chips and their replacement during the assembly process to improve manufacturing yield.

Abstract: An image sensor for an electronic device. The image sensor includes a first light sensitive element for collecting charge and having a first saturation value and a well surrounding at least a portion of the first light sensitive element and having a first doping concentration. The image sensor further includes a bridge region defined in the well and in communication with the first light sensitive element and having a second doping concentration and a blooming node in communication with the bridge region and a voltage source. The second doping concentration is less than the first doping concentration and when light sensitive element collects sufficient charge to reach the first saturation value, additional charge received by the light sensitive element travels to the blooming node via the bridge region.

Abstract: An imaging device is formed in a semiconductor substrate. The device includes a matrix array of photosites. Each photosite is formed of a semiconductor region for storing charge, a semiconductor region for reading charge specific to said photosite, and a charge transfer circuit configured so as to permit a transfer of charge between the charge storage region and the charge reading region. Each photosite further includes at least one buried first electrode. At least one part of that buried first electrode bounds at least one part of the charge storage region. The charge transfer circuit for each photosite includes at least one second buried electrode.

Abstract: Optically sensitive devices include a device comprising a first contact and a second contact, each having a work function, and an optically sensitive material between the first contact and the second contact. The optically sensitive material comprises a p-type semiconductor, and the optically sensitive material has a work function. Circuitry applies a bias voltage between the first contact and the second contact. The optically sensitive material has an electron lifetime that is greater than the electron transit time from the first contact to the second contact when the bias is applied between the first contact and the second contact. The first contact provides injection of electrons and blocking the extraction of holes. The interface between the first contact and the optically sensitive material provides a surface recombination velocity less than 1 cm/s.

Abstract: An image sensor includes a pixel array with a plurality of pixels. A pixel includes a photodiode, a first transfer gate, a storage gate, and a second transfer gate. The first transfer gate is controllable to transfer charge from the photodiode to under the storage gate. The storage gate is connected to a readout circuit to allow the readout circuit to read out a voltage level of a potential at the storage gate. The second transfer gate is controllable to transfer charge from under the storage gate. A method includes controlling the first transfer gate to transfer charge from the photodiode to under the storage gate, reading out a voltage level of a potential at the storage gate using the readout circuit that is connected to the storage gate, and controlling the second transfer gate to drain charge from under the storage gate.

Abstract: A solid-state imaging device includes: a gate electrode arranged over an upper surface of a semiconductor substrate; a photoelectric conversion portion formed over the semiconductor substrate to position under the gate electrode; an overflow barrier formed over the semiconductor substrate to position in a portion other than a position facing the gate electrode in a planar direction and adjoin a side face of the photoelectric conversion portion; and a drain formed over the semiconductor substrate to adjoin a side face of the overflow barrier opposite to a side face adjoining the photoelectric conversion portion.

Abstract: An imaging system may include an image sensor having an array of image pixels formed in a substrate. Each image pixel may include a photodiode directly coupled to an anti-blooming diode. The anti-blooming diode may be connected to a positive voltage supply line and may be configured to drain excess charge from the photodiode when the photodiode is saturated. The anti-blooming drain may be formed from an n-type diffusion region partially surrounded by a p-type doped layer. The p-type doped layer may be interposed between and in contact with the n-type diffusion region of the anti-blooming diode and an n-type doped region of the photodiode. The anti-blooming diode may begin to drain excess charge from the photodiode in response to the photodiode reaching a threshold potential during integration. If desired, multiple pixels may share a common anti-blooming diode.

Abstract: An image sensor including a plurality of pixels each including a charge collection region including an N-type region bounded by P-type regions and having an overlying P-type layer; and an insulated gate electrode positioned over the P-type layer and arranged to receive a gate voltage for conveying charges stored in the charge collection region through the P-type layer.

Abstract: Pixels, imagers and related fabrication methods are described. The described methods result in cross-talk reduction in imagers and related devices by generating depletion regions. The devices can also be used with electronic circuits for imaging applications.

Abstract: Demultiplexing systems and methods are discussed which may be small and accurate without moving parts. In some cases, demultiplexing embodiments may include optical filter cavities that include filter baffles and support baffles which may be configured to minimize stray light signal detection and crosstalk. Some of the demultiplexing assembly embodiments may also be configured to efficiently detect U.V. light signals and at least partially compensate for variations in detector responsivity as a function of light signal wavelength.

Abstract: A CMOS image sensor has a pixel array provided with a plurality of unit pixels arranged in a matrix shape of rows and columns. Each of the unit pixel includes a photocharge generation means for generating photocharges by absorbing an external light; and a sensing node for receiving the photocharges transferred from the photocharge generation means, wherein the sensing node of the unit pixel in a previous scan line is shared with a sensing node of a unit pixel in a current scan line in response to a line select signal of the current line.

Abstract: A solid-state imaging device includes a photoelectric conversion unit that is formed on a semiconductor substrate, a reading unit that reads signal charges of the photoelectric conversion unit, a gate insulating film and an electrode disposed thereon that constitute the reading unit, a light shielding film that covers the electrode, and an antireflection film that is formed on the photoelectric conversion unit and is constituted by films of four or more layers. The film of the lower layer of the antireflection film is also used as a stopper film during patterning, and a gap between the end of the light shielding film and the semiconductor substrate which is defined by interposing a plurality of films of the lower layer of the antireflection film is set so as to be smaller than the thickness of the gate insulating film.

Abstract: A solid-state imaging device includes: a plurality of substrates stacked via a wiring layer or an insulation layer; a light sensing section that is formed in a substrate, of the plurality of substrates, disposed on a light incident side and that generates a signal charge in accordance with an amount of received light; and a contact portion that is connected to a non-light incident-surface side of the substrate in which the light sensing section is formed and that supplies a desired voltage to the substrate from a wire in a wiring layer disposed on a non-light incident side of the substrate.

Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Abstract: Each of pixels 10 arranged in an array pattern includes a photoelectric conversion element 11, a transfer transistor 13 for transferring charges to a floating diffusion layer 12, and an amplifier transistor 14 for outputting the transferred charges to an output line. An insulating isolation part 22 isolates the adjacent photoelectric conversion elements 11, and isolates the photoelectric conversion element 11 and the amplifier transistor 14. The insulating isolation part 22 constitutes a first region A between the photoelectric conversion elements 11 where the amplifier transistor 14 is not arranged, and a second region B between the photoelectric conversion elements 11 where the amplifier transistor 14 is arranged. First and second isolation diffusion layers 23 and 24 are formed below the insulating isolation part 22, and the second isolation diffusion layer 24 is wider than the first isolation diffusion layer 23 in the first region A.

Abstract: A device includes a plurality of photoelectric conversion regions, an interlayer insulating film arranged on the plurality of photoelectric conversion regions, a protective insulating film that is arranged in contact with the interlayer insulating film and has a refractive index different from that of the interlayer insulating film, recesses arranged in a light-receiving surface of each of the plurality of photoelectric conversion regions, and embedded regions embedded in the recesses. When a wavelength of incident light to each of the plurality of photoelectric conversion regions is denoted by ? and a refractive index of the embedded regions is denoted by n, a depth d of the recesses is represented by an expression d??/4n.

Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Abstract: A method of manufacturing a solid state imaging device having a photo-electric conversion portion array and a transfer electrode array, these arrays being provided in parallel to each other, upper surfaces and side wall surfaces of the transfer electrode array being covered with a light-shielding layer, and a transparent layer showing an oxidizing property at the time of film formation, the transparent layer being formed on the photo-electric conversion parts and the light-shielding layer.

Abstract: A semiconductor device and a method for fabricating the same are described. The semiconductor device includes a well of a first conductive type, first doped regions of a second conductive type, gates of the second conductive type, second doped regions of the first conductive type, and isolation structures. The well is disposed in a substrate. The first doped regions are disposed in the well. The first doped regions are arranged in parallel and extend along a first direction. The gates are disposed on the substrate. The gates are arranged in parallel and extend along a second direction different from the first direction. One of the first doped regions is electrically connected to one of the gates. Each of the second doped regions is disposed in the first doped regions between two adjacent gates. Each of the isolation structures is disposed in the substrate between two adjacent first doped regions.

Abstract: A solid-state imaging device according to the present invention is of a MOS type and includes a plurality of pixels arranged in rows and columns, and includes: a semiconductor substrate; a photodiode which is formed in the semiconductor substrate and converts, into a signal charge, light that is incident from a first main surface of the semiconductor substrate; a transfer transistor which is formed in a second main surface of the semiconductor substrate and transfers the signal charge converted by the photodiode; a light shielding film which is conductive and formed on a boundary between the pixels, above the first main surface of the semiconductor substrate; an overflow drain region electrically connected to the light shielding film and formed in the first main surface of the semiconductor substrate; and an overflow barrier region formed between the overflow drain region and the photodiode.

Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Abstract: Embodiments of a pixel including a photosensitive region formed in a surface of a substrate and an overflow drain formed in the surface of the substrate at a distance from the photosensitive area, an electrical bias of the overflow drain being variable and controllable. Embodiments of a pixel including a photosensitive region formed in a surface of a substrate, a source-follower transistor coupled to the photosensitive region, the source-follower transistor including a drain, and a doped bridge coupling the photosensitive region to the drain of the source-follower transistor.

Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Abstract: Optically sensitive devices include a device comprising a first contact and a second contact, each having a work function, and an optically sensitive material between the first contact and the second contact. The optically sensitive material comprises a p-type semiconductor, and the optically sensitive material has a work function. Circuitry applies a bias voltage between the first contact and the second contact. The optically sensitive material has an electron lifetime that is greater than the electron transit time from the first contact to the second contact when the bias is applied between the first contact and the second contact. The first contact provides injection of electrons and blocking the extraction of holes. The interface between the first contact and the optically sensitive material provides a surface recombination velocity less than 1 cm/s.

Abstract: An image sensor formed in a semiconductor stack of a lower region of a first conductivity type and of an upper region of a second conductivity type, including: a photodiode formed of a first portion of the stack; a read area formed of a second portion of the stack; a trench with insulated walls filled with a conductive material, the trench surrounding the photodiode and the read area and being interrupted, all along its height, on a portion facing the photodiode and the read area; and first connection mechanism associated with the conductive material of the trench and capable of being connected to a reference bias voltage.

Abstract: An image sensor of various embodiments includes a pixel array. The pixel array includes a pixel having a photodiode and a transfer gate. The pixel array in various embodiments further includes an antiblooming channel extending from the photodiode to either (i) a pixel output area, or (ii) a drain of a source follower transistor. A method of some embodiments includes (i) driving from a first row driver one or more control signals over one or more control lines to one or more pixels, and (ii) driving from a second row driver the one or more control signals over the one or more control lines to the one or more pixels.

Abstract: A CMOS image sensor has a pixel array provided with a plurality of unit pixels arranged in a matrix shape of rows and columns. Each of the unit pixel includes a photocharge generation means for generating photocharges by absorbing an external light; and a sensing node for receiving the photocharges transferred from the photocharge generation means, wherein the sensing node of the unit pixel in a previous scan line is shared with a sensing node of a unit pixel in a current scan line in response to a line select signal of the current line.

Abstract: A method for making a solid-state imaging device includes forming a pinning layer, which is a P-type semiconductor layer or an N-type semiconductor layer, on a first substrate by deposition; forming a semiconductor layer on the pinning layer; forming a photoelectric conversion unit in the semiconductor layer, the photoelectric conversion unit being configured to convert incident light into an electrical signal; forming, on the semiconductor layer, a transistor of a pixel unit and a transistor of a peripheral circuit unit disposed in the periphery of the pixel unit, and then forming a wiring section on the semiconductor layer; bonding a second substrate on the wiring section; and removing the first substrate after the second substrate is bonded.

Abstract: A multicolor CMOS pixel sensor formed in a p-type semiconductor region includes a first detector formed from an n-type region of semiconductor material located near the surface of the p-type region. A first pinned p-type region is formed at the surface of the p-type region over the first detector, and has a surface portion extending past an edge of the pinned p-type region. A second detector is formed from an n-type region located in the p-type semiconductor region below the first detector. A second-detector n-type deep contact plug is in contact with the second detector and extends to the surface of the p-type semiconductor region. A second pinned p-type region is formed at the surface of the p-type semiconductor region over the top of the second-detector n-type deep contact plug. A surface portion of the second-detector deep contact plug extends past an edge of the second pinned p-type region.

Abstract: Channel stop sections formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate.

Abstract: A solid state imaging apparatus includes: a plurality of photoelectric conversion cells each including a plurality of photoelectric sections arranged in an array of at least two rows and two columns; a plurality of floating diffusion sections each being connected to each of ones of the photoelectric sections which are included in the same row of each said photoelectric conversion cell via each of a plurality of transfer transistors, and being shared by said ones of the photoelectric sections; a plurality of read-out lines each being selectively connected to at least two of the transfer transistors; and a plurality of pixel amplifier transistors each detecting and outputting the potential of each said the floating diffusion section. Charges of the photoelectric conversion sections each being connected to one of the read-out lines and being read out by the transfer transistors are read out by different floating diffusion sections.

Abstract: A solid state imaging apparatus includes: a plurality of photoelectric conversion cells each including a plurality of photoelectric sections arranged in an array of at least two rows and two columns; a plurality of floating diffusion sections each being connected to each of ones of the photoelectric sections which are included in the same row of each said photoelectric conversion cell via each of a plurality of transfer transistors, and being shared by said ones of the photoelectric sections; a plurality of read-out lines each being selectively connected to at least two of the transfer transistors; and a plurality of pixel amplifier transistors each detecting and outputting the potential of each said the floating diffusion section. Charges of the photoelectric conversion sections each being connected to one of the read-out lines and being read out by the transfer transistors are read out by different floating diffusion sections.

Abstract: A CMOS imaging system with increased charge storage of pixels yet decreased physical size, kTC noise and active area. A storage node is connected to the transfer gate and provides a storage node for a pixel, allowing for kTC noise reduction prior to readout. The pixel may be operated with the shutter gate on during the integration period to increase the amount of time for charge storage by a pixel.

Abstract: A source/drain region of a transistor or amplifier is formed in a substrate layer and is connected to a voltage source. A glow blocking structure is formed at least partially around the source/drain region and is disposed between the source/drain region and an imaging array of an image sensor. A trench is formed in the substrate layer adjacent to and at least partially around the source/drain region. The glow blocking structure includes an opaque material formed in the trench and one or more layers of light absorbing material overlying the source/drain region and the opaque material.

Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Abstract: Method and system for manufacturing CMOS image sensing device with reduced blooming. The method includes a step for providing a substrate material. The substrate material can be characterized by a first dimension and a second dimension. In addition, the method includes a step for defining an active region on the substrate material. The active region is characterized by a third dimension and a fourth dimension. The method further includes a step for defining a non-active region on the substrate material. The non-active region is different from the active region. The non-active region is characterized by a fifth dimension and a sixth dimension, the non-active region including a silicon material. The method includes a step for defining a depletion region within the active region. In addition, the method includes a step for forming an n-type region positioned above the depletion region.

Abstract: CMOS image sensors and methods of fabricating the same. The CMOS image sensors include a pixel array region having an active pixel portion and an optical block pixel portion which encloses the active pixel portion. The optical block pixel portion includes an optical block metal pattern for blocking light. The optical block metal pattern may be connected to a ground portion.

Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Abstract: Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO or SnO2. A gate insulator layer comprising a substantially transparent material is located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface. A second variant of the transistor includes a channel layer comprising a substantially transparent material selected from substantially insulating ZnO or SnO2, the substantially insulating ZnO or SnO2 being produced by annealing. Devices that include the transistors and methods for making the transistors are also disclosed.

Abstract: Embodiments of the present invention provide pixel cells with increased storage capacity, which are capable of anti-blooming operations. In an exemplary embodiment a pixel cell has an electronic shutter that transfers charge generated by a photo-conversion device to a storage node before further transferring the charge to the pixel cell's floating diffusion node. Each pixel cell also includes an anti-blooming transistor for directing excess charge out of each respective pixel cell, thus preventing blooming. Additionally, two or more pixel cells of an array may share a floating diffusion node and reset and readout circuitry.

Abstract: A CMOS imaging system with increased charge storage capacitance of pixels yet decreased physical size, kTC noise and active area. A capacitor is linked to the transfer gate and provides a storage node for a pixel, allowing for kTC noise reduction prior to readout. The pixel may be operated with the shutter gate on during the integration period to increase the amount of time for charge storage by a pixel.

Abstract: A solid-state imaging device that suppresses crosstalk of light in a semiconductor substrate that caused by diffraction of light is disclosed. According to one aspect of the present invention, there is provided a solid-state imaging device comprising a plurality of pixels, each pixel comprising a photoelectric conversion element that is provided in a semiconductor substrate and performs photoelectric conversion of incident light to store signal charges, a floating junction that is provided in the semiconductor substrate in the proximity of the photoelectric conversion element and temporarily stores signal charges, and a transfer transistor that transfers the signal charges stored in the photoelectric conversion element to the floating junction, wherein at least one transfer transistor includes a gate electrode extended to cover a corresponding photoelectric conversion element.

Abstract: Disclosed herein is a solid-state imaging element which includes a plurality of drive signal inputs, a plurality of bus lines, and a plurality of vertical transfer register electrodes. In the solid-state imaging element, a charge accumulated in light-receiving elements in a pixel region is vertically transferred by the drive signals input to the electrodes. Each of the electrodes has a contact part connected to the second contact and having a width smaller than a width of the electrodes in the pixel region, and a blank region is formed between predetermined adjacent two of the contact parts so that a width of the blank region is larger than a distance between respective two of the contact parts other than the predetermined adjacent two of the contact parts. The first contact is disposed on the blank region.

Abstract: The reduction in size, noise and voltage is realized in a MOS solid-state imaging device. A gate electrode in a pixel part is formed in a two-level structure. An amplifier gate of an amplifier transistor is formed in the first level while a select gate of a select transistor is formed in the second level. The both are structurally partly overlapped. With the first-level amplifier gate as self-alignment, ions are implanted for a select gate in the second level. Although the gate electrode if formed in one level as in the conventional requires a space of nearly a design rule between the amplifier gate and the select gate, the structure of the invention can eliminate such a dead space. Meanwhile, because the diffusion layer does not exist between the amplifier gate and the select gate, the diffusion layer is eliminated of sheet resistance and voltage drop.