With Metallic Conductor Within Isolating Dielectric Or Between Semiconductor And Isolating Dielectric (e.g., Metal Shield Layer Or Internal Connection Layer) Patents (Class 257/508)
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Patent number: 5382829Abstract: A semiconductor device including an insulating film substrate having a surface, a high frequency semiconductor chip disposed on the surface, and circuit elements disposed on the surface and connected to the semiconductor chip wherein the insulating film substrate is bent into a U-shape, laminated, and encapsulated with a resin. The package of the device is miniaturized.Type: GrantFiled: March 17, 1993Date of Patent: January 17, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Akira Inoue
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Patent number: 5373180Abstract: Through the use of a specifically configured buried dielectric region, devices with strict design rules, e.g., design rules of 0.9 micrometers and less, are significantly improved. In particular, the recessed dielectric region, e.g., field oxide, separating device areas in an integrated circuit, either has a buried conducting shield surrounding the periphery of the oxide or has a configuration such that the upper surface of the dielectric is no more than 20 nm below the upper surface of the silicon forming the device active region. By insuring a suitable configuration, parasitic capacitance resulting in slower operation is considerably reduced while leakage currents are maintained at an acceptable level.Type: GrantFiled: September 14, 1993Date of Patent: December 13, 1994Assignee: AT&T Corp.Inventors: Steven J. Hillenius, William T. Lynch, Lalita Manchanda, Mark R. Pinto, Sheila Vaidya
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Patent number: 5367189Abstract: A semiconductor device comprises a first electrode buried in one main face of a substrate and surrounded by a first insulator, a field oxide film covering the surface of the first electrode, a semiconductor layer connected with the first electrode, a second insulator covering the surface of the semiconductor layer, a second electrode connected with the semiconductor layer, a gate electrode connected with the semiconductor layer between the second insulator and the field oxide film, and an outgoing electrode connected with the first electrode.Type: GrantFiled: November 4, 1992Date of Patent: November 22, 1994Assignee: Fujitsu LimitedInventor: Shunji Nakamura
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Patent number: 5306942Abstract: A semiconductor layer is disposed on a semiconductor substrate and a first element is formed in a region of the semiconductor layer. A second element is formed in another region of the semiconductor layer. An insulating layer surrounds the perimeter of the first element, for electrically insulating and separating the first element from the second element and the semiconductor substrate. An electrical shield layer surrounds the perimeter of the first element, and is adapted to a reference electric potential applied thereto, for shielding the first element from an electrical fluctuation of the semiconductor substrate caused by the second element. An electrode is provided for applying the reference electric potential to the electrical shield layer.Type: GrantFiled: February 3, 1992Date of Patent: April 26, 1994Assignee: Nippondenso Co., Ltd.Inventor: Tetsuo Fujii
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Patent number: 5283461Abstract: The trench pattern of a dielectrically isolated island architecture is filled with doped polysilicon and used as an interconnect structure for circuit devices that are supported within the islands, thereby decreasing the amount of topside interconnect and reducing the potential for parasitics beneath tracks of surface metal. The trench pattern may serve as a voltage distribution network or provide crossunders beneath surface tracks. In addition, at least one of the islands may contain one or more auxiliary poly-filled trench regions to perform the crossunder function. Such an auxiliary trench region may be also provided in an island that contains a circuit device. Manufacture of the conductor-filled trench structure may be facilitated by depositing polysilicon over a dielectrically coated trench grid structure and then planarizing the polysilicon to the surface of the oxide dielectric. The exposed polysilicon is doped and then oxidized to seal the dopant, which forms a thin oxide layer on the poly.Type: GrantFiled: July 17, 1992Date of Patent: February 1, 1994Assignee: Harris CorporationInventor: James D. Beasom
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Patent number: 5266832Abstract: In a semiconductor apparatus and method for producing the same where an upper surface of a semiconductor chip having a thick film electrode is coated with a passivation film, the semiconductor chip being molded with a resin mold such as a power SIT, a conductive film made of a doped polysilicon, a metal material, or the like and which has a thickness of for example 3000 angstroms or more is circumferentially disposed from a bottom circumference of the thick film electrode to a part of region between a field oxide film and a passivation film so as to effectively prevent cracks in the passivation film caused by a cyclic temperature test from extending into the field oxide film.Type: GrantFiled: February 6, 1992Date of Patent: November 30, 1993Assignee: Kabushiki Kaisha Toyoda Jidoshokki SeisakushoInventors: Noriyuki Yamamoto, Yuri Otobe, Takanori Okabe, Minoru Kato
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Patent number: 5262353Abstract: A shielding structure (10) and method of formation. The shielding structure (10) has a substrate (12). A first dielectric layer (14) overlies the substrate (12). A conductive layer (16) is formed overlying the dielectric layer (14), is patterned, and is etched to form electrically isolated conductive regions from conductive layer (16). The electrically isolated conductive regions have sidewalls and the etching of conductive layer (16) exposes portions of dielectric layer (14). The exposed portions of dielectric layer (14) are etched to form trenched portions of dielectric layer (14). A second dielectric layer (18) is formed overlying the electrically isolated conductive regions, including the sidewalls, and overlying the trenched portions to create recessed regions that separate the electrically isolated conductive regions.Type: GrantFiled: February 3, 1992Date of Patent: November 16, 1993Assignee: Motorola, Inc.Inventors: Shih-Wei Sun, Yasunobu Kosa, John R. Yeargain
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Patent number: 5241209Abstract: A semiconductor device having a semiconductor substrate or an insulation layer, an integrated circuit on each of the opposite sides, or main surfaces, of the semiconductor substrate or insulation layer, and a path for an ultrasound signal interconnecting the integrated circuits. The path is afforded by an ultrasonic transducer on each of the opposite sides of the semiconductor substrate or insulation layer. A plurality of paths may be provided in the same semiconductor substrate or insulation layer without crosstalk by transmitting ultrasound signals having different frequencies through the respective paths. The paths may be one-way or two-way. The ultrasonic transducers each contain a piezoelectric material; the thickness of the piezoelectric material in the ultrasonic transducer, at least on the receiver side in each path, is such that the resonant frequency of the ultrasonic transducer corresponds to the frequency of the ultrasound signal signal transmitted through the path.Type: GrantFiled: July 24, 1991Date of Patent: August 31, 1993Assignee: Fujitsu LimitedInventor: Nobuo Sasaki
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Patent number: 5227658Abstract: A method for isolating areas of silicon from a substrate 50 includes the steps of: providing a buried N+ region 52 in the substrate; forming an intrinsic epitaxial layer 12 onto the N+ region; etching trenches 18, 20 through the intrinsic epitaxial layer to thereby form a desired isolation region 16 of intrinsic epitaxial material; laterally etching a cavity 22 underneath the desired isolation region; and, forming an insulation layer 24 of insulation material along the bottom of the desired isolation region exposed by the former etching steps.Type: GrantFiled: October 23, 1991Date of Patent: July 13, 1993Assignee: International Business Machines CorporationInventors: Klaus D. Beyer, San-Mei Ku, Victor J. Silvestri, Andrie S. Yapsir
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Patent number: 5223733Abstract: A semiconductor integrated circuit device is provided which include a plurality of cell columns each having a number of unit cells previously fabricated on a semiconductor substrate selected from the plural kinds of unit cells which are formed in desired circuits by electrically connecting circuit devices previously arranged. Each column includes at least one kind of unit cell of a dynamic circuit which has a node in a floating state during the operation of the cell unit. A fixed potential shield layer is also provided on the cell columns so as to cover the nodes of the dynamic circuits. By virtue of this, a wiring area for electrically connecting the desired cell units can be located between the cell columns and above the shield layer. In other words, signal wirings in the wiring area can pass over the nodes of the dynamic circuits. without adverse parasitic effects. The unit cell can also be provided with a precharge circuit comprising a standard cell and an in-cell wiring layer.Type: GrantFiled: November 14, 1991Date of Patent: June 29, 1993Assignee: Hitachi, Ltd.Inventors: Toshio Doi, Takehisa Hayashi, Kenichi Ishibashi, Mitsuo Asai
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Patent number: 5216280Abstract: For increasing the number of pads to be connected to external terminals such as leads of a lead frame without increasing an area of a semiconductor IC chip, pads are disposed at a periphery of the chip in such a manner that they are arranged in at least first and second rows, to which at least first and second groups of interconnection layers insulated through an interval insulator are electrically connected, respectively.Type: GrantFiled: January 23, 1992Date of Patent: June 1, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Yasunori Tanaka, Kyohsuke Ogawa
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Patent number: 5208480Abstract: A dynamic latch circuit which is fabricated in a semiconductor integrated circuit comprises a first circuit such as a clocked inverter and a second circuit such as an inverter. The first and second circuits are connected by a holding line. In the semiconductor integrated circuit, at least three interconnection layers are provided on a semiconductor substrate to be insulated by insulating layers, such that the holding line is provided as the secondly highest interconnection layer, and an output line of the second circuit is provided as the uppermost interconnection layer to be positioned on the straight upper side of the holding line. For this structure, a coupling capacitance which is formed between the holding line and a through line connected to a third circuit and provided as the uppermost interconnection layer is decreased.Type: GrantFiled: August 28, 1991Date of Patent: May 4, 1993Assignee: NEC CorporationInventor: Takashi Ishibashi
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Patent number: 5202571Abstract: An electron emitting device is provided with a p-semiconductor layer formed on a semiconductor substrate. The p-semiconductor layer is composed of a diamond layer.Type: GrantFiled: July 3, 1991Date of Patent: April 13, 1993Assignee: Canon Kabushiki KaishaInventors: Keiji Hirabayashi, Noriko Kurihara, Takeo Tsukamoto, Nobuo Watanabe, Masahiko Okunuki
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Patent number: 5200639Abstract: A semiconductor device has a device region, and a device separation region formed on a semiconductor substrate doped with impurities. And, the device separation region has a metal wiring formed on the surface of the device region or the back surface of the substrate. An aluminum region extending in the longitudinal direction connected to the metal wiring is formed within the device separation region.Type: GrantFiled: May 29, 1991Date of Patent: April 6, 1993Assignee: Canon Kabushiki KaishaInventors: Keiji Ishizuka, Yuzo Kataoka, Toshihiko Ichise, Hidekazu Takahashi, Hayao Ohzu
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Patent number: 5185650Abstract: A high-speed semiconductor integrated circuit device has a main circuit section formed on a substrate, and a capacitance section formed on the substrate to surround the main circuit section. The capacitance section is made up of two conductive layers, an upper layer being insulatively disposed above a lower layer. These layers are applied with a power source voltage and a ground voltage, respectively. High-speed signal lines insulatively traverse the capacitance section and are connected to the main circuit section. The capacitance section is disconnected in the region where each signal transmission line passes, and defines a micro-strip type signal transmission line path structure. A "ladder"-shaped connection pattern is provided at each disconnected portion of the capacitance section, for electrically connecting a conductive layer arranged on one side of the disconnected portion to the corresponding layer arranged on the other side of the disconnected portion.Type: GrantFiled: April 1, 1992Date of Patent: February 9, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Hirotsugu Wakimoto, Mitsuo Konno, Kunio Yoshihara