Abstract: An isolation structure providing electrical isolation in two dimensions between memory cells in semiconductor memory device. The isolation structure comprises a trench formed in a substrate of a semiconductor memory device such as a Dynamic Random Access Memory (DRAM). The trench is lined with an insulating material and filled with polysilicon to form a floating gate. An electrical charge is then injected into the polysilicon floating gate. The isolation structure is located between memory cells in an array to provide isolation between cells in sub-micron spacing by combining the characteristics of trench and field isolation. The electrical charge is injected into the polysilicon floating gate by applying a charging voltage to the wordlines of the memory cell array. The charging voltage is applied periodically as necessary to maintain effective isolation. Two dimensional isolation is achieved by extending the trench to surround each pair of memory cells sharing a common bitline contact.

Abstract: An electrical circuit and method substantially to mitigate the effects of a current increase due to a fault within the circuit. In particular, where the electrical circuit (80) includes a laser diode it is desirable to create a fault tolerant circuit to avoid a sudden increase in light intensity output by the laser diode. A track (44b) associated with the laser diode is identified and insulated by means of a layout of the circuit. Specifically, where the circuit is an integrated circuit, metal layers (42, 44, 46) and vias (50) are utilised to form an insulating shield (76) around the track (44b) associated with the laser diode.

Abstract: A semiconductor device is disclosed, which comprises a semiconductor substrate, drain and source regions of a MOS transistor, a gate electrode formed on a surface of a channel region of the MOS transistor trench type element isolation regions in each of which an insulating film is formed on a surface of a trench formed in the surface of the semiconductor substrate, the element isolation regions sandwiching the channel region from opposite sides thereof in a channel width direction, and a conductive material layer for a back gate electrode, which is embedded in a trench of at least one of the element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under the channel region of the MOS transistor or to voltage-control the semiconductor substrate region.

Abstract: Apparatus and methods for manufacturing low-resistant substrate contacts in integrated circuits are disclosed. The contacts are low resistive conducting plugs and are located outside the areas of active components. The substrate is connected from the top portion in order to obtain a low resistance. Multiple metal plugs electrically interconnect the substrate of the integrated circuit with the top portion of the integrated circuit.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer, which has been implanted with a compounding material, lines the channel opening. A conductor core fills the opening over the barrier layer. The barrier layer having a dielectric layer proximate portion of a barrier compound varying into a conductor core proximate portion of a pure barrier material.

Abstract: In a semiconductor device having a multilayer interconnection structure, the contact resistance of a conductive plug that connects a wiring layer and an adjacent upper wiring layer is minimized by providing an enlarged portion at the lower end of the conductive plug.

Abstract: A capping layer of an insulator such as silicon oxynitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon oxynitride caps on the metal lines. After the formation of such void-free low k silicon oxide dielectric material between the closely spaced apart metal lines and the silicon oxynitride caps thereon, the structure is planarized to bring the level of the low k silicon oxide dielectric material down to the level of the tops of the silicon oxynitride caps on the metal lines. A further layer of standard k silicon oxide dielectric material is then formed over the planarized void-free low k silicon oxide dielectric layer and the silicon oxynitride caps.

Abstract: An integrated circuit device includes electrical conductors providing electrical communication between a substrate and a silicon chip. The silicon chip has first electronics and second electronics. The second electronics are for operating at higher frequencies than the first electronics. A first portion of electrical conductors are in communication with the first electronics and a second portion of electrical conductors are in communication with the second electronics. A first medium is positioned adjacent to the first portion of electrical conductors and a second medium is positioned adjacent to the second portion of electrical conductors. The second medium is different from the solid first medium.

Abstract: A semiconductor device having a contact using a crack-protecting layer and a method of forming the same are provided. The crack-protecting layer formed of a dielectric material is formed on an interlayer dielectric layer. The crack-protecting layer relieves or absorbs residual stress generated on a conductive layer used in forming a contact plug. Thus, a contact can be formed without damage to the interlayer dielectric layer due to residual stress.

Abstract: Provided is a semiconductor device having a multi-level metallization. The device includes a semiconductor substrate having an active area, a first insulating layer deposited on the substrate, and first and second contact holes penetrating the first insulating layer exposing a predetermined surface of the active area. First and second conductive plugs are formed in the first and second contact holes, respectively. First and second conductive patterns are spaced a predetermined distance on both sides of the second conductive plug. The first conductive pattern is connected to the first conductive plug. An etching prevention layer and a second insulating layer are sequentially formed on the resultant structure. A third contact hole penetrates the second insulating layer and the etching prevention layer exposes a predetermined surface of the first conductive pattern. A fourth contact hole penetrates the second insulating layer and the etching prevention layer to expose the surface of the second conductive plug.

Abstract: A microelectromechanical system is fabricated from a substrate having a handle layer, a silicon sacrificial layer and a device layer. A micromechanical structure is etched in the device layer and the underlying silicon sacrificial layer is etched away to release the micromechanical structure for movement. One particular micromechanical structure described is a micromirror.

Abstract: Copper or a low resistivity copper alloy is initially deposited to fill relatively narrow openings leaving relatively wider openings unfilled. A copper alloy having improved electromigration resistance with respect to copper is then selectively deposited to fill the relatively wider openings, thereby improving electromigration resistance without increasing narrow line resistance. Embodiments include annealing after filling the relatively narrow openings and before filling the relatively wider openings, thereby reducing void formation in narrow lines.

Abstract: A semiconductor device of a SOI (silicon on insulator) structure includes a P-type silicon support substrate, a first insulating layer formed on the semiconductor support substrate, and an SOI layer formed on the first insulating layer. A first hole is formed to penetrate through the semiconductor layer and the first insulating layer, and a P-type polysilicon layer is filled in the first hole so that the P-type polysilicon layer is electrically connected to the semiconductor support substrate. A second insulating layer is formed on the SOI layer. A second hole is formed to penetrate through the second insulating layer in alignment with the first hole, and an aluminum electrode is formed on the second insulating layer to fill the second hole, so that the aluminum electrode is electrically connected through the P-type polysilicon layer to the silicon support substrate. Thus, the potential of the silicon support substrate can be fixed through the aluminum electrode formed on the SOI layer side.

Abstract: Structures and methods are provided for absorbing stress between a first electrical structure and a second electrical structure connected together, wherein the first and second structures have different coefficients of thermal expansion. A dielectric material is disposed on at least one of the first and second electrical structures. This dielectric material is a low modulus material which has a high ultimate elongation property (LMHE dielectric). Preferably, the LMHE dielectric has a Young's modulus of less than 50,000 psi and an ultimate elongation property of at least 20 percent. The LMHE dielectric can be photo patternable to facilitate formation of via openings therein and a metal layer is formed above the LMHE dielectric which has conductors capable of expanding or contracting with the dielectric.

Abstract: The present invention relates to a semiconductor memory device having a SRAM in which a memory cell comprises a pair of transmission transistors and a flip-flop circuit containing a pair of driver transistors and a pair of load transistors, wherein: a first conductive film interconnection formed from a first conductive film which is set on a semiconductor substrate, constitutes respective gate electrodes of said driver transistors, load transistors and transmission transistors; an inlaid interconnection set in a first insulating film lying on said semiconductor substrate, constitutes one of a pair of local interconnections cross-coupling a pair of input/output terminals in said flip-flop circuit; and a second conductive film interconnection formed from a second conductive film which is set on a second insulating film lying on said first insulating film, constitutes the other one of said pair of local interconnections.

Abstract: A pad metal film used to fit a conductor for external connection composed of a bump-like or wire-like conductor can be formed by reduced numbers of processes. A semiconductor device is so configured that a trench for interconnect with its diameter of about 50 &mgr;m and its depth of about 2 &mgr;m is formed on a protective insulating film, formed on a semiconductor substrate, with a thickness of 3 to 4 &mgr;m, and in the trench for interconnect is imbedded an uppermost-layered copper wiring through a first barrier metal film composed of a titanium nitride with a thickness of about 50 nm. Furthermore, approximately in the center region of the upper-layered copper wiring is imbedded a copper pad film through a second barrier metal film with a thickness of about 70 nm.

Abstract: In a semiconductor device, a plurality of linear semiconductors of a predetermined length, on which electronic element are formed, are aligned laterally and in parallel. A semiconductor assembly apparatus for assembling the semiconductor device, aligns the linear semiconductors in parallel via an arranging member. The linear semiconductors are interconnected by a connecting member in the semiconductor assembly apparatus.

Abstract: A cylindrical, electrical insulating region is formed in a circuit substrate made of a semiconductor substrate to continuously extend from the upper surface to the lower surface of the semiconductor substrate and be closed in a plane parallel to the surface of the semiconductor substrate. The electrical insulating region is formed by an insulating region made of a heat-resistant insulating material. The insulating region is formed by forming a through hole or trench in the circuit substrate and forming an oxide film or nitride film on the wall surface of the hole or trench or filling it with an insulating material. When the trench is formed, the substrate is thinned by polishing or the like until the trench appears on the upper and lower surfaces of the substrate after the insulating region is formed. The region surrounded by the insulating region functions as an electrode when the conductivity of the region is increased by diffusing an impurity in it.

Abstract: A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns are formed by drilling holes in the monocrystalline substrate and annealing the monocrystalline substrate to form empty-spaced patterns of various geometries. The empty-spaced patterns are then connected through vias with surfaces of the monocrystalline substrate. The empty-spaced patterns and their respective vias are subsequently filled with conductive materials.

Abstract: A transistor device is disclosed, having an insulating material disposed between the gate electrode and the drain and source lines, wherein the dielectric constant of the insulating material is 3.5 or less. Accordingly, the capacitance between the gate electrode and the drain and source lines can be reduced, thereby improving signal performance of the field effect transistor with decreased cross talk noise.

Abstract: A process of removing excess conductive material from the exposed surface of a dielectric layer, the process comprising the steps of forming a shield layer on the dielectric layer, forming a sacrificial layer on top of the shield layer, depositing the conductive material on top of the sacrificial layer so that the conductive material is positioned within cavities in the dielectric material, and then using chemical mechanical planarization to remove the excess conductive material and the sacrificial layer. The use of a sacrificial layer interposed between the shield layer and the excess conductive material allows for chemical mechanical planarization to fully remove the sacrificial layer to facilitate more uniform removal of excess conductive material.

Abstract: A semiconductor integrated circuit comprising a first circuit block including an oscillation circuit considered to be a noise generator and a second circuit block including circuits considered to be easily affected by a noise generated by the oscillation circuit, being most likely led to a malfunction are created on a single semiconductor substrate with the first and second circuit blocks separated from each other. To put it more concretely, the first and second circuit blocks are respectively created in a first island area and a second island area on the surface of the semiconductor substrate. The first and second island areas are each enclosed by an insulating isolation band. A low-resistance semiconductor area is created in a base area excluding locations occupied by active elements in the first and second island areas and is connected to a stable voltage terminal.

Abstract: A contact structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element where the contact is provided at an opening formed in an insulating layer which overlies at least in part the semiconductor layer. Further, the opening has its surface edges, walls and bottom coated with a metal layer and filled with an insulating layer.

Abstract: A radiation hardened memory device having static random access memory cells includes active gate isolation structures to prevent leakage currents between active regions formed adjacent to each other on a substrate. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a voltage terminal resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

Abstract: The present invention provides methods of manufacturing a field oxide isolation structure over a semiconductor. One of the methods includes the steps of: (1) depositing a first stack-nitride sublayer over the semiconductor at a first deposition rate and (2) subsequently depositing a second stack-nitride sublayer over the first stack-sublayer at a second deposition rate that is either greater or less than the first deposition rate. The first and second deposition rates provide first and second stack-nitride sublayers that cooperate to form a relatively thin, uniform thickness of the field oxide isolation structure over the semiconductor and provide a stress-accommodating system within the semiconductor. The varying rates of deposition and accompanying changes in mixture ratio, produce a stack that is better able to absorb stress, has greater uniformity and is far less subject to the disadvantageous phenomenon of stack-lifting, particularly encountered in semiconductor having a PADOX layer deposited thereon.

Abstract: A semiconductor device and a method of manufacturing the same are provided which are novel and fully improved and are capable of lowering satisfactorily a high-frequency resistance or direct current resistance in a signal line. The semiconductor device is composed of a semiconductor substrate on which predetermined circuit devices are mounted, an insulating film formed on the substrate in a manner that it covers the circuit devices and a conductive path formed on the insulating film to electrically connect the circuit devices. A concave trench is formed in a predetermined position on the semiconductor substrate and the conductive path is formed at a bottom of the concave trench in a manner that it extends along the concave trench, with interlayer dielectrics interposed between conductive layers constituting the conductive path.

Abstract: Within a method for forming a microelectronic fabrication, there is first provided a substrate. There is then formed over the substrate a microelectronic device passivated with a patterned first dielectric layer in turn annularly surrounded by a patterned second dielectric layer. There is also formed over the substrate a patterned conductor layer separated from the microelectronic device by the patterned first dielectric layer and the patterned second dielectric layer. Within the method: (1) the patterned first dielectric layer is formed from a first dielectric material having a first diffusion coefficient with respect to a conductor material from which is formed the patterned conductor layer; (2) the patterned second dielectric layer is formed from a second dielectric material having a second diffusion coefficient with respect to the conductor material from which is formed the patterned conductor layer; and (3) the first diffusion coefficient is greater than the second diffusion coefficient.

Abstract: A semiconductor apparatus includes a functional block that performs necessary functions for the proper operation; a functional signal line that is connected to the functional block to transmit a functional signal; and an enable signal line to supply an enable signal to the functional block. The enable signal line includes a part that is formed on an upper layer of the functional signal line.

Abstract: A three-dimensional integrated circuit and fabrication process is provided for producing active and passive devices on various levels of the integrated circuit. The present process is particularly suited to interconnecting a source of one transistor to a drain of another to form series-connected transistors often employed in core logic units. A junction of an underlying transistor can be connected to a junction of an overlying transistor, with both transistors separated by an interlevel dielectric. The lower transistor junction is connected to the upper level transistor junction using a plug conductor. The plug conductor and, more specifically, the mutually connected junction, is further coupled to a laterally extended interconnect. The interconnect extends from the mutual connection point of the plug conductor to a substrate of the overlying transistor.

Abstract: A backside interconnect structure is used to deliver power through the substrate to the front side of an integrated circuit. One or more power planes are formed on the backside of the substrate and coupled to power nodes on the front side by deep vias in the substrate. In a specific embodiment of the invention, power planes are coupled through the substrate to front side metal lines, well taps and external connection points. Placing power planes on the opposite side of the substrate from the signal interconnects allows the use of low dielectric constant materials between signal lines, while using high dielectric constant materials between power planes thus increasing decoupling capacitance without increasing parasitic capacitance between signal lines.

Abstract: A fast-response semiconductor memory which can avoid noises from over-macro through wiring affecting macro wiring and reduce the parasitic capacitance appearing on the macro wiring as well. The semiconductor memory has a shield layer between RAM macro wiring inside a macro and through wiring over the macro. The shield layer has a plurality of conductive layers arranged parallel to each other at a pitch of W1, the conductive layers extending in the direction orthogonal to the RAM macro wiring. For an appropriate length of the RAM macro wiring, this shield layer is provided so that the pitch W1 of the conductive layers is equal to or smaller than P1, where P1 is a pitch of the conductive layers at which the interlayer capacitance between the RAM macro wiring and the shield layer becomes equal to the interlayer capacitance between the RAM macro wiring and the over-macro through wiring.

Abstract: The connection element in an integrated circuit has a layer structure arranged between two conductive structures. The layer structure has a dielectric layer which can be destroyed by application of a predetermined voltage. At least one conductive structure is composed of tungsten. The conductive structure adjoins a conductive layer made of tungsten or a tungsten compound, which is a constituent part of the layer structure and which adjoins the dielectric layer.

Abstract: To provide a conducting path between the metal—0 layer and a metal—1 interconnect layer, two layers with conducting plugs were necessary in the prior art. In the present invention, the conducting regions electrically coupling two regions of the integrated circuit are formed at the same time as the formation of the conducting plugs coupling selected portions of the integrated circuit with the metal—1 interconnect layer. The conducting regions, as with the conducting plugs, extend to surface of the insulating layer upon which the metal—1 interconnect paths are patterned. Using this technique, process steps required in the prior art can be eliminated. This process has the limitation that the metal—1 interconnect layer can not be formed over the conducting regions.

Abstract: A process for forming a device isolation region comprising the steps of: forming a pad oxide film and a silicon nitride film on a semiconductor substrate; removing the pad oxide film and the silicon nitride film on a region for device isolation and forming a trench in the semiconductor substrate by etching using the remaining pad oxide film and silicon nitride film as an etching mask; forming a first oxide film at least on the bottom and sidewalls of the trench and below the pad oxide film under an end portion of the silicon nitride film using the silicon nitride film as a mask resistant to oxidization; forming a gap between the silicon nitride film and the semiconductor substrate by removing the first oxide film on the bottom and the sidewalls of the trench and the first oxide film and the pad oxide film below the end portion of the silicon nitride film by etching using the silicon nitride film as an etching mask; forming a second oxide film at least on the bottom and the sidewalls of the trench and in the g

Abstract: Silicon-on-insulator (SOI) islands are formed in a silicon substrate. A first set of trenches is formed in the silicon substrate, leaving laterally-isolated rows of silicon between the trenches. The first set of trenches is then filled with silicon oxide. A second set of trenches is then formed in the silicon substrate at a direction orthogonal to the first set of trenches. Silicon nitride is then deposited over the sidewalls of the second set of trenches. An isotropic chemical etch is then used to fully undercut narrow the laterally-isolated rows of silicon between the second set of trenches to form evacuated regions beneath silicon islands. A subsequent oxidation step fills the evacuated regions to form the SOI islands.

Abstract: There are provided a semiconductor device which can prevent short-circuit of the contact plugs and prevent exposure of wirings to ensure sufficient reliability even if level difference is caused in device isolation regions, and a method of manufacturing the same. Device isolation regions 13 are formed on a semiconductor substrate 11 to partition the semiconductor substrate 11 into a plurality of device regions 12. Then, word lines 14 are formed on the semiconductor substrate 11, and then peripheral regions of the word lines 14 are covered with a protection film. Then, impurity diffusion regions formed in the device regions 12, and then a plug insulating film is formed on an overall upper surface of the substrate 11. Then, opening portions 18a for connecting end portions of the device regions 12 are formed in the plug insulating film.

Abstract: The conductor for a given signal in an integrated circuit (IC) is shielded from electromagnetic coupling with one or more other, potentially noisy on-chip signals by shielding structure that essentially surrounds the signal conductor in a Faraday cage. In one embodiment, the signal conductor lies in the outermost metal layer in the IC. In that case, the shielding structure is a pair of adjacent shielding conductors lying on either side of the signal conductor within the outermost metal layer and a subtending shielding conductor lying in a metal layer below the signal conductor and the two adjacent conductors, where the subtending conductor is electrically connected to each of the adjacent conductors via interlevel interconnects, but there are no active components in the IC that draw current from the shielding conductors. When configured for signal processing, the three shielding conductors are connected either directly or indirectly to a quiet external reference.

Abstract: This invention provides an in situ low temperature, two step deposition HDP-CVD process separated by a cooldown period, for forming an inter-metal dielectric passivation layer for an integrated circuit structure. Said process mitigating metal line defects such as distortion or warping caused by excessive heat generated during the etching/deposition process.

Abstract: An isolator having a driver circuit which responsive to an input signal drives appropriate signals into one or more coils which are magnetically coupled to one or more corresponding MR or GMR elements whose resistance is variable in response to the magnetic field applied by the coil(s), and an output circuit that converts the resistance changes to an output signal corresponding to the input signal. A Faraday shield is interposed between the coil(s) and the MR or GMR elements. Common mode transients applied to the driver are capacitively coupled from the coil(s) into the Faraday shield and therethrough to ground, instead of into the MR elements. A second Faraday shield may be disposed in spaced relationship with the first Faraday shield and referenced to the potential of the MR elements for even greater common mode rejection. The entire structure may be formed monolithically as an integrated circuit on a single substrate, for low cost, small size, and low power consumption.

Abstract: Silicon is formed at selected locations on a substrate during fabrication of selected electronic components. A dielectric separation region is formed within the top silicon layer, and filled with a thermally conductive material. A liner material may be optionally deposited prior to depositing the thermally conductive material. In a second embodiment, a horizontal layer of thermally conductive material is also deposited in an oxide layer or bulk silicon layer below the top layer of silicon.

Abstract: Narrow and wide, planar field isolation region (72, 74, 152, 172, 182) is formed by forming trenches (52, 54) within a substrate (10). For wide, planar field isolation regions (72, 152, 172, 182), the trenches (52) define at least one mesa (76, 150, 170, 180) within the field isolation region (72, 152, 172, 182). The trenches (52, 54) are filled with a material (62) that is polished or etched to form the planar field isolation region (72, 74, 152, 172, 182) where the wide, planar field isolation regions (72, 152, 172, 182) include the mesa(s) (76, 150, 170, 180). Etching can be used or by polishing with minimal, if any, dishing occurs because the widths of the trenches (52, 54) are kept relatively narrow (usually no more than five microns wide). Mesas (180) within a wide, planar field isolation region (182) can form linguistic characters to better identify the part number or mask set of the device.

Abstract: Disclosed is a semiconductor diode structure, and method for making semiconductor diode structures for suppressing transistor gate oxide plasma charging damage. The semiconductor diode structure includes a shallow trench isolation region that is configured to isolate an active region of a semiconductor substrate. A doped polysilicon electrode having a first end and a second end. The doped polysilicon electrode is defined in the shallow trench isolation region and the first end is configured to be in electrical contact with the semiconductor substrate. The diode structure further includes a polysilicon gate that has an underlying gate oxide. The polysilicon gate is defined over the active region and extends over part of the shallow trench isolation region so as to make electrical interconnection between the polysilicon gate and the second end of the doped polysilicon electrode.

Abstract: An LSI semiconductor device having a device isolation structure and a method of fabricating the isolation structure are presented. The device is a buried-type field-shielding device which is fabricated in non-active regions of the LSI circuit, and includes field-shield insulator film formed on the interior walls of trench cavities formed on the substrate and the field-shield electrodes buried within the trench cavity. Unlike the conventional buried-type isolation devices, the top surface of present isolation structure is level with the upper surface of the substrate. Therefore, this device structure utilizes the interior space of the substrate rather than the surface area of the substrate as in the conventional field-shield isolation structure.

Abstract: A novel dielectric composition is provided that is useful in the manufacture of integrated circuit devices and integrated circuit packaging devices. The dielectric composition is prepared by imidizing and curing an oligomeric precursor compound comprised of a central polybenzoxazole, polybezothiazole polyamic acid ester segment end-capped at each terminus with an aryl-substituted acetylene moiety such as an ortho-bis(arylethynyl)aryl group, e.g., 3,4-bis(phenylethynly)phenyl. Integrated circuit devices, integrated circuit packaging devices, and methods of synthesis and manufacture are provided as well.

Abstract: A semiconductor device is disclosed, together with a fabricating method therefor. The semiconductor device has an etch barrier structure, made with SiN or SiON, which is formed on an element-isolating region alongside an active region. Although there is an alignment error which causes the element-isolating region to be exposed, the etch barrier structure protects the element-isolating region from being etched when carrying out the etching processes for contact holes in a semiconductor memory cell. Thus, while preventing the deterioration of element-isolation properties, the etch barrier structure can affords a larger allowable alignment error in the etching processes for contact holes, so it is possible to make a small active region and thus, highly integrate semiconductor devices.

Abstract: An isolation structure capable of preventing deterioration of breakdown voltage of a semiconductor device is obtained. The isolation structure, positioned between first and second conductive regions formed on a major surface of a semiconductor substrate for electrically insulating the first and second conductive regions from each other, includes a first conductor formed on a position deeper than the major surface of the semiconductor substrate, an insulator positioned in a direction opposite to that of the position of the first conductive region as viewed from the first conductor and formed on a position deeper than the major surface of the semiconductor substrate and a second conductor positioned in a direction opposite to that of the position of the first conductor as viewed from the insulator and formed on a position deeper than the major surface of the semiconductor substrate.

Abstract: Disclosed is a coaxial tube wiring structure (and method of making) of a semiconductor memory device for shielding a conductive film that transmits a signal. The coaxial tube structure includes: a plurality of signal conductive films formed on a substrate; and an arbitrary conductive film which shields the upper and lower surfaces and both sides of the signal conductive film, which is insulated from the signal conductive film by an insulating film, and to which ground voltage is applied.

Abstract: A method of fabricating integrated circuitry comprises forming a conductive line having opposing sidewalls over a semiconductor substrate. An insulating layer is then deposited. The insulating layer is etched proximate the line along at least a portion of at least one sidewall of the line. An insulating spacer forming layer is then deposited over the substrate and the line. It is anisotropically etched to form an insulating sidewall spacer. A method of forming a local interconnect comprises forming at least two transistor gates over a semiconductor substrate. A local interconnect layer is deposited to overlie at least one of the transistor gates and interconnect at least one source/drain region of one of the gates with semiconductor substrate material proximate another of the transistor gates.

Abstract: A method for fabricating an integrated circuit is presented wherein a trench is patterned in a field region of a semiconductor substrate. The trench is defined within the semiconductor substrate by a trench floor and trench sidewalls. A liner that primarily comprises nitride is formed upon the trench floor and sidewalls. The liner is then oxidized. A trench dielectric may be formed within the trench and planarized to complete the isolation structure.

Abstract: A MOSFET has a buried shield plate under the gate and over the drain with the gate being formed on the periphery of the buried shield plate as a self-aligned structure with minimal or no overlap of the gate over the shield plate. Methods of fabricating the MOSFET are disclosed.